Patent Application
20240381658
The following relates to the integrated circuit (IC) arts, ferroelectric tunnel junction (FTJ) arts, ferroelectric random access memory (FeRAM) arts, and related arts.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
A ferroelectric tunnel junction (FTJ) includes a thin ferroelectric layer made of a ferroelectric material, which is interposed between top and bottom electrodes. The remnant polarization of the ferroelectric layer can be switched between a positive remnant polarization often denoted as +Pr and a negative remnant polarization often denoted as −Pr. The electrical resistance of electrical current tunneling through the FTJ depends strongly on the polarization (+Pr or −Pr), so that measurement of current flow through the FTJ enables readout of the stored remnant polarization. The change in polarization between the +Pr state (which may, for example encode either a logical “1” or a logical “0”) and the −Pr state (which then encodes the other of logical “0” or logical “1”) is 2Pr. The plurality of layers making up the FTJ may include an additional interfacial layer that is interposed between the top and bottom electrodes and is in contact with the ferroelectric layer. The interfacial layer is chosen to engineer the characteristics of the tunnel barrier. A ferroelectric random access memory (FeRAM) includes a FTJ and a transistor, such as a field-effect transistor (FET), which is used to read and write bit values to the FeRAM which serves as nonvolatile storage for the FeRAM.
The fabrication process for fabricating an FTJ includes forming the plurality of layers (top and bottom electrodes with the ferroelectric layer and optional interfacial layer interposed therebetween) and annealing the plurality of layers at a temperature high enough to induce ferroelectric phase crystallization in the ferroelectric material of the ferroelectric layer. However, ferroelectric crystallization can be more difficult at the periphery of the ferroelectric layer. Less effective ferroelectric phase crystallization at the periphery of the ferroelectric layer can lead to local variation of the 2Pr value across the area of the ferroelectric layer, and the resulting nonuniformity in the ferroelectric phase percentage across the ferroelectric layer can in turn lead to nonoptimal FTJ performance, including problems such as electrical current leakage, variable capacitance, and/or so forth.
Without being limited to any particular theory of operation, it is believed ferroelectric phase crystallization during the annealing may be promoted by stress imposed on the ferroelectric layer by a difference in the coefficient of thermal expansion (CTE) of the ferroelectric material and the CTE of surrounding material, notably the top and bottom electrodes. As the top electrode may not cover the entire area of the ferroelectric layer, this can be expected to result in reduced CTE difference-induced stress at the periphery of the ferroelectric layer, leading to the annealing being less effective at inducing ferroelectric phase crystallization at the periphery.
Another challenge in fabrication of FTJs and associated devices such as FeRAM arrays is achievement of effective isolation of the FTJ from neighboring devices, such as integrated circuitry located at the periphery of an FeRAM array. Sidewalls of the FTJ are typically coated with a dielectric layer, but may be insufficient to avoid electromagnetic interference in the FTJ operation from peripheral devices.
In embodiments disclosed herein, these problems are addressed by disposing a conformal dielectric spacer the peripheral area of the ferroelectric layer that surrounds the top electrode. The conformal dielectric spacer may be made of a material such as tantalum oxide (TaO) or another metal oxide, which has a large difference in CTE compared with the ferroelectric layer which may, for example, comprise hafnium zinc oxide (HZO). The conformal dielectric spacer may also coat a sidewall of the top electrode, thus having an L-shaped cross-section. Additionally or alternatively, an outer conformal dielectric spacer may be provided, such as a TaO or other metal oxide spacer, disposed on a sidewall of the FTJ including on a sidewall of the ferroelectric layer. The conformal dielectric spacer or spacers are expected to improve ferroelectric phase crystallization during the annealing by imposing additional stress on the peripheral area of the ferroelectric layer due to the difference between the CTE of the conformal dielectric spacer and the CTE of the ferroelectric layer. As a non-limiting illustrative example, HZO has a CTE of about 30 μm/(m·K) while TaO has a CTE of about 3.6 μm/(m·K), that is, a large difference in CTE of about 88%. Furthermore, the conformal dielectric spacer or spacers are expected to improve isolation of the FTJ from peripheral devices by providing additional material coating the sidewall of the FTJ including the sidewall of the ferroelectric layer. Thus, the conformal dielectric spacer(s) advantageously isolate the FTJ cells from periphery devices, presenting the FTJ-based memory from being affected by logic processes.
With reference to
The FTJ 10 comprises a bottom electrode 20, a top electrode 22, and a ferroelectric layer 24 disposed between the bottom electrode 20 and the top electrode 22. In some embodiments, the FTJ further includes an interfacial layer (not shown) that is also disposed between the bottom electrode layer 20 and the top electrode layer 22 and is in contact with the ferroelectric layer 24. The interfacial layer, if included, promotes electrical carrier tunneling and may be chosen to optimize performance of the FTJ 10. Moreover, in some embodiments the ferroelectric layer 24 could be a stack of two or more ferroelectric layers spaced apart by interfacial layers. The bottom and top electrodes 20 and 22 can be, for example, titanium nitride (TiN) or a TiN/tantalum nitride (TaN) stack, by way of nonlimiting illustrative example.
In the illustrative example of
With continuing reference to
With reference now to
In the illustrative example of
Moreover, although not shown by perspective views, referencing
Notably, the inner conformal dielectric spacer 40 includes the first leg 401 that is in intimate contact (e.g. deposited directly onto) the peripheral area of the ferroelectric layer 24 (i.e., on the peripheral area 24P indicated in
Similarly, the outer conformal dielectric layer 42 includes the second leg 422 that is in intimate contact (e.g. deposited directly onto) the sidewall of the ferroelectric layer 24. If the outer conformal dielectric spacer 42 is made of a material with a significantly lower CTE than the CTE of the material of the ferroelectric layer 24, then during the ferroelectric phase crystallization by annealing the outer conformal dielectric spacer 42 (and especially the second leg 422 thereof) is positioned to apply stress to the peripheral area 24P of the ferroelectric layer 24 during the annealing (in this case, via the sidewall thereof). This stress is believed to promote formation of the ferroelectric phase during the annealing.
In further detail, the ferroelectric layer 24 is made of a ferroelectric material such as hafnium oxide doped with zinc, silicon, yttrium, aluminum, gadolinium, lanthanum, or strontium. As a specific example, when zinc is the dopant the material is sometimes referred to as hafnium zinc oxide (HZO), corresponding to a composition Hf1-xZrxO2 with x typically in a range of 0.4≤x≤0.7. More generally, the composition could be Hf1-xDxO2 where the dopant D can be zinc, silicon, yttrium, aluminum, gadolinium, lanthanum, or strontium, for example, and the composition fraction x is chosen to provide a desired ferroelectric property. In other embodiments, the ferroelectric layer 24 may comprise another type of ferroelectric material such as SrBi2Ta2O9, PbZrxTi1-xO3, or BaTiO3. These are merely some nonlimiting illustrative examples.
In one fabrication process, the ferroelectric layer 24 in its as-deposited state is an amorphous material, or a polycrystalline or single crystal material with various crystal phases. For proper operation of the ferroelectric tunnel junction, a sufficient portion of the ferroelectric layer 24 should be in a ferroelectric crystal phase. For the example of HZO, a suitable ferroelectric crystal phase is an orthorhombic phase, which is non-centrosymmetric with oxygen atoms are arranged to be able to respond to form intrinsic polarizations in response to external electric fields, thereby being capable of being switched by application of electric field between positive remnant polarization (+Pr) and negative remnant polarization (−Pr) states. The ferroelectric behavior of the orthorhombic crystal phase of HZO is a consequence of its non-centrosymmetric However, the as-deposited layer 24 may be amorphous, or may have a mixture of phases, e.g. a mixture of tetragonal and/or monoclinic and/or orthorhombic crystal phases. Characterization techniques such as X-ray diffraction (XRD) and/or electron backscatter diffraction (EBSD) can be used to assess the fractional phases of the layer 24.
To perform as a ferroelectric tunnel junction, the ferroelectric layer 24 should have a sufficiently high fraction of its material in a ferroelectric crystal phase (e.g., in the orthorhombic phase in the case of HZO or some other hafnium oxide-based ferroelectric materials). To induce the material of the ferroelectric layer 24 into the appropriate ferroelectric crystal phase, ferroelectric phase crystallization by annealing is typically performed at a suitably high temperature for a sufficient time interval (e.g., ˜550° C. for about 5 minutes may be sufficient in some cases). For examples in which the ferroelectric layer 24 comprises HZO (or another suitably doped hafnium oxide composition), the annealing promotes ferroelectric orthorhombic phase crystallization in the ferroelectric HZO layer 24. By way of nonlimiting illustrative example, the ferroelectric phase crystallization produced by the anneal may be at least 35% orthorhombic crystal phase, or at least 50% orthorhombic crystal phase, or at least 70% orthorhombic crystal phase, in some nonlimiting illustrative examples. The remainder of the HZO may, for example, be in a tetragonal phase and/or a monoclinic phase or so forth.
It is believed that ferroelectric phase crystallization during the annealing is promoted at least partly by the difference in CTE (hereinafter denoted as ΔCTE) between the CTE of ferroelectric layer 24 and the CTE of the surrounding material, such as the bottom electrode 20 and the top electrode 22. The ΔCTE imposes stress on the ferroelectric layer 24 which tends to preferentially bias the crystallization of the HZO material into the ferroelectric orthorhombic phase, over non-ferroelectric phases such as tetragonal or monoclinic phases.
However, as previously noted, because the top electrode 22 does not cover the peripheral area 24P of the ferroelectric layer 24, the periphery would ordinarily be under less stress due to difference in CTE during the anneal process than the central portion of the ferroelectric layer 24. As just described, however, the inner conformal dielectric spacer 40 and/or the outer conformal dielectric spacer 42 can provide additional difference in CTE-induced stress to the peripheral area 24P of the ferroelectric layer 24, so as to promote ferroelectric phase crystallization in the peripheral area 24P of the ferroelectric layer 24 during the annealing, thereby improving uniformity in the ferroelectric phase percentage across the ferroelectric layer 24 and thereby improving FTJ performance, such as providing for lower electrical current leakage, more uniform capacitance, and/or so forth.
In some embodiments, the ratio of the CTE of the peripheral conformal spacer 401 (and of the inner conformal spacer 40 as a whole) to the CTE of the ferroelectric layer is 0.67 or lower, as computed according to:
where CTEFe is the CTE of the ferroelectric material 24, and CTEconformal_spacer is the CTE of the conformal spacer 40 (or of the outer conformal spacer 42, if that outer spacer 42 is providing the peripheral ferroelectric phase crystallization enhancement). As a non-limiting illustrative example, HZO has a CTE of about 30 μm/(m·K) while TaO has a CTE of about 3.6 μm/(m·K), that is, ΔCTE of about 88%. As another example, the spacer 40 (or spacer 42) could comprise aluminum oxide (AlO) having a CTE about 8.1, providing ΔCTE of about73% respective to HZO. Other metal oxides, or other dielectric materials with suitable ΔCTE, are contemplated for use as the spacer 40 and/or spacer 42, such as silicon nitride (SiN, CTE˜3.3), silicon oxide (SiOx, CTE˜5.8), or so forth. Notably, because the conformal dielectric layer 40 is conformal and has intimate contact with the periphery of the ferroelectric layer 24 over its first portion 401, it is capable of effectively applying stress to the periphery of the ferroelectric layer 24 due to the ΔCTE during the anneal. Likewise, because the outer conformal dielectric layer 42 is conformal and has intimate contact with the periphery of the ferroelectric layer 24 over its second portion 422, it is capable of effectively applying stress to the periphery of the ferroelectric layer 24 due to the ΔCTE during the anneal. Hence, the inner conformal dielectric layer 40, the outer dielectric layer 42, or both, can be provided to effectively enhance ferroelectric phase crystallization in the periphery of the ferroelectric layer 24 during the anneal.
With returning reference to
Thus, the FTJ 10 described with reference to
In a device manufacturing method, the FTJ 10 is formed, including the bottom electrode 20, the top electrode 22, and the ferroelectric layer 24 disposed between the bottom electrode 20 and the top electrode 22. A peripheral area 24P of the ferroelectric layer 24 is not covered by the top electrode 22, and surrounds the sidewall of the top electrode 22. The dielectric material 32 is disposed in the space between the peripheral area 24P of the ferroelectric layer 24 and the sidewall of the top electrode 22. Additionally, at least one conformal metal oxide (or other dielectric) spacer 40 and/or 42 is deposited. This may include, prior to the disposing of the dielectric material 32, depositing the inner conformal metal oxide (or other dielectric) spacer 40 on the peripheral area 24P of the ferroelectric layer 24 and on the sidewall of the top electrode 22. Additionally or alternatively, after the disposing of the dielectric material 32, depositing the outer conformal metal oxide (or other dielectric) spacer 42 on the dielectric material 32 and on the sidewall of the peripheral area 24P of the ferroelectric layer 24. The FTJ 10 is annealed to induce ferroelectric phase crystallization in the ferroelectric layer 24 of the FTJ 10. The anneal is suitably performed after the depositing of the at least one conformal metal oxide (or other dielectric) layer 40 and/or 42, so that it can assist the ferroelectric phase crystallization in the peripheral area 24P of the ferroelectric layer 24 during the anneal by way of applying stress due to the difference in CTE between the ferroelectric layer 24 and the at least one conformal metal oxide (or other dielectric) layer 40 and/or 42.
With reference now to
With continuing reference to
In a step S3, a conformal dielectric layer 40L is disposed on tops and sidewalls of the top electrodes 22 and on a surface of the continuous ferroelectric layer 24L between the top electrodes 22. In the illustrative example, additionally a nonconformal dielectric layer 32L is deposited on the conformal dielectric layer 40L, which will be the source of the dielectric material 32. The result is shown in
In a step S4 FTJ cells are formed, each including a top electrode 22 of the array of top electrodes, a bottom electrode 20, and a ferroelectric layer 24 formed from the continuous ferroelectric layer 24L. The result is shown in
In a step S5, the outer conformal dielectric spacer 42 is formed on sidewalls of the formed FTJ cells 10 including on the dielectric material 32 disposed on the sidewall conformal spacer 402 and on the peripheral conformal spacer 401 of each FTJ cell 10. To this end, a conformal dielectric layer 42L is deposited over the entire surface including the FTJs 10 and the areas therebetween. The result is shown in
Thereafter, in a step S6 indicated in
In a step S7, the top metallization is performed, including depositing IMD 12, photolithographically defining via openings and filling with the vias Vx-1 and depositing the metal layer Mx. While
With reference now to
In the illustrative examples, the conformal dielectric spacer(s) 40 and/or 42 are employed to improve a ferroelectric tunnel junction (FTJ). However, the approach can be more generally applied to a magnetoresistive tunnel junction (MTJ), which may for example be used in a magnetoresistive random access memory (MRAM).
In the following, some further embodiments are described.
In a nonlimiting illustrative embodiment, a method of manufacturing a device is disclosed. The method includes: forming bottom electrodes electrically contacting a lower metallization layer, a continuous ferroelectric layer disposed over the bottom electrodes, and a top electrode layer disposed over the continuous ferroelectric layer; patterning the top electrode layer to form an array of top electrodes disposed on the continuous ferroelectric layer; disposing a conformal dielectric layer on tops and sidewalls of the top electrodes and on a surface of the continuous ferroelectric layer between the top electrodes; forming FTJ cells each including a top electrode of the array of top electrodes, a bottom electrode, and a ferroelectric layer formed from the continuous ferroelectric layer; and annealing to induce ferroelectric phase crystallization in the ferroelectric layers of the formed FTJ cells. A peripheral area of the ferroelectric layer of each formed FTJ cell is not covered by the top electrode and surrounds the sidewall of the top electrode. Each formed FTJ cell further includes a sidewall conformal spacer comprising the portion of the conformal dielectric layer disposed on the sidewall of the top electrode and a peripheral conformal spacer comprising the portion of the conformal dielectric layer disposed on the peripheral area of the ferroelectric layer.
In a nonlimiting illustrative embodiment, a device is disclosed, comprising: a ferroelectric tunnel junction (FTJ) including a bottom electrode, a top electrode, and a ferroelectric layer disposed between the bottom electrode and the top electrode, wherein a peripheral area of the ferroelectric layer is not covered by the top electrode and surrounds a sidewall of the top electrode; and a conformal dielectric spacer disposed on the peripheral area of the ferroelectric layer and on the sidewall of the top electrode. The conformal dielectric spacer has an L-shaped cross-section in a section of the FTJ, the L-shaped cross-section of the conformal dielectric spacer including a first leg corresponding to a first portion of the conformal dielectric spacer disposed on the peripheral area of the ferroelectric layer and a second leg corresponding to a second portion of the conformal dielectric spacer disposed on the sidewall of the top electrode.
In a nonlimiting illustrative embodiment, a method of manufacturing a device is disclosed. The method includes: forming a ferroelectric tunnel junction (FTJ) including a bottom electrode, a top electrode, and a ferroelectric layer disposed between the bottom electrode and the top electrode, wherein a peripheral area of the ferroelectric layer is not covered by the top electrode and surrounds a sidewall of the top electrode; disposing a dielectric material in a space between the peripheral area of the ferroelectric layer and a sidewall of the top electrode; depositing at least one conformal metal oxide spacer; and annealing the FTJ to induce ferroelectric phase crystallization in the ferroelectric layer of the FTJ. The depositing at least one conformal metal oxide spacer includes at least one of: (i) prior to the disposing of the dielectric material, depositing an inner conformal metal oxide spacer on the peripheral area of the ferroelectric layer and on the sidewall of the top electrode, and/or (ii) after the disposing of the dielectric material, depositing an outer conformal metal oxide spacer on dielectric material and on a sidewall of the peripheral area of the ferroelectric layer.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
