FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE

Abstract

A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, features and advantages of the invention are understood within the context of the Description of the Preferred Embodiment, as set forth below. The Description of the Preferred Embodiment is understood within the context of the accompanying drawings, that form a material part of this disclosure, wherein:

FIG. 1 to FIG. 8 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a field effect transistor device in accordance with a first embodiment of the invention.

FIG. 9 to FIG. 17 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in fabricating a field effect transistor device in accordance with a second embodiment of the invention.

Claims

1. A semiconductor structure comprising: a semiconductor substrate having a channel region separating a pair of source/drain regions; anda gate electrode located over the channel region, where a top surface of the gate electrode is no higher than a top surface of the pair of source/drain regions.

2. The semiconductor structure of claim 1 wherein the top surface of the gate electrode is lower than the top surface of the pair of source/drain regions.

3. The semiconductor structure of claim 1 wherein the gate electrode is an element of a planar field effect transistor.

4. The semiconductor structure of claim 1 further comprising a spacer layer laterally adjacent the gate electrode, where a height of the spacer layer is also no higher than the top surface of the pair of source/drain regions.

5. The semiconductor structure of claim 1 wherein the gate electrode comprises a silicon gate electrode.

6. The semiconductor structure of claim 1 wherein the gate electrode comprises a silicide gate electrode.

7. The semiconductor structure of claim 1 wherein the gate electrode comprises a metal germanide.

8. The semiconductor structure of claim 1 wherein the pair of source/drain regions comprises a pair of intrinsic source/drain regions and a pair of raised source/drain layers located thereupon.

9. The semiconductor structure of claim 8 wherein the pair of raised source/drain layers imparts a mechanical stress with respect to the pair of intrinsic source/drain regions.

10. A method for fabricating a field effect transistor comprising: forming an extension region into a semiconductor substrate which includes at least a gate electrode of a first thickness thereon, the gate electrode serving as a mask;forming an intrinsic source/drain region into the semiconductor substrate while using the gate electrode and a horizontal spacer layer formed adjacent thereto as a mask; andetching the gate electrode to a second thickness which is less than the first thickness, thereby forming a reduced thickness gate electrode.

11. The method of claim 10 wherein the etching forms a reduced thickness silicon gate electrode.

12. The method of claim 11 further comprising the step of reacting the reduced thickness silicon gate electrode with a metal silicide forming metal to form a reduced thickness silicide gate electrode.

13. The method of claim 10 further comprising the step of forming a raised source/drain layer upon the semiconductor substrate while using at least the gate electrode and the spacer layer as a mask.

14. The method of claim 13 wherein the step of forming the raised source/drain layer upon the semiconductor substrate provides that a top surface of the raised source/drain layer is higher than a top surface of the reduced thickness gate electrode.

15. A method for fabricating a field effect transistor comprising: forming an extension region into a semiconductor substrate which includes at least a gate electrode stack thereon, the gate electrode stack serving as a mask, the gate electrode stack comprising a reduced thickness gate electrode, an etch stop layer thereupon and a vertical spacer layer further thereupon;forming an intrinsic source/drain region into the semiconductor substrate while using the gate electrode stack and a horizontal spacer layer formed adjacent thereto as a mask; andstripping the vertical spacer layer from the gate electrode stack while using the etch stop layer as a stop layer, and then further stripping the etch stop layer to expose the reduced thickness gate electrode.

16. The method of claim 15 wherein the stripping exposes a reduced thickness silicon gate electrode.

17. The method of claim 16 further comprising the step of reacting the reduced thickness silicon gate electrode with a metal silicide forming metal to form a silicide gate electrode.

18. The method of claim 15 further comprising the step of forming a raised source/drain layer upon the semiconductor substrate while using the gate electrode and the spacer layer as a mask.

19. The method of claim 18 wherein the step of forming the raised source/drain layer upon the semiconductor substrate provides that a top surface of the raised source/drain layer is higher than a top surface of the reduced thickness gate electrode.

20. The method of claim 18 further comprising the step of forming a silicide layer upon the raised source/drain layer.