Patent Application
20070267652
In the accompanying drawings:
A compound semiconductor according to the present invention corresponds to a III-V compound semiconductor. In addition to GaAs and GaN, gallium phosphide (GaP), gallium antimonide (GaSb), indium nitride (InN), and indium phosphide (InP) can also be used as the compound semiconductor. Further, as a semi-insulating substrate, a substrate composed of the GaAs or InP can be used.
Hereinafter, description will be made using the GaAs as an example of the III-V compound semiconductor.
As shown in
The undoped AlGaAs epitaxial layer is an intrinsic semiconductor in which a doped concentration of an n-type dopant is equal to or lower than 1×1016 cm−3.
Each of the undoped GaAs epitaxial layers is the intrinsic semiconductor in which the doped concentration of the n-type dopant is equal to or lower than 1×1016 cm−3.
The field-effect transistor 1 according to the first embodiment further includes two cap layers 7a and 7b, a source electrode 8, a drain electrode 9, a gate electrode 10 and a passivation layer 11. The cap layers 7a and 7b are formed of n+-type GaAs epitaxial layers grown on the gate buried layer 6, patterned, and separated by a predetermined distance from each other. The source electrode 8 is formed on the cap layer 7a. The drain electrode 9 is formed on the cap layer 7b. The gate electrode 10 controls a current flowing into the channel layer 4 between the source electrode 8 and the drain electrode 9, and a part of the gate electrode 10 is buried into the gate buried layer 6. The passivation layer 11 covers a surface excluding the source electrode 8 and drain electrode 9.
As shown in
In the gate electrode 10, a bottom face thereof is in contact with the gate contact layer 5, a lower side wall 24a is in contact with an inner wall of the through hole 21, and an upper side wall 24b is opposed to an inner wall of the recess 23 while intervening a gap.
Note that a thickness of the gate buried layer 6 with which the lower side wall 24a of the gate electrode 10 is in contact refers to a “recess region buried layer thickness” 26, hereinafter. Further, the gap between the upper side wall 24b of the gate electrode 10 and the inner side wall of the recess 23 opposed to each other refers to a “recess width” 27, hereinafter.
In the field-effect transistor 1 according to the first embodiment, the recess region buried layer thickness 26 is more than 0 nm and equal to or less than 50 nm, and the recess width 27 is more than 0 μm and equal to or less than 0.5 μm.
Next, a suitable range of the recess region buried layer thickness 26 will be described.
As described in the background of the invention section, a gate leakage current greatly depends on a buried layer thickness. The gate leakage current becomes smaller as the buried layer thickness reduces. To be specific, when the buried layer thickness was, for example, 20 nm, 40 nm, 50 nm, or 100 nm, a drain-gate voltage Vdg in a case where the gate leakage current Igd was 0.1 mA/mm was 22 V, 13 V, 10 V, or 6 V, respectively. The drain-gate voltage Vdg requires at least twice an operation voltage of 5 V, so the buried layer thickness is preferably equal to or less than 50 nm, thus allowing to attain the gate leakage current Igd of equal to or less than 0.1 mA/mm in a case where the drain-gate voltage is 10 V. This is also applied to the recess region buried layer thickness 26, so the recess region buried layer thickness 26 is preferably equal to or less than 50 nm.
In addition, when the recess region buried layer thickness 26 is set to 0 nm to expose the gate contact layer 5, a density of electrons to be captured is significantly increased because Al is likely to be oxidized on a surface of the AlGaAs forming the gate contact layer 5, which causes an expansion of a surface depletion layer and a reduction of a maximum drain current. Therefore, in consideration of a process margin, the recess region buried layer thickness 26 is preferably more than 10 nm so that the AlGaAs is not exposed.
Next, a suitable range of the recess width 27 will be described.
In each of first, second, third, and fourth examples, a field-effect transistor, which was the same as that of the first embodiment except that the recess 23 had the recess width 27 of 0.4 μm, 0.5 μm, 0.6 μm, or 1.0 μm, was produced and evaluated with respect to a pulse drain current characteristic. The pulse drain current characteristic was represented by a percentage obtained as follows. A gate voltage having a frequency of 1 MHz was applied to the gate electrode 10 and a source/drain voltage of 2 V was applied between the source electrode 8 and the drain electrode 9, thereby obtaining a pulse drain current value. Further, a DC gate voltage was applied to the gate electrode 10 and a source/drain voltage of 2 V was applied between the source electrode 8 and the drain electrode 9, thereby obtaining a DC drain current value. Then, a maximum value of the pulse drain current was compared to the DC drain current value.
In a case where the recess width 27 was 0.4 μm, 0.5 μm, 0.6 μm, or 1.0 μm, the pulse drain current characteristic was 86%, 80%, 73%, or 65%, respectively. As mentioned above, as the recess width 27 is increased, the pulse drain current characteristic is reduced. This is because the pulse drain current characteristic is greatly affected depending on whether a surface level is high or low, as compared with the DC drain current. This is also because, as the recess width 27 becomes large, the surface level is increased. The recess width 27 is preferably set to equal to or less than 0.5 μm because the pulse drain current characteristic is generally required to be equal to or more than 80%.
In order that the inner wall of the recess 23 is not in contact with the side wall of the gate electrode 10, the recess width 27 is required to be more than 0 μm.
Further, in some cases, a field-effect transistor formed of a compound semiconductor, which is used as a high output amplifier operating in a high frequency band, specifically, in K band or higher, has the gate electrode 10 and the cap layer 7b on the drain electrode 9 side which are separated by approximately 0.5 μm at minimum. The field-effect transistor can also be provided with the recess 23.
The field-effect transistor 1 according to the first embodiment and a field-effect transistor of a first comparative example which is the same as that according to the first embodiment except the gate buried layer 6 in which the doped concentration of the n-type dopant is 5×1016 cm−3 were produced and a breakdown voltage leakage current characteristic was obtained.
The breakdown voltage leakage current characteristic is obtained by measuring the drain-gate voltage Vdg applied between the drain electrode 9 and the gate electrode 10 when the gate leakage current Igd flowing through the gate electrode 10 and the drain electrode 9 is 0.1 mA/mm.
In the field-effect transistor 1 according to the first embodiment, the drain-gate voltage Vdg was 28 V when the gate leakage current Igd was 0.1 mA/mm. On the other hand, in the field-effect transistor of the first comparative example, the drain-gate voltage Vdg was 10 V when the gate leakage current Igd was 0.1 mA/mm. As described above, the gate leakage current of the field-effect transistor 1 according to the first embodiment is greatly suppressed. This is because the doped concentration of the n-type dopant in each of the gate buried layer 6 and the gate contact layer 5 is equal to or less than 1×1016 cm−3, regions of the gate buried layer 6 and the gate contact layer 5 which are in contact with the gate electrode 10 are likely to be depleted, and a leakage path in a reverse direction is made smaller. Accordingly, the gate leakage current flowing from the gate electrode 10 into the drain electrode 9 is suppressed.
In the field-effect transistor 1 as described above, only the lower side wall 24a of the gate electrode 10 which is buried in the gate buried layer 6 is in contact with the gate buried layer 6, so the gate leakage current is suppressed and the surface level of the gate buried layer 6 only by the recess width 27 affects the maximum drain current. Therefore, reduction in maximum drain current can be suppressed.
In addition, the gate buried layer 6 and the gate contact layer 5 are undoped and each have the doped concentration of equal to or less than 1×1016 cm−3, so the leakage path is made smaller and the gate leakage current can be suppressed.
A field-effect transistor 1B according to the second embodiment of the present invention is different from the field-effect transistor 1 according to the first embodiment in that the field-effect transistor 1B includes injection/anneal regions 30 in parts of a gate buried layer 6, a gate contact layer 5, and a channel layer 4 and does not include cap layers 7a and 7b. The other components of the field-effect transistor 1B are the same as those of the field-effect transistor 7 of the first embodiment, so the same components are denoted by the same reference numerals and the description thereof will be omitted.
As shown in
The injection/anneal regions 30 into which silicon is injected first as an n-type dopant are then subjected to activation anneal, thereby forming ohmic junction with the source electrode 8 and the drain electrode 9.
As described above, the silicon is injected into the regions 6a and 6b of the gate buried layer 6, on which the source electrode 8 and the drain electrode 9 are formed, respectively, then, the activation anneal and the ohmic junction between the source electrode 8 and the channel layer 4 and between the drain electrode 9 and the channel layer 4 are performed. Therefore, a resistance is not increased, but rather reduced. In particular, an increase in source resistance which causes a reduction in gain can be prevented.
Also, the injection/anneal regions 30 are provided in the gate contact layer 5, which can prevent an increase in resistance.
As described above, the gate buried layer 6 is formed of an undoped GaAs epitaxial layer and the gate contact layer 5 is formed of an undoped AlGaAs epitaxial layer, which can produce an effect of suppressing a gate leakage current and can prevent the increase in resistance.
Note that a component of the n-type dopant is not limited to silicon.
In addition, the provision of the injection/anneal regions 30 in the gate buried layer 6 can omit the cap layers 7a and 7b, which can simplify a process of forming the epitaxial layers and reduce a cost.
Note that a process of forming the silicon injection process and the ohmic layer forming process are added but an etching process of the cap layers 7a and 7b can be omitted, so the number of wafer processes is substantially the same.
In general, electric field concentration is likely to occur at a corner of the recess. In a region where the electric field concentration occurs, a polarized molecule such as water or an ion tends to concentrate, which easily leads to reaction or corrosion. Further, when a region having a square shape is highly doped, reaction is promoted compared with a case of an undoped region because sufficient electrons for reaction exist and the electric field concentration is likely to occur.
In the second embodiment, only the undoped region in the gate buried layer 6 corresponds to a region having the corner of the recess, which can improve moisture resistance of the surface.
A field-effect transistor 1C according to the third embodiment of the present invention is different from the field-effect transistor 1B according to the second embodiment in that the field-effect transistor 1C includes electron supply layers 40a and 40b and a channel layer 4B instead of the channel layer 4. The other components of the field-effect transistor 1C are the same as those of the field-effect transistor 1B of the second embodiment, so the same components are denoted by the same reference numerals and the description thereof will be omitted.
As shown in
An injection/anneal region 30B according to the third embodiment is formed by injecting silicon and performing an activation anneal with a rapid annealing technique, for example, a rapid thermal annealing technique. Note that the injection/anneal region may be applied to the field-effect transistor according to the first or second embodiment.
As described above, the injection/anneal region 30B is formed with the rapid annealing technique, so epitaxial layers thinner than those of the field-effect transistor 1B according to the second embodiment are laminated. Thus, the injection/anneal region 30B may be formed in the high electron mobility field-effect transistor, in which a width of the epitaxial layer itself changes during dopant activation anneal.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-141257 | May 2006 | JP | national |
