Field effect transistor

Abstract

A field effect transistor includes a first semiconductor layer made of a first group III-V nitride; a second semiconductor layer formed on the first semiconductor layer, made of a second group III-V nitride and having a gate recess portion for exposing the first semiconductor layer therein; and a gate electrode formed on the first semiconductor layer in the gate recess portion. A product of stress applied by the second semiconductor layer to the first semiconductor layer and the thickness of the second semiconductor layer is 0.1 N/cm or less.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a field effect transistor according to Embodiment 1 of the invention;

FIG. 2 is a flowchart of a simulation method for a piezoelectric charge density in the field effect transistor of Embodiment 1 of the invention;

FIG. 3 is a graph for showing the correlation between a product of stress and a thickness of a capping layer and an electron concentration in a channel region obtained in the field effect transistor of Embodiment 1;

FIG. 4 is a graph for showing the ranges of the stress of the capping layer and the thickness of the capping layer suitably employed in the field effect transistor of Embodiment 1;

FIG. 5 is a graph for showing the correlation between the thickness of the capping layer and resistance change obtained in the field effect transistor of Embodiment 1;

FIGS. 6A, 6B and 6C are cross-sectional views for showing procedures in a method for fabricating a field effect transistor according to Embodiment 1 of the invention;

FIG. 7 is a cross-sectional view of a field effect transistor according to Embodiment 2 of the invention;

FIGS. 8A, 8B, 8C and 8D are cross-sectional views for showing procedures in a method for fabricating a field effect transistor according to Embodiment 2 of the invention;

FIG. 9 is a cross-sectional view of a field effect transistor according to Embodiment 3 of the invention;

FIG. 10 is a graph for showing influence on stress of an angle between a portion of a capping layer corresponding to a sidewall of a gate recess portion and a top face of a barrier film in the field effect transistor of this invention;

FIGS. 11A, 11B, 11C and 11D are cross-sectional views for showing procedures in a method for fabricating a field effect transistor according to Embodiment 3 of the invention;

FIG. 12 is a cross-sectional view of a field effect transistor according to Embodiment 4 of the invention;

FIGS. 13A, 13B and 13C are cross-sectional views for showing procedures in a method for fabricating a field effect transistor according to Embodiment 4 of the invention;

FIGS. 14A and 14B are respectively a cross-sectional view of a field effect transistor according to Embodiment 5 of the invention and an enlarged cross-sectional view of a gate recess portion thereof;

FIG. 15 is a cross-sectional view of a simulation model used for evaluating a characteristic of the field effect transistor of Embodiment 5 of the invention;

FIGS. 16A and 16B are graphs for respectively showing a stress characteristic and an electron concentration characteristic of the field effect transistor of Embodiment 5 of the invention; and

FIGS. 17A, 17B, 17C and 17D are cross-sectional views for showing procedures in a method for fabricating a field effect transistor according to Embodiment 5 of the invention.

Claims

1. A field effect transistor comprising: a first semiconductor layer made of a first group III-V nitride;a second semiconductor layer formed on said first semiconductor layer, made of a second group III-V nitride and having a gate recess portion;a gate electrode formed on said first semiconductor layer in said gate recess portion; andohmic electrodes formed on said second semiconductor layer on both sides of said gate electrode,wherein a product of stress applied by said second semiconductor layer to said first semiconductor layer and a thickness of said second semiconductor layer is 0.1 N/cm or less at a gate recess side end of said second semiconductor layer.

2. The field effect transistor of claim 1, wherein said second semiconductor layer has a constant thickness.

3. The field effect transistor of claim 1, wherein said second semiconductor layer has a smaller thickness at the gate recess side end than beneath said ohmic electrodes.

4. The field effect transistor of claim 3, wherein said second semiconductor layer has a thickness reduced in a stepwise manner toward the gate recess side end.

5. The field effect transistor of claim 3, wherein said second semiconductor layer has a continuously reduced thickness in which thickness change becomes gradually smaller toward the gate recess side end.

6. A field effect transistor comprising: a first semiconductor layer made of a first group III-V nitride;a second semiconductor layer formed on said first semiconductor layer, made of a second group III-V nitride and having a gate recess portion;a gate electrode formed on said first semiconductor layer in said gate recess portion; andohmic electrodes formed on said second semiconductor layer on both sides of said gate electrode,wherein a thickness of said second semiconductor layer is reduced toward a gate recess side end thereof in such a manner that thickness change becomes smaller toward the gate recess side end.

7. The field effect transistor of claim 6, wherein the thickness of said second semiconductor layer is reduced in a stepwise manner.

8. The field effect transistor of claim 6, wherein the thickness of said second semiconductor layer is continuously reduced.

9. A field effect transistor comprising: a first semiconductor layer made of a first group III-V nitride;a second semiconductor layer formed above said first semiconductor layer, made of a second group III-V nitride and having a gate recess portion;a third semiconductor layer that is formed between said second semiconductor layer and said first semiconductor layer, is made of a third group III-V nitride and absorbs stress caused between said second semiconductor layer and said first semiconductor layer;a gate electrode formed on said first semiconductor layer in said gate recess portion; andohmic electrodes formed on said second semiconductor layer on both sides of said gate electrode.

10. The field effect transistor of claim 9, wherein said third semiconductor layer is made of an amorphous film or a polycrystalline film.

11. The field effect transistor of claim 9, wherein said third semiconductor layer is grown at a lower growth temperature than said first semiconductor layer.

12. A field effect transistor comprising: a first semiconductor layer made of a first group III-V nitride;a second semiconductor layer formed on said first semiconductor layer, made of a second group III-V nitride and having a gate recess portion;a gate electrode formed on said first semiconductor layer in said gate recess portion;ohmic electrodes formed on said second semiconductor layer on both sides of said gate electrode; anda stress reducing film for covering a bottom and a sidewall of said gate recess portion and causing stress in a direction for cancelling stress applied by said second semiconductor layer to said first semiconductor layer.