Field effect transistor

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority from a Japanese application No. 2008-094030 filed on Mar. 31, 2008, the entire content of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a field effect transistor, which is comprised of a semiconductor of a III group nitride compound.

2. Description of the Background Art

There are disclosed as a field effect transistor, which is made use of a semiconductor of a III group nitride compound, such as an HEMT (a high electron mobility transistor), which is made use of an AlGaN/GaN based substance, an MOSFET (a metal oxide semiconductor field effect transistor), which is made use of a GaN based substance (refer to a nonpatent document 1 and 2, a patent document 1, for example). Moreover, such the devices individually have a dielectric breakdown voltage (referred to as a withstand voltage hereinafter) and a saturated velocity (simply referred to as a mobility hereinafter) as higher for each thereof comparing to that according to any other field effect transistors, that are made use of any other semiconductors of the other III group nitride compound, such as Si, GaAs, InP, or the like, and further, such the devices perform an operation as a normally off type. And then thereby, such the devices are suitable for a power device.

[Nonpatent Document 1] M. Kuraguchi et al., “Normally-off GaN-MISFET with well-controlled threshold voltage” International Workshop on Nitride Semiconductors 2006 (IWN2006), Oct. 22-27, 2006, Kyoto, Japan, WeED1-4.

[Non-patent Document 2] Huang W, Khan T, Chow T P: Enhancement-Mode n-Channel GaN MOFETs on p and n-GaN/Sapphire substrates. In: 18th International Symposium on Power Semiconductor Devices and ICs (ISPSD) 2006 (Italy), 10-1.

[Patent Document 1] International Patent Application Publication Pamphlet No. 2003/071607

However, regarding the conventional MOSFET of the GaN based, there is a subject that there is not realized any field effect transistor, that it becomes possible therefor to be compatible with both of the mobility thereof as high and the breakdown voltage thereof as high, though there are reported a device that has a maximum field ion effect mobility of 167 cm²/Vs as high, another device that has a breakdown voltage as close to 1000 V, or the like.

SUMMARY OF THE INVENTION

Here, the present invention has been made to overcome with having regard to such the above mentioned conventional subject, and it is an object of the present invention to provide a field effect transistor of a normally off type, wherein it becomes possible to be compatible with both of the mobility thereof as higher and the breakdown voltage thereof as higher.

For attaining the above mentioned objects and for achieving the object thereof, according to the present invention, a field effect transistor, which is comprised of a semiconductor of a III group nitride compound, comprises: an electron running layer comprised of GaN, that is formed on a substrate; an electron supplying layer comprised of Al_xGa_l-xN (0.01≦x≦0.4), that is formed on the electron running layer, has a band gap energy as different from that of the electron running layer, and is separated due to a recess region, that is formed with having a depth as reaching to the electron running layer; a source electrode and a drain electrode, that are formed on each of the electron supplying layers to be separated, with sandwiching the recess region; a gate insulating film layer, that is formed for covering a surface of the electron running layer regarding an inside of the recess region as all over the electron supplying layer; and a gate electrode, that is formed on the gate insulating film layer regarding the recess region, wherein a layer thickness of the electron supplying layer is not thinner than 5.5 nm but not thicker than 40 nm.

Moreover, in the field effect transistor according to the present invention, the electron running layer is the one that there is added any one of Mg, Be, Zn and C as an acceptor.

Further, in the field effect transistor according to the present invention, an addition density of the acceptor for the electron running layer is not lower than 1×10¹⁵cm⁻³but not higher than 5×10¹⁷cm⁻³.

Still further, in the field effect transistor according to the present invention, the electron running layer comprises a lower part layer and an upper part layer, that is formed on the lower part layer and has a density of the acceptor as different from that for the lower part layer, and the recess region is formed with having a depth for reaching to the lower part layer.

Still further, in the field effect transistor according to the present invention, the electron supplying layer at a side for the drain, that is positioned at directly under the drain electrode, comprises a step structure of not more than three steps, that is formed for becoming thinner for the layer thickness thereof from the side for the drain electrode toward a side for the gate electrode.

Still further, in the field effect transistor according to the present invention, the electron supplying layer at the side for the drain further comprises a drain side region to be positioned at the side for the drain electrode, and a gate side region to be positioned at the side for the gate electrode with having a layer thickness as thinner than that of the drain side region, the layer thickness of the drain side region is a thickness that a sheet carrier density of a two dimensional electron gas to be formed at an interface for the electron running layer becomes between 6 and 8×10¹²cm⁻², and the layer thickness of the gate side region is a thickness that the sheet carrier density of the two dimensional electron gas to be formed at the interface for the electron running layer becomes between 2 and 4×10¹²cm⁻².

Furthermore, in the field effect transistor according to the present invention, the electron supplying layer at the side for the drain to be positioned at directly under the drain electrode further comprises a plurality of regions, that are formed for a composition ratio of Al to become smaller as step by step from the side for the drain electrode toward the side for the gate electrode.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a cross sectional drawing exemplary showing an MOSFET regarding the first embodiment according to the present invention.

FIG. 2 is an explanatory drawing explaining a structure of the electron supplying layer and of a peripheral part thereof, that are shown in FIG. 1.

FIG. 3 is an explanatory drawing showing a variation of a depletion layer in a case where a drain voltage is applied to the MOSFET as shown in FIG. 1.

FIG. 4 is a diagram showing a relation between a layer thickness of an electron supplying layer, that has composition ratios of Al as different from therebetween, and a sheet carrier density of a two dimensional electron gas.

FIG. 5 is an explanatory drawing explaining one example of a process for producing the MOSFET as shown in FIG. 1.

FIG. 6 is an explanatory drawing explaining one example of a process for producing the MOSFET as shown in FIG. 1.

FIG. 7 is an explanatory drawing explaining one example of a process for producing the MOSFET as shown in FIG. 1.

FIG. 8 is a cross sectional drawing exemplary showing an MOSFET regarding the second embodiment according to the present invention.

FIG. 9 is a diagram showing a relation between a layer thickness of an electron supplying layer and a sheet carrier density of a two dimensional electron gas, that in a case where an electron running layer is GaN, which is undoped or contains Mg.

FIG. 10 is a diagram showing an acceptor density dependence regarding an acceptor ion density and a threshold voltage thereof.

FIG. 11 is a cross sectional drawing exemplary showing an MOSFET regarding the third embodiment according to the present invention.

FIG. 12 is a cross sectional drawing exemplary showing an MOSFET regarding the fourth embodiment according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment regarding a field effect transistor according to the present invention will be described in detail below, with reference to the drawings. Moreover, the present invention is not limited according to such the present embodiment. Furthermore, there is made use of a similar symbol for the elements that are similar therebetween or for an element corresponding thereto regarding the drawings as shown below.

FIG. 1 is a cross sectional drawing for exemplary showing an MOSFET regarding the first embodiment according to the present invention. As shown in FIG. 1, such an MOSFET 100 comprises an electron running layer 103, that is comprised of GaN as an undoped to be formed via a buffer layer 102 onto a substrate 101, which is comprised of such as sapphire, SiC, ZrB2, Si, or the like. Moreover, such the buffer layer 102 is the layer that there are laminated eight layers of a GaN/AlN composite lamination with an individual thickness thereof as 200 nm/20 nm for example. Further, the electron running layer 103 is the layer that is designed to have a thickness thereof as 2 μm approximately.

Still further, such the MOSFET 100 further comprises an electron supplying layer 104 and a 105, that are formed on the electron running layer 103. Still further, such the electron supplying layer 104 and the 105 are individually comprised of Al_xGa_l-xN (0.01≦x≦0.4), which has a band gap energy as different from that of the electron running layer 103, and then the same individually form so called a modulated dope structure. Here, the reason for a composition range of the Al_xGa_l-xN layer to be designed as within the above mentioned range thereof is for generating a two dimensional electron gas by forming a band offset at an interface of heterojunction between the Al_xGa_l-xN layer and the GaN layer. Still further, such the electron supplying layer 104 and the 105 are designed to be spaced therebetween due to a recess region 106, that is formed with becoming to have a depth as reaching to the electron running layer 103. Still further, such the recess region 106 is designed to have a width thereof as approximately 2 μm for example, and the same is designed to have a depth thereof from an individual upper surface of the electron supplying layer 104 and of the 105 as approximately 60 nm for example.

Still further, such the MOSFET 100 further comprises a source electrode 107 and a drain electrode 108, that are formed with sandwiching the recess region 106 at the individual upper surface of the electron supplying layer 104 and of the 105 respectively. Still further, such the MOSFET 100 further comprises a gate insulator layer 109 to be comprised of such as SiO₂or the like, which is formed for covering a surface of the electron running layer 103 regarding an inside of the recess region 106 for all over the individual upper surface of the electron supplying layer 104 and of the 105, and the same also comprises a gate electrode 110 as well, which is formed on the gate insulating film layer 109 regarding the recess region 106. Still further, a space between the source electrode 107 and the drain electrode 108 is designed to be as approximately 30 nm for example.

Still further, according to such the MOSFET 100, the electron supplying layer 104, which is positioned to be at directly under the drain electrode 108, comprises a drain side region 104a, which is designed to be positioned at a side for the drain electrode 108, and a gate side region 104b, which is designed to be positioned at a side for the gate electrode 110 and the same is designed to have a layer thickness thereof as thinner than that of the drain side region 104a. That is to say, such the electron supplying layer 104 is designed to have a step structure of two steps, wherein there is designed for the layer thickness thereof to become as thinner from the side for the drain electrode 108 toward the side for the gate electrode 110. Still further, each of the layer thicknesses regarding the drain side region 104a and the gate side region 104b is designed to be as within a range of between 5.5 nm and 40 nm respectively. And then it becomes able to design a quantity of the two dimensional electron gas therein to be as between three and seven times 10¹²/cm², by designing the layer thickness of such the electron supplying layer to be as within the above mentioned range of between 5.5 nm and 40 nm. Furthermore, a layer thickness of the electron supplying layer 105 is designed to be as approximately similar to that of the drain side region 104a.

Next, FIG. 2 is an explanatory drawing for explaining a structure of the electron supplying layer 104 and that of a peripheral part thereof. As shown in FIG. 2, a thickness of the drain side region 104a is defined to be as a t2, and a length thereof is defined to be as an L2. Moreover, a thickness of the gate side region 104b is defined to be as a t1, and a length thereof is defined to be as an L1. Further, in a vicinity of an interface between the electron running layer 103 and the electron supplying layer 104, there becomes to be individually generated a two dimensional electron gas 103a and a 103b, that individually have a mobility as higher, at directly under the drain side region 104a and the gate side region 104b respectively, due to a difference of the band gap energies of between the GaN to comprise the electron running layer 103 and the Al_xGa_l-xN to comprise the electron supplying layer 104. Furthermore, an individual density of such the two dimensional electron gas 103a and of the 103b is defined to be as an Ns1 and an Ns2 respectively.

Next, a variation of a depletion layer in a case where a drain voltage is applied to such the MOSFET 100 will be described in detail below. Here, FIG. 3 is an explanatory drawing for showing a variation of a depletion layer in a case where a drain voltage is applied to the MOSFET 100. Moreover, according to FIG. 3, there are shown a structure of the electron supplying layer 104 and that of a peripheral part thereof, and also shown a potential as an Ec of a conduction band in the vicinity of the interface between the electron running layer 103 and the electron supplying layer 104 as well.

At first, a variation of a depletion layer regarding the drain side region 104a will be described in detail below. And first of all, in a case where both of a gate voltage and the drain voltage are assumed to be as zero V respectively, there is formed a triangular potential P1 at an interface between the electron running layer 103 and the drain side region 104a. And then in a case of applying the drain voltage thereto and of increasing such the voltage with keeping the gate voltage as zero V under such a state thereof, the potential of the conduction band therein becomes to be decreased because an electric potential at the side for the drain side region 104a becomes to be higher. As a result, the potential of the conduction band therein becomes to be increased regarding the electron running layer 103, as indicated with making use of an arrow Ar1 therein, and then thereby the two dimensional electron gas in the vicinity of the interface therebetween becomes to be pinched off, and all of the electrons therein becomes to be depleted therefrom at all. Hence, the depletion layer therein becomes to be extended toward the side for the gate, as indicated with making use of an arrow Ar2 therein.

Next, a variation of a depletion layer regarding the gate side region 104b will be described in detail below. At first, in a case where both of the gate voltage and the drain voltage are assumed to be as zero V respectively, there becomes to be an accumulative mode regarding an MOS structure, that there becomes to be formed according to the gate electrode 110, the gate insulating film layer 109, and the electron running layer 103. And then in a case of applying the drain voltage thereto and of increasing such the voltage with keeping the gate voltage as zero V under such a state thereof, the potential of the conduction band therein becomes to be decreased as indicated with making use of an arrow Ar3 therein, because an electric potential at the side for the electron running layer 103 becomes to be higher. As a result, the depletion layer therein becomes to be extended toward the side for the drain, as indicated with making use of an arrow Ar4 therein.

That is to say, according to such the MOSFET 100, each of the depletion layers therein individually become to be extended from the side for the drain and from the side for the gate regarding the interface between the electron running layer 103 and the electron supplying layer 104, and then thereby it becomes able to realize a withstand voltage thereof as higher. Moreover, according to the recent result thereof, it becomes able to realize a value thereof as 100 V/μm, by adjusting a length between the gate and the drain. Further, in addition thereto, it becomes able to realize a mobility thereof as not less than 1000 cm²/Vs in drift region, because of making use of the two dimensional electron gas as a carrier. Still further, it becomes able to realize an operation as a normally off type, because the electron running layer 103 is designed to be made use of GaN as undoped thereinto.

Still further, according to such the MOSFET 100, there becomes to be as Ns1<Ns2 regarding each of the densities of the two dimensional electron gas 103a and the 103b at directly under the drain side region 104a and the gate side region 104b respectively, because the layer thickness of the 104b is designed to be thinner than the layer thickness of the 104a. As a result, there becomes to be formed an RESURF (a reduced surface field) region of 2-zone thereat, and then it becomes able to design the MOSFET with having a withstand voltage thereof as higher, because it becomes able to design the Ns1 and the Ns2, for the pinch off of the two dimensional electron gas therein to be facilitated regarding the drain side region 104a, and at the same time for the extension of the depletion layer therein to be facilitated regarding the gate side region 104b.

Still further, regarding the Ns1 and the Ns2 as the densities of the two dimensional electron gas 103a and the 103b, it is able to realize a withstand voltage thereof as higher if Ns1<Ns2, however, for realizing the withstand voltage thereof as higher, it is desirable to design as a sheet carrier density for the Ns1 to be as between two and four times 10¹²cm⁻², and in particular therefor to be as approximately three times 10¹²cm⁻², and for the Ns2 to be as between six and eight times 10¹²cm⁻², and in particular therefor to be as approximately 7.5 times 10¹²cm⁻². Still further, regarding the L1 as the length of the gate side region 104b, and regarding the L2 as the length of the drain side region 104a, it is desirable to design the same to be as L1=12 μm and to be as L2=8 μm respectively, for realizing the withstand voltage thereof as higher.

Still further, regarding the Ns1 and the Ns2 as the above mentioned densities individually thereof, it is able to realize the same by designing properly the layer thickness of the electron supplying layer 104 and the composition ratio of Al as the x for the Al_xGa_l-xN that comprises the same. Here, FIG. 4 is a diagram for showing a relation between each of the layer thicknesses of the electron supplying layer 104, that has the individual composition ratio of Al as different from therebetween, and the sheet carrier density of the two dimensional electron gas therein. Still further, an R2 and an R1 therein as the ranges thereof individually designate a preferred range for the density Ns2 and for the Ns1 respectively. And then as shown in FIG. 2, such the sheet carrier density thereof mainly depends on the layer thickness of the electron supplying layer 104. Furthermore, it becomes able to realize a preferred value for each of the Ns1 and the Ns2 as the above mentioned densities thereof, if the thickness of the gate side region 104b as the t1 is designed to be as between 7.5 nm and 8.8 nm, and also if the thickness of the drain side region 104a as the t2 is designed to be as between 11.0 nm and 16.0 nm, in a case where the composition ratio of Al as the x is assumed to be as 0.2 for example.

Next, a process for producing such the MOSFET 100 will be described in detail below. Here, FIG. 5 to FIG. 7 are explanatory drawings for explaining one example of the process for producing the MOSFET 100. Moreover, a case where there is made use of an MOCVD (a metalorganic chemical vapor deposition) method will be described in detail below as the method for a semiconductor layer to be grown by making use thereof, however, the present invention is not limited thereto in particular. That is to say, it may be made use of such as an HVPE (a halide vapor phase epitaxy) method, an MBE (a molecular beam epitaxy) method, or the like therefor as well.

First, as shown in FIG. 5, there becomes to be epitaxially grown for example the buffer layer 102, and then the electron running layer 103 as one after the other onto the substrate 101, that an (111) face thereof is designed to be as a principal surface therefor and the same is designed to be comprised of Si. Moreover, for forming the electron supplying layer 104 and the 105, there becomes to be epitaxially grown the AlGaN layer 111 to become to have the thickness thereof as approximately 30 nm for example, that corresponds to the layer thickness of the drain side region 104a, and the same has the composition ratio of Al as 0.2 for example, on the electron running layer 103. Further, in the case of growing such the AlGaN layer 111, there is designed to add Si with a density thereof to be as approximately 1·10¹⁷cm⁻³(the symbol “·” means a multiplication operator), with making use of silane for example as an impurity of an n type. Next, there becomes to be coated a photo resist onto the surface of the AlGaN layer 111, and then thereafter there becomes to be formed a pattern for device separation by performing a photolithography process therefor. Furthermore, by making use of a dry etching method, such as an RIE (a reactive ion etching) method or the like, there becomes to be formed a trench (as not shown in the figures) for device separation with becoming to have a depth thereof as approximately 200 nm. And then thereafter there becomes to be removed such the photo resist with making use of acetone.

Next, as shown in FIG. 6, there becomes to be formed a mask layer 112, which is designed to be comprised of SiO2, onto the AlGaN layer 111 with becoming to have a thickness thereof as approximately 300 nm by making use of a PECVD (plasma chemical vapor deposition) method for example. Moreover, there becomes to be performed a patterning process therefor by making use of a photolithography process, and then thereafter there becomes to be formed an open part 112a at a region for the gate side region 104b to be formed thereat, with making use of an aqueous solution of a hydrofluoric acid based. And then thereafter there becomes to be formed a thin layer region 111a, which corresponds to the gate side region 104b, by performing an etching process for the AlGaN layer 111 to become to have a depth thereof as approximately 20 nm regarding the open part 112a, with making use of a dry etching equipment. And then thereafter there becomes to be removed such the mask layer 112 with making use of an aqueous solution of a hydrofluoric acid based.

Next, as shown in FIG. 7, there becomes to be formed a mask layer 113, which is designed to be comprised of SiO2, onto all over a surface thereof with becoming to have a thickness thereof as approximately 300 nm by making use of the PECVD method for example. Moreover, there becomes to be performed a patterning process by making use of a photolithography process, and then thereafter there becomes to be formed an open part 113a at a region for the recess region 106 to be formed thereat, with making use of an aqueous solution of a hydrofluoric acid based. And then thereafter there becomes to be formed the recess region 106 by performing an etching process for the AlGaN layer 111 and then for the electron running layer 103 to become to have a depth thereof as approximately 60 nm regarding the open part 113a, with making use of the dry etching equipment. And then due to the formation of such the recess region, there becomes to be separated such the AlGaN layer 111, and then thereby there becomes to be formed the electron supplying layer 104 and the 105. And then thereafter there becomes to be removed such the mask layer 113 with making use of an aqueous solution of a hydrofluoric acid based.

Next, there becomes to be formed the gate insulator layer 109 for all over an upper surface of the electron supplying layer 104 and of the 105, which is designed to be comprised of SiO₂, with becoming to have a thickness thereof as approximately 60 nm by making use of the PECVD method, for covering the surface of the electron running layer 103 regarding an inside of the recess region 106. Next, there becomes to be removed a part of the gate insulator layer 109 with making use of an aqueous solution of a hydrofluoric acid based, and then thereafter there become to be formed the drain electrode 108 and the source electrode 107 individually onto the electron supplying layer 104 and the 105 respectively, by making use of a lift off technology. Moreover, such the drain electrode 108 and the source electrode 107 are designed to be ohmic contacted with the electron supplying layer 104 and with the 105 respectively, and then to have a Ti/Al layer structure with having individual thicknesses as 25 nm/300 nm for example. Further, regarding a film formation of a metal film layer for forming such the electrodes thereon, it is able to perform the same by making use of a spattering method, a vacuum evaporation method, or the like. Furthermore, there becomes to be formed such the source electrode 107 and the drain electrode 108, and then thereafter there becomes to be performed an annealing process therefor approximately at a temperature thereof as 600° C. for ten minutes.

Next, there becomes to be formed a poly-Si (polysilicon) layer for all over a surface thereof, by making use of such as an LPCVD (a low pressure chemical vapor deposition) method, the spattering method, or the like. Next, there becomes to be performed a heat treatment approximately at a temperature thereof as 900° C. for twenty minutes with making use of a thermal diffusion furnace in which POCl₃gas is enclosed, and then by making use of a thermal diffusion method, there becomes to be doped P into such the poly-Si layer. Moreover, it may be available for a doping material source to make use of a member on which P is evaporated as well. Next, there becomes to be formed a photolithography process for such the poly-Si layer, and then thereby there becomes to be formed the gate electrode 110. Thus, it becomes able to complete such the MOSFET 100 as shown in FIG. 1. Furthermore, it may be available to form such the gate electrode 110 by making use of such as the lift off technology as well, with making use of a substance that is comprised of such as Au, Pt, Ni, or the like.

Thus, as described above, according to the MOSFET 100 regarding the first embodiment, it becomes able to obtain such the MOSFET as a normally off type, in which it becomes able to be compatible with between the mobility thereof as higher and the breakdown voltage thereof as higher as well.

Next, the second embodiment according to the present invention will be described in detail below. Here, regarding an MOSFET according to the second embodiment, an electron running layer therein comprises a lower part layer and an upper part layer, and then Mg is added individually thereinto with a density as different from therebetween.

FIG. 8 is a cross sectional drawing for exemplary showing such the MOSFET according to the second embodiment. Here, such a MOSFET 200 is designed to have a structure that the electron running layer 103 according to the MOSFET 100 regarding the first embodiment is replaced to a lower part layer 203a, an upper part layer 203b and a 203c, and also that each of the elements which corresponds thereto is replaced to a recess region 206 and a gate insulating film layer 209. Moreover, the recess region 206 is designed to be formed to become to have a depth as reaching to the lower part layer 203a. Further, the gate insulating film layer 209 is designed to be formed for covering a surface of such the lower part layer 203a regarding an inner side of the recess region 206.

Still further, each of the lower part layer 203a, the upper part layer 203b and of the 203c is designed to be individually comprised of p-GaN, in which Mg as a dopant of a p type becomes to be added with a density thereof as different from therebetween. And then a layer thickness thereof is designed to be as approximately 500 nm for the lower part layer 203a, to be as approximately 50 nm for the upper part layer 203b and the same for the 203c respectively.

Still further, according to such the MOSFET 200, it becomes able to be compatible with between the mobility thereof as higher and the breakdown voltage thereof as higher as well, because of the configuration as similar to that according to the MOSFET 100. Furthermore, according to such the MOSFET 200, it becomes able to realize an operation of a normally off type, it becomes able to realize a preferred density of the two dimensional electron gas as in higher accuracy and as easily, and it becomes able to obtain a threshold voltage thereof' as higher as well, because of making use of the lower part layer 203a and the upper part layer 203b and the 203c that are individually comprised of p-GaN in which an addition density of Mg is different from therebetween. Here, the reason why Mg is adopted as the dopant is because that an acceptor level thereof is shallower comparing to that of other elements of the II group except for Be in the case of Mg, and also that it is the easiest to be activated among such the elements of the II group.

Next, there will be described in further detail as below. As described above, according to the MOSFET 100, it is able to realize the preferred values individually for the above mentioned densities as the Ns1 and the Ns2, if the thickness as the t1 regarding the gate side region 104b is designed to be as between 7.5 nm and 8.8 nm, and also if the thickness as the t2 regarding the drain side region 104a is designed to be as between 11.0 nm and 16.0 nm, in the case where the composition ratio of Al as the x is assumed to be as 0.2. However, in a case where the gate side region 104b is designed to be as having a preferred layer thickness thereof by performing a dry etching process, it becomes necessary to control strictly regarding a depth thereof to be etched thereby.

On the contrary thereto, according to the MOSFET 200, it becomes able to design a tolerance regarding the layer thickness of the gate side region 104b and of the drain side region 104a for being able to realize the preferred density individually thereof as the Ns1 and the Ns2, because each of the upper part layer 203b and the 203c is designed to be comprised of p-GaN in which Mg is added.

That is to say, in the case where both of the electron supplying layer and the electron running layer individually have the AlGaN/GaN layer structure, there becomes to be stood up a neutrality condition of electric charge as expressed by the following Equation 1.

ρ⁺+N_D⁺=ρ⁻+N_2D⁻ (Equation 1).

Here, according to Equation 1, the ρ⁺ and the ρ⁻ are the electric charges that are individually appeared due to a positive and to a negative piezo polarization respectively, the N_D⁺ is a donor ion density in the AlGaN layer, and the N_2D⁻ is a density of the two dimensional electron gas therein. Moreover, according to Equation 1, the left side thereof is the electric charge at a side for the AlGaN layer, meanwhile, the right side thereof is the electric charge at a side for the GaN layer, and then the neutrality condition of electric charge is maintained for standing up a boundary condition at an interface therebetween.

Next, in a case where Mg is added into the GaN layer, a neutrality condition of electric charge becomes to be expressed by the following Equation 2.

ρ⁺+N_D⁺=ρ⁻+N_2D⁻+N_A⁻ (Equation 2).

Here, the N_A⁻ is an acceptor ion density of according to the Mg therein. Moreover, according to Equation 1 and Equation 2, the ρ⁺, the N_D⁺ and the ρ⁻ are the values as similar to therebetween respectively. Therefore, the N_2D⁻ becomes to be decreased because of increasing the N_A⁻ due to the addition of the Mg therein.

Next, FIG. 9 is a diagram for showing a relation between a layer thickness of the electron supplying layer, that in a case where the electron running layer is designed to be comprised of GaN, which is undoped or contains Mg, and a sheet carrier density of the two dimensional electron gas therein. Moreover, there is assumed for the composition ratio as the x regarding the electron supplying layer to be as 0.35 in FIG. 9. Further, the curved line C1 in FIG. 9 designates for a case where the electron running layer is designed to be comprised of GaN as undoped therein, meanwhile, the curved lines C2 and the C3 therein individually designate for a case where the electron running layer is designed to be comprised of GaN as consisting Mg, and for a case where each of the layer thickness thereof is designed to be as 1 μm and 2 μm respectively. Further, for the case as shown in FIG. 9, Mg is added into the electron running layer with a density as approximately homogeneously, and then the density of the acceptor ions is designed to be as 1.5·10¹⁶cm⁻³(the symbol “·” means the multiplication operator). Still further, in the case where the electron running layer contains Mg, the sheet carrier density thereof becomes to be decreased for all over thereof comparing to the case of undope, and a variation of the density thereof corresponding to a variation of the layer thickness thereof becomes to be gradual as well, as shown in FIG. 9. Therefore, if an electron running layer contains Mg, the tolerance of the layer thickness of the electron supplying layer becomes to be larger, because the variation of the sheet carrier density becomes to be smaller comparing to an error, such as a manufacturing error or the like, regarding the layer thickness of such the electron supplying layer, and then thereby it becomes able to produce as further easier by performing an etching process or the like. Furthermore, it becomes able to adjust a degree of magnitude regarding the sheet carrier density thereof and a rate of variation regarding the density thereof by controlling the layer thickness of the electron running layer and the addition density of Mg. As a result, it becomes able to realize a preferred density of the two dimensional electron gas therein as in an accuracy as further higher and easier as well.

For example, as comparing between the curved line C1 that is non-doped and the curved line C3 that the film layer thickness of the electron running layer is 2 μm and Mg is doped for the acceptor density thereof to become as one times 10¹⁷/cm³, in a case of the composition ratio of Al as 0.35 (Al: 35%), it is necessary for the layer thickness of the electron supplying layer to be designed as between 6.5 nm and 7.5 nm for the case of the curved line C1 in a case for realizing the sheet carried density to be as between two and four times 10¹²cm⁻², on the contrary, it may be available for such the layer thickness of the electron supplying layer to be designed as between 8.5 nm and 12.0 nm for the case of the curved line C3 in such the case.

Moreover, in the case where the electron running layer is designed to be as the GaN layer that contains Mg, there is a predetermined relationship between the addition density of Mg (an acceptor density) therein and the density of the acceptor ions due to the Mg therein. While, the threshold voltage of the MOSFET is uniquely determined due to the N_A⁻ as the density of the acceptor ions according to the Mg therein. Therefore, it becomes able to change such the threshold voltage thereof by performing an adjustment for the acceptor density of Mg therein. Here, FIG. 10 is a diagram for showing an acceptor density dependence regarding the density of the acceptor ions and the threshold voltage thereof, wherein the horizontal axis indicates the acceptor density as the N_A, the vertical axis at the left side therein indicates the density of the acceptor ions as the N_A⁻, and the vertical axis at the right side therein indicates the threshold voltage thereof as a V_th. Further, regarding FIG. 10, there is calculated with assuming for the layer thickness of the gate insulating film layer to be as 50 nm, for a work function regarding the gate electrode to be as 4.1 eV, for the acceptor level regarding the Mg therein to be as 200 meV, and a temperature to be as 300 K. And then as shown in FIG. 10, it becomes able to realize a threshold voltage thereof as +3 V that is to be required in a case where such the device is made use for a power device, if the acceptor density thereof is designed to be as 1·10¹⁷cm⁻³(the symbol “·” means a multiplication operator), and also if the density of the acceptor ions is designed to be as 1.5·10¹⁶cm⁻³(the symbol “·” means the multiplication operator). Still further, in a case of the conventional HEMT of AlGaN/GaN based, the threshold voltage thereof is smaller as +1 V, on the contrary, according to the second embodiment, it becomes able to realize the threshold voltage thereof as extremely higher than such the conventional value.

Still further, according to the MOSFET 200 regarding the second embodiment, the threshold voltage thereof is designed to be determined according to the density of the acceptor ions therein due to Mg regarding the lower part layer 203a. On the contrary, there is influenced on the sheet carrier density of the two dimensional electron gas by the density of the acceptor ions due to Mg regarding the upper part layer 203b and the 203c. Therefore, according to such the MOSFET 200, by performing an optimization independently for the addition density of Mg regarding the lower part layer 203a and the upper part layer 203b and the 203c, it becomes able to control independently for the withstand voltage thereof and the threshold voltage thereof to be a preferred value for each thereof. Still further, from a point of view of the withstand voltage thereof and the threshold voltage thereof, for a case of designing the threshold voltage to be as between 3 V and 5 V, it is desirable for the addition density of Mg for the lower part layer 203a and for the upper part layer 203b to be as not lower than 1·10¹⁵cm⁻³(the symbol “·” means the multiplication operator) but not higher than 5·10¹⁷cm⁻³(the symbol “·” means the multiplication operator) for both thereof respectively.

Still further, it is able to produce such the MOSFET 200 according to the second embodiment by making use of a process as similar to the process for producing the MOSFET 100 as described above. Still further, for the addition of Mg, there is made use of such as Cp2 Mg (biscyclopentadienyl magnesium) or the like.

Still further, according to the MOSFET 200 regarding the second embodiment, the individual addition densities of Mg regarding the lower part layer 203a and the upper part layer 203b and the 203c are designed to be different from therebetween, however, even in a case where it is designed to be a density thereof as similar to therebetween, it becomes able to obtain an advantage that it becomes able to obtain the tolerance for the thickness of the electron supplying layer as larger.

Furthermore, according to the above mentioned first and the second embodiments, the electron supplying layer 104 comprises the step structure of two steps, however, it may be available to be designed as a step structure of three steps as well. And then in such the case of the step structures as between two and three steps, it becomes easier to produce such the device by making use thereof.

Next, the third embodiment according to the present invention will be described in detail below. Here, FIG. 11 is a cross sectional drawing for exemplary showing an MOSFET according to the third embodiment. Moreover, such a MOSFET 300 is designed to have a structure that each of the elements which corresponds to each thereof according to the MOSFET 200 regarding the second embodiment is replaced to an electron supplying layer 304 and a 305, a recess region 306, a gate insulator layer 309, and a gate electrode 310 therein respectively.

Further, the electron supplying layer 304 is designed to be comprised of Al_xGa_l-xN, and the same comprises a drain side region 304a, which is designed to be positioned at a side for the drain electrode 108, and a gate side region 304b, which is designed to be positioned at a side for the gate electrode 310. Still further, the electron supplying layer 305 is designed to be comprised of Al_xGa_l-xN. Still further, the recess region 306 is designed to be formed with becoming to have a depth as reaching to the lower part layer 203a. Still further, the gate insulating film layer 309 is designed to be formed for covering the surface of such the lower part layer 203a regarding an inner side of the recess region 306 for all over the electron supplying layer 304 and the 305. Still further, each of the drain side region 304a and the gate side region 304b is designed to have a layer thickness as approximately similar to therebetween, however, a composition ratio of Al in the gate side region 304b is designed to be as smaller than a composition ratio of Al in the drain side region 304a. As a result, as similar to that according to the MOSFET 100 and the 200, there becomes to be formed an RESURF region of 2-zone therein, and then thereby regarding such the MOSFET, it becomes able to obtain a mobility thereof as higher, and it becomes able to obtain a withstand voltage thereof as higher as well. Still further, regarding each of the composition ratios of Al in the drain side region 304a and in the gate side region 304b, it is able to be designed as 0.4 and 0.2 respectively, however, the present invention is not limited thereto in particular if it is within a range of between 0.01 and 0.4. Still further, the layer thickness and the composition ratio of the electron supplying layer 305 are designed to be as individually similar to that of the drain side region 304a, however, the present invention is not limited thereto in particular.

Still further, it is able to produce such the MOSFET 300 according to the third embodiment by making use of a process as similar to the process for producing the MOSFET 100 as described above. Still further, for forming such the electron supplying layer 304, it is able to make use of such as a method for regrowth thereof or the like.

Still further, according to such the MOSFET 300 regarding the third embodiment, the electron supplying layer 304 therein comprises the regions as two, however, it may be available for an electron supplying layer therein to be designed as comprising regions as not less than two as well, that are designed to be formed for a composition ratio of Al therein to become smaller as step by step from a side for the drain electrode toward a side for the gate electrode. Furthermore, regarding such a number of the regions therein, it becomes easier to produce such a device thereby if the number thereof is designed to be as between two and three.

The Fourth Embodiment

Next, the fourth embodiment according to the present invention will be described in detail below. Here, FIG. 12 is a cross sectional drawing for exemplary showing an MOSFET according to the fourth embodiment. Moreover, such a MOSFET 400 is designed to have a structure that each of the elements which correspond to each thereof according to the MOSFET 300 regarding the third embodiment is replaced to an electron supplying layer 404 and a 405 therein respectively.

Further, such the electron supplying layer 404 and the 405 are individually comprised of Al_xGa_l-xN (0.01≦x≦0.4), and then each of such the layers have a layer thickness as equivalent to therebetween which is within a range of between 5.5 nm and 40 nm. Still further, regarding such the MOSFET 400, as different from the cases according to the MOSFET 100 to the 300, there is designed to be formed an RESURF region of 1-zone therein. Still further, according to such the MOSFET 400 as similar thereto, there is designed for a depletion layer to be extended from both of a side for the drain and a side for the gate at an interface between the upper part layer 203b and the electron supplying layer 404, and then thereby it becomes able to realize a withstand voltage thereof as higher. Furthermore, it becomes able to realize a mobility in the drift region thereof as higher as well, which is not lower than 1000 cm²/Vs, because there is designed to be made use of the two dimensional electron gas therein as a carrier.

EFFECT OF THE INVENTION

Thus, according to the present invention, it becomes able to obtain an advantage that it becomes able to realize a field effect transistor of a normally off type, wherein a mobility thereof as higher and a breakdown voltage thereof as higher become to be compatible with therebetween.

Field effect transistor

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