Patent Application
20250147433
The present disclosure relates generally to field of view selection for metrology associated with semiconductor manufacturing.
A lithographic projection apparatus can be used, for example, in the manufacture of integrated circuits (ICs). A patterning device (e.g., a mask) may include or provide a pattern corresponding to an individual layer of the IC (“design layout”), and this pattern can be transferred onto a target portion (e.g. comprising one or more dies) on a substrate (e.g., silicon wafer) that has been coated with a layer of radiation-sensitive material (“resist”), by methods such as irradiating the target portion through the pattern on the patterning device. In general, a single substrate contains a plurality of adjacent target portions to which the pattern is transferred successively by the lithographic projection apparatus, one target portion at a time. In one type of lithographic projection apparatus, the pattern on the entire patterning device is transferred onto one target portion in one operation. Such an apparatus is commonly referred to as a stepper. In an alternative apparatus, commonly referred to as a step-and-scan apparatus, a projection beam scans over the patterning device in a given reference direction (the “scanning” direction) while synchronously moving the substrate parallel or anti-parallel to this reference direction.
Different portions of the pattern on the patterning device are transferred to one target portion progressively. More information with regard to lithographic devices can be found in, for example, U.S. Pat. No. 6,046,792, incorporated herein by reference.
Prior to transferring the pattern from the patterning device to the substrate, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures (“post-exposure procedures”), such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the transferred pattern. This array of procedures is used as a basis to make an individual layer of a device, e.g., an IC. The substrate may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish the individual layer of the device. If several layers are required in the device, then the whole procedure, or a variant thereof, is repeated for each layer. Eventually, a device will be present in each target portion on the substrate. These devices are then separated from one another by a technique such as dicing or sawing, such that the individual devices can be mounted on a carrier, connected to pins, etc.
Manufacturing devices, such as semiconductor devices, typically involves processing a substrate (e.g., a semiconductor wafer) using a number of fabrication processes to form various features and multiple layers of the devices. Such layers and features are typically manufactured and processed using, e.g., deposition, lithography, etch, chemical-mechanical polishing, and ion implantation. Multiple devices may be fabricated on a plurality of dies on a substrate and then separated into individual devices. This device manufacturing process may be considered a patterning process. A patterning process involves a patterning step, such as optical and/or nanoimprint lithography using a patterning device in a lithographic apparatus, to transfer a pattern on the patterning device to a substrate and typically, but optionally, involves one or more related pattern processing steps, such as resist development by a development apparatus, baking of the substrate using a bake tool, etching using the pattern using an etch apparatus, etc.
Lithography is a central step in the manufacturing of device such as ICs, where patterns formed on substrates define functional elements of the devices, such as microprocessors, memory chips, etc. Similar lithographic techniques are also used in the formation of flat panel displays, micro-electro mechanical systems (MEMS) and other devices.
As semiconductor manufacturing processes continue to advance, the dimensions of functional elements have continually been reduced. At the same time, the number of functional elements, such as transistors, per device has been steadily increasing, following a trend commonly referred to as “Moore's law.” At the current state of technology, layers of devices are manufactured using lithographic projection apparatuses that project a design layout onto a substrate using illumination from an illumination source, creating individual functional elements having dimensions well below 100 nm.
This process in which features with dimensions smaller than the classical resolution limit of a lithographic projection apparatus are printed, is commonly known as low-k1 lithography, according to the resolution formula CD=k1×λ/NA, where λ is the wavelength of radiation employed (currently in most cases 248 nm or 193 nm), NA is the numerical aperture of projection optics in the lithographic projection apparatus, CD is the “critical dimension”-generally the smallest feature size printed—and k1 is an empirical resolution factor. In general, the smaller k1 the more difficult it becomes to reproduce a pattern on the substrate that resembles the shape and dimensions planned by a designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated fine-tuning steps are applied to the lithographic projection apparatus, the design layout, or the patterning device. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting patterning devices, optical proximity correction (OPC, sometimes also referred to as “optical and process correction”) in the design layout, source mask optimization (SMO), or other methods generally defined as “resolution enhancement techniques” (RET).
In manufacturing processes of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and are free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes, such as a scanning electron microscope (SEM) can be employed. As the physical sizes of IC components continue to shrink, and their structures continue to become more complex, accuracy and throughput in defect detection and inspection become more important.
Users typically manually select fields of view for metrology and inspection that include various diverse patterns. Often, some of the fields of view overlap with each other, have pattern geometry that is only slightly different, and include a large amount of redundant information from one field of view to the next. The large number of groups, the redundant information, and/or other factors, can burden downstream computing (e.g., process monitoring, computational lithography, etc.) processes because the large number and/or redundant information creates a need for significant computing resources. Overlapping fields of view may cause wafer charging in scanning electron microscope (SEM) measurement. In addition, manual selection generally makes the manufacturing process less efficient and/or has other disadvantages.
According to an embodiment, there is provided a method for selecting one or more subsets of fields of view of a pattern layout. The method comprises determining a set of candidate fields of view based on pattern groups of the pattern layout, and selecting the one or more subsets of the fields of view from the set of candidate fields of view according to prescribed criteria. The prescribed criteria is for combinations of fields of view included in the one or more subsets for scanning electron microscope (SEM) measurement.
In some embodiments, the method comprises grouping patterns of the pattern layout into the pattern groups. The grouping comprises pattern matching to produce the pattern groups.
In some embodiments, each of the one or more subsets corresponds to a field of view list.
In some embodiments, a field of view includes a portion of the pattern layout.
In some embodiments, a subset of fields of view comprises a list of fields of view selected from the set of candidate fields of view.
In some embodiments, selecting the one or more subsets comprises assigning fields of view including specific patterns to respective fields of view lists by applying a graph based overlapping elimination algorithm.
In some embodiments, the graph based overlapping elimination algorithm comprises a graph coloring algorithm, and each field of view list corresponds to a color.
In some embodiments, the prescribed criteria is configured such that the graph based elimination and/or graph coloring algorithm outputs an optimally diverse group of patterns in a predetermined number of lists of fields of view.
In some embodiments, selecting the one or more subsets comprises assigning fields of view including specific patterns to respective fields of view lists by applying an integer linear programming algorithm.
In some embodiments, selecting the one or more subsets comprises assigning fields of view including specific patterns to respective fields of view lists by applying the integer linear programming algorithm and a graph coloring algorithm, wherein each field of view list corresponds to a color.
In some embodiments, the prescribed criteria is configured such that the integer linear programming and/or graph coloring algorithm outputs an optimally diverse group of patterns in a predetermined number of lists of fields of view.
In some embodiments, determining the set of candidate fields of view is further based constraints on characteristics of a given field of view.
In some embodiments, the characteristics of a given field of view comprise a distance from the given fields of view to another fields of view and/or a size of the given field of view.
In some embodiments, determining the set of candidate fields of view is further based on a generation method comprising matched instance pattern replacement for the set of candidate fields of view.
In some embodiments, the matched instance pattern replacement comprises pattern matching of patterns in the pattern layout to produce pattern groups, and selecting an alternate pattern from the same pattern group to replace a pattern in the pattern group.
In some embodiments, determining the set of candidate fields of view is based on a generation method comprising field of view merging and/or shifting.
In some embodiments, field of view merging and/or shifting comprises combining patterns from different pattern groups into a single candidate field of view.
In some embodiments, field of view merging and/or shifting is based on a proximity of patterns from different pattern groups to each other.
In some embodiments, the prescribed criteria comprises a pattern group diversity metric. In some embodiments, the prescribed criteria comprises a pattern group criticality metric. In some embodiments, the pattern group criticality metric comprises a weight of a pattern group. In some embodiments, the prescribed criteria comprises a subset and/or fields of view quantity metric.
In some embodiments, determining the set of candidate fields of view based on pattern groups of the pattern layout comprises determining the set of candidate fields of view based on an initial list of pattern locations and matching information for the pattern groups.
In some embodiments, the prescribed criteria is set such that patterns included in the one or more subsets of fields of view in combination represent an entirety of the pattern layout or a portion of the pattern layout.
In some embodiments, the prescribed criteria causes inclusion of an optimally diverse group of patterns in a predetermined number of subsets of fields of view.
In some embodiments, the optimally diverse group of patterns comprises a plurality of patterns having geometries that, in combination, represent at least a threshold amount of the pattern layout, given the predetermined number of subsets that form the determined one or more subsets.
In some embodiments, the predetermined number of subsets is set by a user. In some embodiments, the predetermined number of subsets is minimized.
In some embodiments, the method further comprises providing the determined one or more subsets of fields of view as input for model calibration, critical dimension (CD) metrology, and/or defect inspection for a semiconductor lithography process.
In some embodiments, the pattern layout comprises a design layout for a semiconductor wafer.
According to another embodiment, there is provided a non-transitory computer readable medium having instructions thereon, the instructions when executed by a computer causing the computer to perform any of the operations of the method described above.
According to another embodiment, there is provided a system comprising one or more processors configured to perform any of the operations of the method described above.
According to another embodiment, there is provided a non-transitory computer readable medium having instructions thereon, the instructions when executed by a computer causing the computer to perform a method for selecting one or more lists of fields of view of a pattern layout, the method comprising: determining a set of candidate fields of view based on pattern groups of the pattern layout and constraints on characteristics of a given field of view, wherein the characteristics of a given field of view comprise a distance from the given field of view to another field of view and/or a size of the given field of view; and selecting the one or more lists of the fields of view from the set of candidate fields of view according to prescribed criteria for combinations of fields of view included in the one or more lists for scanning electron microscope measurement, wherein selecting the one or more lists comprises: assigning fields of view including specific patterns to respective lists by applying a graph based elimination and graph coloring algorithm, wherein each field of view list corresponds to a color; or assigning fields of view including specific patterns to respective fields of view lists by applying an integer linear programming algorithm and graph coloring algorithm, wherein each field of view corresponds to a color; wherein the prescribed criteria comprises inclusion of an optimally diverse group of patterns in a predetermined number of lists of fields of view.
Other advantages of the embodiments of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings, which set forth, by way of illustration and example, certain example embodiments.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate one or more embodiments and, together with the description, explain these embodiments. Embodiments will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:
Making extremely small ICs is a complex, time-consuming, and expensive process, often involving hundreds of individual steps. Errors in even one step have the potential to result in defects in the finished IC, thereby rendering it useless. Thus, one goal of the manufacturing process is to avoid such defects to maximize the number of functional ICs made in the process, that is, to improve the overall yield of the process.
One component of improving yield is monitoring the chip making process to ensure that it is producing a sufficient number of functional integrated circuits. One way to monitor the process is to inspect the chip circuit structures at various stages of their formation. Inspection can be carried out using optical systems, and/or a scanning electron microscope (SEM), for example.
Several fields of view (FOVs) for an inspection that each include various combinations of patterns from different pattern groups may be used. For example, an initial listing of FOVs that cover certain target pattern groups may be provided for SEM inspection. With the existing manual selection method, for a given pattern list, pattern matching and/or grouping techniques to find replaceable matched instances of pattern groups across a full pattern layout are not considered. This limits the manual selection method's ability to avoid overlap, reduce a required number of FOVs, and/or has other disadvantages. Based on the given pattern list, the existing manual selection method only considers a pattern center for FOV candidate determination, without considering whether pattern merging and/or shifting may be possible to optimize an FOV candidate (e.g., to avoid overlap, reduce a required number of FOVs, etc.). For candidate FOVs generated based on the pattern center, the existing manual selection method discards overlapping FOVs arbitrarily, instead of determining an optimal set of FOVs that cover as wide of a range of pattern geometry as possible in the fewest number of FOVs and/or lists, for example.
The present disclosure provides a mechanism of generating and optimizing FOV lists of a pattern layout selected for metrology, and/or for other purposes. Embodiments of the present disclosure are configured to find matched instances of a pattern through pattern matching or pattern grouping techniques (e.g., to avoid overlap, reduce a required number of FOVs, etc.). Embodiments of the present disclosure can facilitate covering more pattern groups with less FOVs in one or more lists. Embodiments of the present disclosure utilize FOV merging and shifting methods, graph coloring and integer linear programming, and/or other technique to identify FOVs for FOV lists which represent diverse and critical patterns in a pattern layout. With these techniques, users can be provided with a least (and/or otherwise user specified) number of FOVs and/or lists that include diverse and critical patterns for different downstream applications such as model calibration, critical dimension (CD) metrology, hotspot and/or defects detection, etc.
Embodiments of the present disclosure are described in detail with reference to the drawings, which are provided as illustrative examples of the disclosure so as to enable those skilled in the art to practice the disclosure. The figures and examples below are not meant to limit the scope of the present disclosure to a single embodiment, but other embodiments are possible by way of interchange of some or all of the described or illustrated elements. Where certain elements of the present disclosure can be partially or fully implemented using known components, only those portions of such known components that are necessary for an understanding of the present disclosure will be described, and detailed descriptions of other portions of such known components will be omitted so as not to obscure the disclosure. Embodiments described as being implemented in software should not be limited thereto, but can include embodiments implemented in hardware, or combinations of software and hardware, and vice-versa, as will be apparent to those skilled in the art, unless otherwise specified herein. In the present specification, an embodiment showing a singular component should not be considered limiting; rather, the disclosure is intended to encompass other embodiments including a plurality of the same component, and vice-versa, unless explicitly stated otherwise herein. Moreover, applicants do not intend for any term in the specification or claims to be ascribed an uncommon or special meaning unless explicitly set forth as such. The present disclosure encompasses present and future known equivalents to the known components referred to herein by way of illustration.
Although specific reference may be made in this text to the manufacture of ICs, it should be explicitly understood that the description herein has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal display (LCD) panels, thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms “reticle”, “wafer” or “die” in this text should be considered as interchangeable with the more general terms “mask”, “substrate” and “target portion”, respectively.
In the present document, the terms “radiation” and “beam” are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g. with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultra-violet radiation, e.g. having a wavelength in the range of about 5-100 nm).
A (e.g., semiconductor) patterning device can comprise, or can form, one or more design layouts. The design layout can be generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts/patterning devices. These rules are set by processing and design limitations. For example, design rules define the space tolerance between devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the devices or lines do not interact with one another in an undesirable way. The design rules may include or specify specific parameters, limits on ranges for parameters, or other information. One or more of the design rule limitations or parameters may be referred to as a “critical dimension” (CD). A critical dimension of a device can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes, or other features. Thus, the CD determines the overall size and density of the designed device. One of the goals in device fabrication is to faithfully reproduce the original design intent on the substrate (via the patterning device).
The term “mask” or “patterning device” as employed in this text may be broadly interpreted as referring to a generic semiconductor patterning device that can be used to endow an incoming radiation beam with a patterned cross-section, corresponding to a pattern that is to be created in a target portion of the substrate. Besides the classic mask (transmissive or reflective; binary, phase-shifting, hybrid, etc.), examples of other such patterning devices include a programmable mirror array and a programmable LCD array.
As used herein, the term “patterning process” generally means a process that creates an etched substrate by the application of specified patterns of light as part of a lithography process. However, “patterning process” can also include (e.g., plasma) etching, as many of the features described herein can provide benefits to forming printed patterns using etch (e.g., plasma) processing.
As used herein, the term “pattern” means an idealized pattern that is to be etched on a substrate (e.g., wafer).
As used herein, a “printed pattern” (or a pattern on a substrate) means the physical pattern on a substrate that was etched based on a target pattern. The printed pattern can include, for example, troughs, channels, depressions, edges, or other two and three dimensional features resulting from a lithography process.
As used herein, the term “calibrating” means to modify (e.g., improve or tune) or validate something, such as a model.
A patterning system may be a system comprising any or all of the components described herein, plus other components configured to performing any or all of the operations associated with these components. A patterning system may include a lithographic projection apparatus, a scanner, systems configured to apply or remove resist, etching systems, or other systems, for example.
As an introduction,
Lithographic projection apparatus LA can include an illumination system IL, a first object table T, a second object table WT, and a projection system PS. Illumination system IL, can condition a beam B of radiation. In this example, the illumination system also comprises a radiation source SO. First object table (e.g., a patterning device table) T can be provided with a patterning device holder to hold a patterning device MA (e.g., a reticle), and connected to a first positioner to accurately position the patterning device with respect to item PS. Second object table (e.g., a substrate table) WT can be provided with a substrate holder to hold a substrate W (e.g., a resist-coated silicon wafer), and connected to a second positioner to accurately position the substrate with respect to item PS. Projection system (e.g., which includes a lens) PS (e.g., a refractive, catoptric or catadioptric optical system) can image an irradiated portion of the patterning device MA onto a target portion C (e.g., comprising one or more dies) of the substrate W. Patterning device MA and substrate W may be aligned using patterning device alignment marks M1, M2 and substrate alignment marks P1, P2, for example.
As depicted, the apparatus can be of a transmissive type (i.e., has a transmissive patterning device). However, in general, it may also be of a reflective type, for example (with a reflective patterning device). The apparatus may employ a different kind of patterning device for a classic mask; examples include a programmable mirror array or LCD matrix.
The source SO (e.g., a mercury lamp or excimer laser, LPP (laser produced plasma) EUV source) produces a beam of radiation. This beam is fed into an illumination system (illuminator) IL, either directly or after having traversed conditioning means, such as a beam expander, or beam delivery system BD (comprising directing mirrors, the beam expander, etc.). for example. The illuminator IL may comprise adjusting means AD for setting the outer or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in the beam. In addition, it will generally comprise various other components, such as an integrator IN and a condenser CO. In this way, the beam B impinging on the patterning device MA has a desired uniformity and intensity distribution in its cross-section.
In some embodiments, source SO may be within the housing of the lithographic projection apparatus (as is often the case when source SO is a mercury lamp, for example), but that it may also be remote from the lithographic projection apparatus. The radiation beam that it produces may be led into the apparatus (e.g., with the aid of suitable directing mirrors), for example. This latter scenario can be the case when source SO is an excimer laser (e.g., based on KrF, ArF or F2 lasing), for example.
The beam B can subsequently intercept patterning device MA, which is held on a patterning device table T. Having traversed patterning device MA, the beam B can pass through the lens PL, which focuses beam B onto target portion C of substrate W. With the aid of the second positioning means (and interferometric measuring means IF), the substrate table WT can be moved accurately, e.g. to position different target portions C in the path of beam B. Similarly, the first positioning means can be used to accurately position patterning device MA with respect to the path of beam B, e.g., after mechanical retrieval of the patterning device MA from a patterning device library, or during a scan. In general, movement of the tables T, WT can be realized with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning). However, in the case of a stepper (as opposed to a step-and-scan tool), patterning device table T may be connected to a short stroke actuator, or may be fixed.
The depicted tool can be used in two different modes, step mode and scan mode. In step mode, patterning device table T is kept essentially stationary, and an entire patterning device image is projected in one operation (i.e., a single “flash”) onto a target portion C. Substrate table WT can be shifted in the x or y directions so that a different target portion C can be irradiated by beam B. In scan mode, essentially the same scenario applies, except that a given target portion C is not exposed in a single “flash.” Instead, patterning device table T is movable in a given direction (e.g., the “scan direction”, or the “y” direction) with a speed v, so that projection beam B is caused to scan over a patterning device image. Concurrently, substrate table WT is simultaneously moved in the same or opposite direction at a speed V=Mv, in which M is the magnification of the lens (typically, M=1/4 or 1/5). In this manner, a relatively large target portion C can be exposed, without having to compromise on resolution.
In order for the substrates W (
An inspection apparatus, which may also be referred to as a metrology apparatus, is used to determine properties of the substrates W, and in particular, how properties of different substrates W vary or how properties associated with different layers of the same substrate W vary from layer to layer. The inspection apparatus may alternatively be constructed to identify defects on the substrate W and may, for example, be part of the lithocell LC, or may be integrated into the lithographic apparatus LA, or may even be a stand-alone device. The inspection apparatus may measure the properties using an actual substrate (e.g., a charged particle—SEM—image of a wafer pattern) or an image of an actual substrate, on a latent image (image in a resist layer after the exposure), on a semi-latent image (image in a resist layer after a post-exposure bake step PEB), on a developed resist image (in which the exposed or unexposed parts of the resist have been removed), on an etched image (after a pattern transfer step such as etching), or in other ways.
The computer system CS may use (part of) a design layout to be patterned to predict which resolution enhancement techniques to use and to perform computational lithography simulations and calculations to determine which mask layout and lithographic apparatus settings achieve the largest overall process window of the patterning process (depicted in
The metrology apparatus (tool) MT may provide input to the computer system CS to enable accurate simulations and predictions, and may provide feedback to the lithographic apparatus LA to identify possible drifts, e.g. in a calibration status of the lithographic apparatus LA (depicted in
In lithographic processes, it is desirable to make frequent measurements of the structures created, e.g., for process control and verification. Tools to make such measurements include metrology tool (apparatus) MT. Different types of metrology tools MT for making such measurements are known, including scanning electron microscopes (SEM) or various forms of scatterometer metrology tools MT. In some embodiments, metrology tools MT are or include an SEM.
In some embodiments, metrology tools MT are or include a spectroscopic scatterometer, an ellipsometric scatterometer, or other light based tools. A spectroscopic scatterometer may be configured such that the radiation emitted by a radiation source is directed onto target features of a substrate and the reflected or scattered radiation from the target is directed to a spectrometer detector, which measures a spectrum (i.e. a measurement of intensity as a function of wavelength) of the specular reflected radiation. From this data, the structure or profile of the target giving rise to the detected spectrum may be reconstructed, e.g. by Rigorous Coupled Wave Analysis and non-linear regression or by comparison with a library of simulated spectra. An ellipsometric scatterometer allows for determining parameters of a lithographic process by measuring scattered radiation for each polarization states. Such a metrology tool (MT) emits polarized light (such as linear, circular, or elliptic) by using, for example, appropriate polarization filters in the illumination section of the metrology apparatus. A source suitable for the metrology apparatus may provide polarized radiation as well.
As described above, fabricated devices (e.g., patterned substrates) may be inspected at various points during manufacturing.
When the substrate 70 is irradiated with electron beam 52, secondary electrons are generated from the substrate 70. The secondary electrons are deflected by the E×B deflector 60 and detected by a secondary electron detector 72. A two-dimensional electron beam image can be obtained by detecting the electrons generated from the sample in synchronization with, e.g., two dimensional scanning of the electron beam by beam deflector 58 or with repetitive scanning of electron beam 52 by beam deflector 58 in an X or Y direction, together with continuous movement of the substrate 70 by the substrate table ST in the other of the X or Y direction. Thus, in some embodiments, the electron beam inspection apparatus has a field of view for the electron beam defined by the angular range into which the electron beam can be provided by the electron beam inspection apparatus (e.g., the angular range through which the deflector 60 can provide the electron beam 52). Thus, the spatial extent of the field of the view is the spatial extent to which the angular range of the electron beam can impinge on a surface (wherein the surface can be stationary or can move with respect to the field).
As shown in
The secondary charged particle detector module 585 detects secondary charged particles 593 emitted from the sample surface (maybe also along with other reflected or scattered charged particles from the sample surface) upon being bombarded by the charged particle beam probe 592 to generate a secondary charged particle detection signal 594. The image forming module 586 (e.g., a computing device) is coupled with the secondary charged particle detector module 585 to receive the secondary charged particle detection signal 594 from the secondary charged particle detector module 585 and accordingly form at least one scanned image. In some embodiments, the secondary charged particle detector module 585 and image forming module 586, or their equivalent designs, alternatives or any combination thereof, together form an image forming apparatus which forms a scanned image from detected secondary charged particles emitted from sample 590 being bombarded by the charged particle beam probe 592.
In some embodiments, a monitoring module 587 is coupled to the image forming module 586 of the image forming apparatus to monitor, control, etc. the patterning process or derive a parameter for patterning process design, control, monitoring, etc. using the scanned image of the sample 590 received from image forming module 586. In some embodiments, the monitoring module 587 is configured or programmed to cause execution of an operation described herein. In some embodiments, the monitoring module 587 comprises a computing device. In some embodiments, the monitoring module 587 comprises a computer program configured to provide functionality described herein. In some embodiments, a probe spot size of the electron beam in the system of
Electron source 501, Coulomb aperture plate 571, condenser lens 510, source conversion unit 520, beam separator 533, deflection scanning unit 532, and primary projection system 530 may be aligned with a primary optical axis of tool 504. Secondary projection system 550 and electron detection device 540 may be aligned with a secondary optical axis 551 of tool 504.
Controller 509 may be connected to various components, such as source conversion unit 520, electron detection device 540, primary projection system 530, or a motorized stage. In some embodiments, as explained in further details below, controller 509 may perform various image and signal processing functions. Controller 509 may also generate various control signals to control operations of one or more components of the charged particle beam inspection system.
Deflection scanning unit 532, in operation, is configured to deflect primary beamlets 511, 512, and 513 to scan probe spots 521, 522, and 523 across individual scanning areas in a section of the surface of wafer 508. In response to incidence of primary beamlets 511, 512, and 513 or probe spots 521, 522, and 523 on wafer 508, electrons emerge from wafer 508 and generate three secondary electron beams 561, 562, and 563. Each of secondary electron beams 561, 562, and 563 typically comprise secondary electrons (having electron energy≤50 eV) and backscattered electrons (having electron energy between 50 eV and the landing energy of primary beamlets 511, 512, and 513). Beam separator 533 is configured to deflect secondary electron beams 561, 562, and 563 towards secondary projection system 550. Secondary projection system 550 subsequently focuses secondary electron beams 561, 562, and 563 onto detection elements 541, 542, and 543 of electron detection device 540. Detection elements 541, 542, and 543 are arranged to detect corresponding secondary electron beams 561, 562, and 563 and generate corresponding signals which are sent to controller 509 or a signal processing system (not shown), e.g., to construct images of the corresponding scanned areas of wafer 508.
In some embodiments, detection elements 541, 542, and 543 detect corresponding secondary electron beams 561, 562, and 563, respectively, and generate corresponding intensity signal outputs (not shown) to an image processing system (e.g., controller 509). In some embodiments, each detection elements 541, 542, and 543 may comprise one or more pixels. The intensity signal output of a detection element may be a sum of signals generated by all the pixels within the detection element.
In some embodiments, controller 509 may comprise an image processing system that includes an image acquirer (not shown) and a storage (not shown). The image acquirer may comprise one or more processors. For example, the image acquirer may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, and the like, or a combination thereof. The image acquirer may be communicatively coupled to electron detection device 540 of tool 504 through a medium such as an electrical conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, among others, or a combination thereof. In some embodiments, the image acquirer may receive a signal from electron detection device 540 and may construct an image. The image acquirer may thus acquire images of wafer 508. The image acquirer may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, and the like. The image acquirer may be configured to perform adjustments of brightness and contrast, etc. of acquired images. In some embodiments, the storage may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), other types of computer readable memory, and the like. The storage may be coupled with the image acquirer and may be used for saving scanned raw image data as original images, and post-processed images.
In some embodiments, the image acquirer may acquire one or more images of a sample based on one or more imaging signals received from electron detection device 540. An imaging signal may correspond to a scanning operation for conducting charged particle imaging. An acquired image may be a single image comprising a plurality of imaging areas or may involve multiple images. The single image may be stored in the storage. The single image may be an original image that may be divided into a plurality of regions. Each of the regions may comprise one imaging area containing a feature of wafer 508. The acquired images may comprise multiple images of a single imaging area (e.g., an FOV) of wafer 508 sampled multiple times over a time sequence or may comprise multiple images of different imaging areas of wafer 508. The multiple images may be stored in the storage. In some embodiments, controller 509 may be configured to perform image processing steps with the multiple images of the same location of wafer 508.
In some embodiments, controller 509 may include measurement circuitries (e.g., analog-to-digital converters) to obtain a distribution of the detected secondary electrons. The electron distribution data collected during a detection time window, in combination with corresponding scan path data of each of primary beamlets 511, 512, and 513 incident on the wafer surface, can be used to reconstruct images of the wafer structures under inspection. The reconstructed images can be used to reveal various features of the internal or external structures of wafer 508, and thereby can be used to reveal any defects that may exist in the wafer.
In some embodiments, controller 509 may control the motorized stage to move wafer 508 during inspection of wafer 508. In some embodiments, controller 509 may enable the motorized stage to move wafer 508 in a direction continuously at a constant speed. In other embodiments, controller 509 may enable the motorized stage to change the speed of the movement of wafer 508 over time depending on the steps of scanning process.
Although electron beam tool 504 as shown in
As described above, it may be desirable to use one or more tools to produce results that, for example, can be used to design, control, monitor, etc., a patterning process. One or more tools used in computationally controlling, designing, etc. one or more aspects of the patterning process, such as the pattern design for a patterning device (including, for example, adding sub-resolution assist features or optical proximity corrections), the illumination for the patterning device, etc., may be provided. Accordingly, in a system for computationally controlling, designing, etc. a manufacturing process involving patterning, the manufacturing system components or processes can be described by various functional modules or models. In some embodiments, one or more electronic (e.g., mathematical, parameterized, etc.) models may be provided that describe one or more steps or apparatuses of the patterning process. In some embodiments, a simulation of the patterning process can be performed using one or more electronic models to simulate how the patterning process forms a patterned substrate using a design pattern provided by a patterning device.
Images, from, e.g., the system of
It should be understood that the method of the present disclosure, while sometimes described in reference to an SEM, can be applied to or on any suitable metrology tool where determining optimal FOVs is advantageous, such as an SEM, an X-ray diffractometer, an ultrasound, an optical imaging device, etc. Additionally, the operations described herein can be applied in multiple metrology apparatuses, steps, or determinations.
In some embodiments, a non-transitory computer readable medium stores instructions which, when executed by a computer, cause the computer to execute one or more of operations 602-608, or other operations. The operations of method 600 are intended to be illustrative. In some embodiments, method 600 may be accomplished with one or more additional operations not described, or without one or more of the operations discussed. For example, in some embodiments, operations 602 and/or 608 may be eliminated from method 600. Additionally, the order in which the operations of method 600 are illustrated in
Returning to
The representation of the pattern layout may be and/or include all or substantially all of the patterns of a pattern layout. The representation may comprise a simulation, an image, an electronic file, a target polygon design, and/or other representations. The representation may include information describing patterns of the pattern layout themselves and/or information related to the patterns. The patterns may include the geometrical shapes of contours in the pattern layout and/or information related to the geometrical shapes. Using a semiconductor chip as an example, a representation of a pattern layout may include all (or substantially all) of the patterns that make up a chip design (e.g., including pattern layout structures configured to facilitate inspections and/or other operations). This may include channels, protrusions, vias, gratings, etc., as shown in a simulation, an image, a .GDS file, etc.
Grouping the patterns of the pattern layout into groups may be based on relative similarity of between patterns, and/or information associated with the patterns. For example, the grouping may be based on pattern polygons obtained directly from a layout design. In some embodiments, the pattern grouping may be based on pattern images or contours of the pattern layout, where the images or contours can be obtained from any suitable inspection or metrology system, or simulation. For example, the grouping may be based on aerial images, optical images, mask images, resist images, etch images, wafer image of the patterns as measured or simulated.
The patterns in a pattern layout may include two and/or three dimensional geometrical shapes, for example. The received representation includes data that describes the characteristics of the shapes (e.g., such as X-Y dimensional data points, a mathematical equation that describes the geometrical shape, etc.), processing parameters associated with the shapes, and/or other data. In some embodiments, the representation of the pattern layout may comprise inspection results from an after development inspection (ADI) for the pattern layout (e.g., from a previously inspected wafer), a model of the pattern in the pattern layout, and/or other information. The inspection results from the after development inspection for the pattern layout may be obtained from an SEM, an optical metrology tool, and/or other sources. In some embodiments, the patterns may be obtained from aerial images, mask images, etch images, or etc., that result from a resist model, an optical model, an etch model, an etch bias model and/or other modelling sources. In some embodiments, the representation of the pattern layout comprises a .GDS file, a .GDSII file, a .OASIS file, and/or an electronic file having other file formats, and/or another electronic representation of the pattern layout.
Pattern grouping may be based on this information, for example. Individual patterns (which may include identical and/or similar patterns as described above) may have repeating instances across a full pattern layout. Individual patterns may be identified, with repeating (identical or nearly identical, e.g., similar or like) patterns grouped together. The grouping may be performed, for example, by exact and/or fuzzy matching algorithms, clustering, machine learning, or any other grouping method or process that is known in the art. Repeating patterns may be grouped across the full pattern layout.
At operation 604, a set of candidate FOVs are determined. As described above, an FOV includes a portion of the pattern layout. The candidate FOVs may be determined based on constraints on characteristics of a given field of view, the pattern groups of the pattern layout, a generation method, and/or other information.
The characteristics of a given FOV may comprise a distance from the given FOV to another FOV, a size of the given FOV, and/or other characteristics. Constraints on these characteristics may include, for example, a minimum threshold distance between FOVs, a (minimum, maximum, prescribed threshold, allowable, etc.) size of an FOV, an actual size of the FOV for a given SEM, and/or other constraints. The distance from a given FOV to another FOV may be a distance across a pattern layout between the closest (e.g., rectangular) edges of the two FOVs. The distance from a given FOV to another FOV may be a distance in an “x” direction across a pattern layout, a “y” direction, and/or a combination thereof. The distance between FOVs may be large enough to prevent charging of imaged structures by an SEM, provide clear and separate images of pattern structures in each FOV, and/or may be configured in other ways. In some embodiments, the distance from a given FOV to another FOV is at least about 1-4 μm, depending on the inspection tool.
The size of an FOV may comprise the area imaged in the FOV, and/or the extent of an area of the pattern layout that fits within an FOV. Depending on the shape of the FOV, an FOV may have a length, width, diameter, radii, and/or other dimensions that describe the size of the FOV. Typically the size of an FOV is SEM (or other metrology tool) dependent. In some embodiments, the size of a FOV is about 1-12 square μm, depending on the inspection tool.
In some embodiments, determining the set of candidate FOVs is based on the pattern groups in a pattern layout, a candidate FOV generation method, and/or other factors. For example, in some embodiments, determining the set of candidate FOVs based on pattern groups of the pattern layout and/or based on a candidate FOV generation method comprises determining the set of candidate FOVs based on an initial list of pattern locations and matching information for the pattern groups. This may be a seed pattern list is a list comprising a baseline or initial listing of FOVs that cover certain target pattern groups of interest provided for SEM inspection. Determining the set of candidate FOVs based on a list of pattern locations and matching information for the pattern groups may comprise matched instance pattern replacement for the set of candidate FOVs, for example. The matched instance pattern replacement comprises pattern matching of patterns in the pattern layout to produce pattern groups (e.g., operation 602), and selecting an alternate pattern from the same pattern group to replace a pattern in the pattern group.
For example,
In some embodiments, the candidate FOV generation method comprises FOV merging and/or shifting. FOV merging and/or shifting comprises combining patterns from different pattern groups into a single candidate field of view. FOV merging and/or shifting is based on a proximity of patterns from different pattern groups to each other and/or other information.
For example,
Returning to
The prescribed criteria is for combinations of FOVs included in the one or more subsets for scanning electron microscope (SEM) measurement and/or other metrology. The selected one or more subsets (e.g., lists) each comprises a number of FOVs that individually (e.g., within a list) and/or collectively (e.g., across a set of lists) meet the prescribed criteria. In some embodiments, the prescribed criteria is set such that patterns included in the one or more subsets of FOVs, in combination, represent an entirety of the pattern layout or a portion of the pattern layout. In some embodiments, the prescribed criteria causes inclusion of an optimally diverse group of patterns in a predetermined number of subsets (lists) of FOVs. The optimally diverse group of patterns comprises a plurality of patterns having geometries that, in combination, represent at least a threshold amount of the pattern layout, given the predetermined number of subsets of FOVs that form the determined one or more subsets. The predetermined number of subsets may be set by a user, determined automatically, and/or determined in other ways. In some embodiments, the predetermined number of subsets is minimized.
For example, in some embodiments, the selected one or more subsets (lists) of FOVs contain an optimally diverse set of pattern groups, in less than a prescribed limit number of subsets. The optimally diverse set of pattern groups comprises a plurality of pattern groups having geometries that, in combination, represent as much of the pattern layout as possible, given the predetermined number of subsets (lists) of FOVs that form the one or more selected subsets. Phrased another way, the selected one or more subsets (lists) may have FOVs that include as many geometrically unique patterns of the pattern layout as possible in a (minimum, maximum, prescribed threshold, allowable, etc.) allowable number of subsets (lists).
In some embodiments, the prescribed criteria comprises a pattern group diversity metric, a pattern group criticality metric, a subset (e.g., list) and/or FOV quantity metric, and/or other metrics. In some embodiments, the diversity metric may specify a pattern group count (e.g., the higher the pattern group count the higher the diversity), an amount and/or percentage of a pattern layout that is to be represented in the lists of FOVs, a range of patterns and/or pattern groups that should be included in the lists of FOVs, and/or other diversity metrics. In some embodiments, the criticality metric comprises a priority of a pattern group, a weight of a pattern group, a score associated with a pattern group, a weight order and/or order of importance of pattern groups, and/or other metrics. In some embodiments, a criticality metric can be any attribute used to define a pattern or pattern group priority (e.g., minimum CD, pattern density, etc.). In some embodiments, the subset and/or FOV quantity metric comprises a threshold number of lists and/or FOVs. In some embodiments, the prescribed criteria comprises inclusion of a maximum threshold number of lists and/or FOVs. The threshold number is configured to ensure that, in combination with other criteria, the FOVs included in the selected subset(s) (list(s)) provide adequate pattern overage, for example representing an entirety (or almost an entirety) of the pattern layout, for example.
A pattern group diversity metric, a pattern group criticality metric, a list and/or FOV quantity metric, and/or other criteria may be set by a user (e.g., via a user interface as described below); set automatically based on the patterns in the pattern layout and/or the pattern groups, the number of candidate FOVs of the pattern layout, and/or other information; and/or set in other ways. For example, user determined criteria may be configured such that the one or more subsets (lists) may be configured to include a (minimum, maximum, prescribed threshold, allowable, etc.) representative number of each geometrically unique pattern in the minimum (or fewest possible) number of FOVs.
According to embodiments of the present disclosure, FOV generation or optimization can include selecting the one or more subsets (e.g., lists of FOVs) comprises assigning FOVs including specific patterns to respective FOV lists by applying a graph based overlapping elimination algorithm. The graph based overlapping elimination algorithm comprises a graph coloring algorithm, where each FOV list corresponds to a color. The prescribed criteria is configured such that the graph based elimination and/or graph coloring algorithm outputs an optimally diverse group of patterns in a predetermined number of lists of FOVs.
For example,
According to other embodiments of the present disclosure, FOV generation or optimization can include selecting the one or more subsets comprises assigning FOVs including specific patterns to respective FOV lists by applying an integer linear programming algorithm. In some embodiments, selecting the one or more subsets comprises assigning FOVs including specific patterns to respective FOV lists by applying the integer linear programming algorithm. The prescribed criteria is configured such that the integer linear programming and/or graph coloring algorithm outputs an optimally diverse group of patterns in a predetermined number of lists of FOVs. The integer linear programming may enforce user defined constraints such that, for example, critical patterns and/or pattern groups are selected based on group weight, the total list count is less than a prescribed limit, pattern coverage is maximized with a minimum FOV count, etc.
For example,
Returning to
In some embodiments, the data associated with the SEM inspection according to the FOV lists can be used as calibration data for a physical, semi-physical or empirical model, or used as training data for training a machine learning model. In some embodiments, the data associated with the SEM inspection according to the FOV lists may be provided as input to a trained machine learning model for the purpose of generating a prediction (output) from the model (e.g., a prediction about a semiconductor manufacturing process). Providing may include electronically sending, uploading, and/or otherwise inputting information to a machine learning simulation model. In some embodiments, the simulation model may be integrally programmed with the instructions that cause others of operations 602-608 (e.g., such that no “providing” is required, and instead data simply flows directly to a simulation model).
For example, data may be provided to one or more machine learning simulation models. A simulation model may be configured to predict an impact one or more geometrically unique features may have on the patterning process (e.g., as described above). For example, a machine learning model may be associated with optical proximity correction (OPC), hotspot or defect prediction, and/or source mask optimization (SMO) for a semiconductor lithography process, and/or other operations. Selecting optimal subset(s) (list(s)) of FOVs for training can save runtime during model training and/or execution operations, and/or have other advantages.
Adjustments to a semiconductor manufacturing process may be made based on the SEM inspection, model outputs, and/or other information. Adjustments may including changing one or more semiconductor manufacturing process parameters, for example. Adjustments may include pattern parameter changes (e.g., sizes, locations, and/or other design variables), and/or any adjustable parameter such as an adjustable parameter of the etching system, the source, the patterning device, the projection optics, dose, focus, etc. Parameters may be automatically or otherwise electronically adjusted by a processor (e.g., a computer controller), modulated manually by a user, or adjusted in other ways. In some embodiments, parameter adjustments may be determined (e.g., an amount a given parameter should be changed), and the parameters may be adjusted from prior parameter set points to new parameter set points, for example.
Computer system CS may be coupled via bus BS to a display DS, such as a cathode ray tube (CRT) or flat panel or touch panel display for displaying information to a computer user. An input device ID, including alphanumeric and other keys, is coupled to bus BS for communicating information and command selections to processor PRO. Another type of user input device is cursor control CC, such as a mouse, a trackball, or cursor direction keys for communicating direction information and command selections to processor PRO and for controlling cursor movement on display DS. This input device typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), that allows the device to specify positions in a plane. A touch panel (screen) display may also be used as an input device.
In some embodiments, portions of one or more methods described herein may be performed by computer system CS in response to processor PRO executing one or more sequences of one or more instructions contained in main memory MM. Such instructions may be read into main memory MM from another computer-readable medium, such as storage device SD. Execution of the sequences of instructions included in main memory MM causes processor PRO to perform the process steps (operations) described herein. One or more processors in a multi-processing arrangement may also be employed to execute the sequences of instructions contained in main memory MM. In some embodiments, hard-wired circuitry may be used in place of or in combination with software instructions. Thus, the description herein is not limited to any specific combination of hardware circuitry and software.
The term “computer-readable medium” as used herein refers to any medium that participates in providing instructions to processor PRO for execution. Such a medium may take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media include, for example, optical or magnetic disks, such as storage device SD. Volatile media include dynamic memory, such as main memory MM. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise bus BS. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Computer-readable media can be non-transitory, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CD-ROM, DVD, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM, any other memory chip or cartridge. Non-transitory computer readable media can have (machine-readable) instructions recorded thereon. The instructions, when executed by a computer, can implement any of the operations described herein. Transitory computer-readable media can include a carrier wave or other propagating electromagnetic signal, for example.
Various forms of computer readable media may be involved in carrying one or more sequences of one or more machine-readable instructions to processor PRO for execution. For example, the instructions may initially be borne on a magnetic disk of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instructions over a telephone line using a modem. A modem local to computer system CS can receive the data on the telephone line and use an infrared transmitter to convert the data to an infrared signal. An infrared detector coupled to bus BS can receive the data carried in the infrared signal and place the data on bus BS. Bus BS carries the data to main memory MM, from which processor PRO retrieves and executes the instructions. The instructions received by main memory MM may optionally be stored on storage device SD either before or after execution by processor PRO.
By way of an example, for an SEM (e.g., as described above), a computer readable medium may be provided that stores instructions for a processor (PRO) of a controller (e.g., CS) to carry out image inspection, image acquisition, activating a charged-particle source, adjusting electrical excitation of stigmators, adjusting landing energy of electrons, adjusting objective lens excitation, adjusting secondary electron detector position and orientation, stage motion control, beam separator excitation, applying scan deflection voltages to beam deflectors, receiving and processing data associated with signal information from electron detectors, configuring an electrostatic element, detecting signal electrons, adjusting the control electrode potential, adjusting the voltages applied to the electron source, extractor electrode, and the sample, etc.
Computer system CS may also include a communication interface CI coupled to bus BS. Communication interface CI provides a two-way data communication coupling to a network link NDL that is connected to a local network LAN. For example, communication interface CI may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, communication interface CI may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. Wireless links may also be implemented. In any such implementation, communication interface CI sends and receives electrical, electromagnetic, or optical signals that carry digital data streams representing various types of information.
Network link NDL typically provides data communication through one or more networks to other data devices. For example, network link NDL may provide a connection through local network LAN to a host computer HC. This can include data communication services provided through the worldwide packet data communication network, now commonly referred to as the “Internet” INT. Local network LAN (Internet) may use electrical, electromagnetic, or optical signals that carry digital data streams. The signals through the various networks and the signals on network data link NDL and through communication interface CI, which carry the digital data to and from computer system CS, are exemplary forms of carrier waves transporting the information.
Computer system CS can send messages and receive data, including program code, through the network(s), network data link NDL, and communication interface CI. In the Internet example, host computer HC might transmit a requested code for an application program through Internet INT, network data link NDL, local network LAN, and communication interface CI. One such downloaded application may provide all or part of a method described herein, for example. The received code may be executed by processor PRO as it is received, or stored in storage device SD, or other non-volatile storage for later execution. In this manner, computer system CS may obtain application code in the form of a carrier wave.
The concepts disclosed herein may be used with any imaging, etching, polishing, inspection, etc. system for sub wavelength features, and may be useful with emerging imaging technologies capable of producing increasingly shorter wavelengths. Emerging technologies include EUV (extreme ultra violet), DUV lithography that is capable of producing a 193 nm wavelength with the use of an ArF laser, and even a 157 nm wavelength with the use of a Fluorine laser. Moreover, EUV lithography is capable of producing wavelengths within a range of 20-50 nm by using a synchrotron or by hitting a material (either solid or a plasma) with high energy electrons in order to produce photons within this range. Embodiments of the present disclosure can be further described by the following clauses.
1. A method for selecting one or more subsets of fields of view of a pattern layout, the method comprising:
2. The method of clause 1, further comprising grouping patterns of the pattern layout into the pattern groups, the grouping comprising pattern matching to produce the pattern groups.
3. The method of clause 1 or 2, wherein each of the one or more subsets corresponds to a field of view list.
4. The method of any of clauses 1-3, wherein a field of view includes a portion of the pattern layout.
5. The method of any of clauses 1-4, wherein a subset of fields of view comprises a list of fields of view selected from the set of candidate fields of view.
6. The method of any of clauses 1-5, wherein selecting the one or more subsets comprises assigning fields of view including specific patterns to respective fields of view lists by applying a graph based overlapping elimination algorithm.
7. The method of clause 6, wherein the graph based overlapping elimination algorithm comprises a graph coloring algorithm, and wherein each field of view list corresponds to a color.
8. The method of clause 6 or 7, wherein the graph based elimination and/or graph coloring algorithm outputs a diverse group of patterns in a predetermined number of lists of fields of view based on the prescribed criteria.
9. The method of any of clauses 1-5, wherein selecting the one or more subsets comprises assigning fields of view including specific patterns to respective fields of view lists by applying an integer linear programming algorithm.
10. The method of clause 9, wherein selecting the one or more subsets comprises assigning fields of view including specific patterns to respective fields of view lists by applying the integer linear programming algorithm and a graph coloring algorithm, wherein each field of view list corresponds to a color.
11. The method of clause 9 or 10, wherein the prescribed criteria is configured such that the integer linear programming and/or graph coloring algorithm outputs an optimally diverse group of patterns in a predetermined number of lists of fields of view.
12. The method of any of clauses 1-11, wherein determining the set of candidate fields of view is further based constraints on characteristics of a given field of view.
13. The method of clause 12, wherein the characteristics of a given field of view comprise a distance from the given field of view to another field of view and/or a size of the given field of view.
14. The method of any of clauses 1-13, wherein determining the set of candidate fields of view is further based on a generation method comprising matched instance pattern replacement for the set of candidate fields of view.
15. The method of clause 14, wherein the matched instance pattern replacement comprises pattern matching of patterns in the pattern layout to produce pattern groups, and selecting an alternate pattern from the same pattern group to replace a pattern in the pattern group.
16. The method of any of clauses 1-15, wherein determining the set of candidate fields of view is based on a generation method comprising field of view merging and/or shifting.
17. The method of clause 16, wherein field of view merging and/or shifting comprises combining patterns from different pattern groups into a single candidate field of view.
18. The method of clause 16 or 17, wherein field of view merging and/or shifting is based on a proximity of patterns from different pattern groups to each other.
19. The method of any of clauses 1-18, wherein the prescribed criteria comprises a pattern group diversity metric.
20. The method of any of clauses 1-19, wherein the prescribed criteria comprises a pattern group criticality metric.
21. The method of clause 20, wherein the pattern group criticality metric comprises a weight of a pattern group.
22. The method of any of clauses 1-21, wherein the prescribed criteria comprises a subset and/or fields of view quantity metric.
23. The method of any of clauses 1-22, wherein determining the set of candidate fields of view based on pattern groups of the pattern layout comprises determining the set of candidate fields of view based on a list of pattern locations and matching information for the pattern groups.
24. The method of any of clauses 1-23, wherein the prescribed criteria is set such that patterns included in the one or more subsets of fields of view in combination represent an entirety of the pattern layout or a portion of the pattern layout.
25. The method of any of clauses 1-24, wherein the prescribed criteria causes inclusion of an optimally diverse group of patterns in a predetermined number of subsets of fields of view.
26. The method of clause 25, wherein the optimally diverse group of patterns comprises a plurality of patterns having geometries that, in combination, represent at least a threshold amount of the pattern layout, given the predetermined number of subsets that form the determined one or more subsets.
27. The method of clause 25 or 26, wherein the predetermined number of subsets is set by a user.
28. The method of any of clauses 25-27, wherein the predetermined number of subsets is minimized.
29. The method of any of clauses 1-28, further comprising providing the determined one or more subsets of fields of view as input for model calibration, critical dimension (CD) metrology, and/or defect inspection for a semiconductor lithography process.
30. The method of any of clauses 1-29, wherein the pattern layout comprises a design layout for a semiconductor wafer.
31. The method of any of clauses 1-30, wherein selecting the one or more subsets comprises assigning fields of view including specific patterns to respective fields of view lists by applying an integer linear programming algorithm, wherein the criteria is defined as constraint cliques.
32. A non-transitory computer readable medium having instructions thereon, the instructions when executed by a computer causing the computer to perform the method of any of clauses 1-30.
33. A system for selecting one or more subsets of fields of view of a pattern layout, the system comprising one or more processors configured by machine readable instructions to perform the method of any of clauses 1-30.
34. A non-transitory computer readable medium having instructions thereon, the instructions when executed by a computer causing the computer to perform a method for selecting one or more lists of fields of view of a pattern layout, the method comprising:
35. The medium of clause 34, wherein determining the set of candidate fields of view is further based on a generation method for the set of candidate fields of view comprising matched instance seed pattern replacement and/or field of view merging and/or shifting.
36. The medium of clause 34, wherein the prescribed criteria comprises a pattern group diversity metric, a pattern group weight, and/or a list and/or field of view quantity metric.
37. The medium of clause 34, wherein the optimally diverse group of patterns comprises a plurality of patterns having geometries that, in combination, represent at least a threshold amount of the pattern layout, given a number of lists in the determined one or more lists.
38. The medium of clause 34, the method further comprising providing the one or more lists of fields of view as input for model calibration, critical dimension (CD) metrology, and/or defect inspection for a semiconductor lithography process.
While the concepts disclosed herein may be used for manufacturing with a substrate such as a silicon wafer, it shall be understood that the disclosed concepts may be used with any type of manufacturing system (e.g., those used for manufacturing on substrates other than silicon wafers).
In addition, the combination and sub-combinations of disclosed elements may comprise separate embodiments. For example, one or more of the operations described above may be included in separate embodiments, or they may be included together in the same embodiment.
The descriptions above are intended to be illustrative, not limiting. Thus, it will be apparent to one skilled in the art that modifications may be made as described without departing from the scope of the claims set out below.
| Number | Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/077061 | Feb 2022 | WO | international |
This application claims priority of International application PCT/CN2022/077061 which was filed on Feb. 21, 2022 and which is incorporated herein in its entirety by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2023/052215 | 1/31/2023 | WO |
