This Disclosure relates to semiconductor devices, more particularly to vertical trench gate metal oxide semiconductor field effect transistors (MOSFETs).
One type of power MOSFET is a trench gate MOSFET which is designed to handle significant power and to provide a high-power drive capability by vertically conducting current from a top surface to a bottom surface of the semiconductor die. The trench gate MOSFET in its active region generally includes a large number of parallel connected active trench gate MOSFET cells each including a trench formed in the semiconductor die, with each active trench having surrounding source regions and oppositely-doped body regions, and where the trenches are deep enough to cross through the body regions to a drift region below the top surface of the semiconductor die.
Each active trench gate cell has a gate stack buried in the trench comprising a gate electrode generally including doped polysilicon and a gate dielectric. The gate electrodes when appropriately biased controls the current conduction in the body region in their vicinity by virtue of the field effect that enables the MOSFET cells to be turned on, thus enabling current to flow between the source and the drain that has a drain contact on a bottom side of the semiconductor die.
This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. Various disclosed methods and devices of the present disclosure may be beneficially applied to transistors and integrated circuits that include trench field plates. While such embodiments may be expected to reduce defects, e.g. leakage between trench gates a surrounding source region, no particular result is a requirement unless explicitly recited in a particular claim.
Future generation trench gate MOSFETS may require a 2× thicker field plate dielectric layer along the trench (trench wall dielectric) to accommodate a 100 V operating voltage as compared to 45 V technology, the thicker field plate dielectric providing a higher dielectric breakdown voltage. However, the inventors have discovered that a thicker trench wall dielectric layer may result in significant recess in the top portion of the sidewall of the trench wall dielectric layer during a wet etch process that takes place before a bottom dielectric (e.g., silicon oxide) layer is grown to isolate the gate electrode from the field plate. This undercut can result in defects in the gate dielectric in which the gate dielectric is significantly thinner in the recess than at the rest of the gate electrode, degrading the electrical isolation between the gate electrode and the field plate. Such defects can cause significant current leakage between the gate and the source, resulting in yield loss.
The inventors have discovered that such defects may be reduced or eliminated by thinning down a small portion of the top trench wall dielectric layer at the top of the trench field plate. Where a baseline device may have a field plate with two widths (a double-width field plate), the addition of the thin trench wall dielectric layer portion results in a field plate with three different widths (a triple-width field plate) a corresponding trench wall dielectric layer with three different thicknesses along the field plate in the height/thickness direction of the trench. Although examples are described herein having three different polysilicon widths for the field plate, it is possible to also have four or more polysilicon widths for the field plate.
Disclosed aspects include a trench gate MOSFET device that has a substrate with a semiconductor surface layer doped a first conductivity type. At least one trench gate MOSFET cell is located in or over the semiconductor surface layer, and includes a body region in the semiconductor surface layer doped a second conductivity type, and a source region on top of the body region doped the first conductivity type. A trench extends down from a top side of the semiconductor surface layer, the trench abutting the body region and being lined with a dielectric material. A field plate that includes polysilicon is located in the trench, and a gate electrode is located over the field plate. The field plate has a bottom portion, a middle portion, and a top portion, wherein the bottom portion is narrower than the middle portion, and the middle portion is narrower than the top portion.
Disclosed aspects further include a method of fabricating a transistor. The method includes forming a plurality of trenches in a semiconductor layer over a semiconductor substrate, the plurality of trenches including a first trench and a second trench. A gate dielectric layer is formed on first and second sidewalls of the trench, and a gate electrode between the first and second sidewalls. A dielectric liner is formed on the first and second sidewalls, the dielectric liner having a first portion at a bottom of the trench with a first thickness, a second portion between the first portion and the gate dielectric layer with a second thickness less than the first thickness, and a third portion between the second portion and the gate dielectric layer with a third thickness less than the second thickness. A conductive field plate is formed in the trench, the field plate having a bottom portion with a first width, a middle portion between the bottom portion and the gate electrode with a second width greater than the first width, and a top portion between the middle portion and the gate electrode with a third width greater than the second width.
Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, wherein:
Example aspects are described with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. Illustrated ordering of acts or events should not be considered as limiting, as some acts or events may occur in different order and/or concurrently with other acts or events. Furthermore, some illustrated acts or events may not be required to implement a methodology in accordance with this disclosure.
Also, the terms “connected to” or “connected with” (and the like) as used herein without further qualification are intended to describe either an indirect or direct electrical connection. Thus, if a first device “connects” to a second device, that connection can be through a direct electrical connection where there are only parasitics in the pathway, or through an indirect electrical connection via intervening items including other devices and connections. For indirect connecting, the intervening item generally does not modify the information of a signal
The active region has a plurality of active trench gate MOSFET cells 105 with their polysilicon gates 105a shown, with their length direction being oriented parallel to one another. The trench gate MOSFET device 100 is shown formed on a substrate 109, e.g. n+ doped (about 1019 cm−3 to about 1021 cm−3), that provides a drain for the device 100. The substrate 109 has having an epitaxial surface layer 108 thereon of the same conductivity type and lightly doped (about 1014 cm−3 to about 1018 cm−3). Although not shown, there is generally a metal drain contact layer (e.g., Ti/Ni/Ag) on the bottom side of the substrate 109.
The junction termination trench 130 provides the junction termination region that surrounds the active region for the MOSFET device 100 that enables the MOSFET device 100 to sustain a higher drain to source breakdown voltage (BV). The junction termination trench 130 is generally connected to a field plate 105b (
The active area as described below in
The field plate 105b comprises a bottom portion 105b1, a middle portion 105b2, and a top portion 105b3, all in the active area 210 of the trench gate MOSFET device 200. A trench wall dielectric layer 105c, e.g. silicon oxide, comprises a bottom portion 105c1, a middle portion 105c2, and a top portion 105c3. The triple width arrangement of the field plate 105b is distinct from a double width field plate structure without a breakdown voltage degradation. The top portion 105c3 of the trench dielectric wall dielectric 105b, because it occupies a comparatively small portion of the trench wall dielectric's total height, has a generally minimal impact on the BV between the gate electrode 105a and the source region 103, which is typically conductively connected on the semiconductor die to the field plate.
In some examples, the height (in a direction normal to the top surface of the surface layer 108) of the bottom portion 105b1 may be in a range from 3 μm to 4 μm, the height of the middle portion 105b2 may be in a range from 0.7 μm to 1.5 μm, the height of the top portion 105c3 may be in a range from 1,000 Å to 5,000 Å, and the total height of the field plate 105b may be in a range from 3.8 μm to 5.6 μm. In some examples, the thickness (parallel to the top surface of the surface layer 108) of the bottom portion 105b1 may be in a range from 1,000 Å to 3,000 Å, the thickness of the middle portion 105b2 may be in a range from 5,000 Å to 11,000 Å, and the thickness of the top portion 105b3 may be in a range from 7,000 Å to 13,000 Å. In some examples, the thickness (parallel to the top surface of the surface layer 108) of the bottom portion 105c1 of the trench wall dielectric layer 105c may be in a range from 3,000 Å to 8,000 Å, the thickness of the middle portion 105c2 may be in a range from 1,500 Å to 2,500 Å, and the thickness of the top portion 105c3 may be in a range from 700 Å to 1,300 Å.
In a more specific example, presented without implied limitation, the height of the bottom portion 105b1 may be about 3.4 μm, the height of the middle portion 105b2 may be about 1.1 μm, and the height of the top portion may be about 3,000 Å; the thickness of the bottom portion 105b1 may be about 2,000 Å, the thickness of the middle portion 105b2 may be about 8,000 Å, and the thickness of the top portion 105b3 may be about 1 μm; and the thickness of the bottom portion 105c1 may be about 5,000 Å, the thickness of the middle portion 105c2 may be about 2,000 Å, and the thickness of the top portion 105c3 may be about 1,000 Å
In the case that the field plates 105b are formed from doped polysilicon, the polysilicon can be doped (e.g., n+ or p+), which can comprise in-situ doping during the polysilicon deposition, or ion implantation of undoped polysilicon with one or more dopant ions. Alternatively, because the field plate 105b does not conduct any electrical current during trench gate MOSFET device operation, the field plate can also comprise undoped polysilicon.
The source regions 103 are shown as n+ doped for acting as a source for the active trench gate MOSFET cells 105 formed with the body regions 102. The active trench MOSFET cells 105 generally have a polysilicon gate 105a with a gate dielectric layer 105d below the polysilicon gate 105a and between the sidewalls of the polysilicon gate 105a and the body region 102 and the source region 103. The total gate dielectric layer 105d thickness may be in a range from 100 Å to 10,000 Å. The triple shield field plate 105b portions 105b1, 105b2 and 105b3 are shown below the gate dielectric layer 105d under the polysilicon gate 105a. The gate 105a, the source region 103, and the substrate 109 operates as a 3-terminal trench gate MOSFET cell 105, with the source region 103 being tied to the body region 102.
The polysilicon gates 105a are optionally shown having gate recesses (indentations) that have a pre-metal dielectric (PMD) layer 124 above that also fills the gate recesses. Recessed gates may provide more process margin for the source contacts.
The trench dielectric layer 105c comprising portions 105c1, 105c2, and 105c3 can comprise thermal silicon oxide with a deposited dielectric layer thereon, that may also comprise silicon oxide, or another dielectric material such as silicon nitride or silicon oxynitride, or a material comprising a high-k dielectric (e.g., k>5) such as HfO2. A metal 1 (M1) layer is over and fills contact apertures formed in the PMD layer 124 shown with a metal contact 118a connecting the source region 103 and body region 102 of the active trench gate MOSFET cells 105, and a metal contact 118b providing a common connection to the polysilicon gates 105a of the active trench gate MOSFET cells 105.
A process flow is now described performing a disclosed trench gate MOSFET device including a triple field plate.
Gate polysilicon deposition and patterning follows to form the polysilicon gates 105a shown with optional polysilicon gate recesses, followed by the deposition of the PMD layer 124 which also fills the gate recesses, followed by contact aperture formation through the PMD layer 124 to expose the source region 103 and body region 102 shown recessed into the silicon, and to expose the polysilicon gates 105a. As described above the polysilicon gates are doped. Metal 1 formation follows to provide metal contacts including metal contacts 118a to source region 103 and body region 102, and another metal contact that is not shown in
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The addition of the wider top portion 105b3 is an innovative solution to the undercut issue described previously. Unlike the double-width field plate of some baseline devices, the top portion 105b3 has no significant effect on the electrical operation of transistors employing this feature. Whereas the double-width field plate is typically used to make more uniform the electrical fields in the drift region of the surface layer 108, this advantage is not generally applicable at the top of the field plate 105b, where the electric field is substantially reduced relative to the bottom of the field plate 105b. While providing little to no electrical benefit, the wider top portion 105b3 provides significant processing benefit by reducing the area available for a wet etch, e.g. an HF etch, to attack the dielectric liner 105c3 while removing the dielectric liner 105c from the trench sidewalls in preparation to form a clean gate dielectric layer above the field plate 105b. Moreover, while a thinner dielectric liner dielectric might otherwise result in reduced voltage capacity of the transistor, the described implementations include the realization that such a thinner dielectric liner adjacent the gate 105a can be used to increase the process margin of the transistor while not sacrificing voltage range due to the reduced electric field near the body region 102. Absent this realization, there is no motivation to add the wider top portion 105b3 to the double-width field plate.
Disclosed aspects are further illustrated by the following specific Examples, which should not be construed as limiting the scope or content of this Disclosure in any way.
Probe yield based on the parameter Igss (the gate to source leakage measured at 12 V) of a disclosed trench gate n-channel MOSFET device having a triple width field plate compared to Igss probe yield data of a trench gate n-channel MOSFET device having a double width field plate demonstrated a probe yield about four times higher for the triple width field plate MOSFET device as compared to the double width field plate MOSFET device.
Disclosed aspects can be used to form trench gate MOSFET devices comprising a semiconductor die that may be integrated into a variety of assembly flows to form a variety of different devices and related products. The semiconductor die may include various elements therein and/or layers thereon, including barrier layers, dielectric layers, device structures, active elements and passive elements including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. Moreover, the semiconductor die can be formed from a variety of processes including bipolar, Insulated Gate Bipolar Transistor (IGBT), CMOS, BiCMOS and MEMS.
Those skilled in the art to which this Disclosure relates will appreciate that many other aspects are possible within the scope of the claimed invention, and further additions, deletions, substitutions and modifications may be made to the described aspects without departing from the scope of this Disclosure.
Number | Date | Country | Kind |
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202111091799.6 | Sep 2021 | CN | national |