Patent Application
20150214338
Embodiments of the invention relate generally to fin-shaped field effect transistors (FinFETs) which may include silicon germanium (SiGe) stressors. More specifically, embodiments of the invention include a method of forming a FinFET with a SiGe stressor and a resulting FinFET structure.
In integrated circuit (IC) structures, a transistor is a critical component used to implement digital circuitry designs. Generally, a transistor includes three electrical terminals: a source, a drain, and a gate. By applying different voltages to the gate terminal, the flow of electric current from the source to the drain can be enabled or disabled. A common type of transistor is a metal oxide field effect transistor (MOSFET). One type of MOSFET design is known as a “FinFET,” typically built upon a semiconductor-on-insulator (SOI) layer and buried insulator layer. A FinFET can be composed of a semiconductor structure etched into a “fin” shaped body, with one side of the fin acting as a source terminal and the other side of the fin acting as a drain terminal. A gate structure, typically composed of polysilicon and/or a metal, can be formed around one or more of the semiconductor fins. By applying a voltage to the gate structure, an electrically conductive channel can be created between the source and drain terminals of each fin in contact with the gate.
To enhance the operation of an IC, mechanical stress may be applied to the transistors of the circuit. For example, the operation of a p-type MOSFET is enhanced if a compressive stress is applied to its channel, while the operation of an n-type MOSFET is enhanced if a tensile stress is applied to its channel. To apply mechanical stress to an IC component composed of single-crystal semiconductor (e.g., the fins of a FinFET), a “stressor” material can be introduced to the component. Silicon germanium (SiGe), a conventional stressor used in MOSFETs and sometimes used in a FinFET, can be introduced, for example, by creating a recess within source and drain regions of the transistor and growing epitaxial silicon germanium (SiGe) therein. This conventional process of introducing a stressor material may be limited by the amount of semiconductor material (e.g., silicon) available in the recessed semiconductor fin. The various crystal growth conditions of SiGe, in some cases, can also create a faceted epitaxy at the bottom of the recess within the fin, which will prevent the application of strain to the semiconductor fin.
According to one embodiment of the present invention, a method of forming a FinFET with a silicon germanium (SiGe) stressor can include: forming a semiconductor fin on a buried insulator layer; forming a gate structure on the semiconductor fin; forming a silicon germanium (SiGe) layer on the buried insulator layer, wherein the SiGe layer contacts the semiconductor fin; and heating the SiGe layer, wherein the heating diffuses germanium (Ge) into the semiconductor fin.
According to another embodiment of the present invention, a FinFET structure can include: a semiconductor fin positioned above a buried insulator layer, wherein the semiconductor fin includes: a semiconductor channel region; a silicon germanium (SiGe) source region positioned adjacent to the semiconductor channel region; and a silicon germanium (SiGe) drain region positioned adjacent to the semiconductor channel region, each stressor having a highest concentration of Ge along an exterior of the semiconductor fin, and a lowest concentration of Ge proximate to the semiconductor channel region.
According to an additional embodiment of the present invention, a method of forming a FinFET structure can include: forming a semiconductor fin on a buried insulator layer, wherein the semiconductor fin includes a source region and a drain region; forming a gate structure on the semiconductor fin; forming a spacer on the gate structure; growing a SiGe layer on the buried insulator layer, wherein the SiGe layer contacts the semiconductor fin; annealing the SiGe layer, wherein the annealing causes germanium (Ge) to diffuse from the SiGe layer into the semiconductor fin at each of the source region and the drain region; and removing the SiGe layer.
It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be used and that changes may be made without departing from the scope of the present teachings. The following description is, therefore, merely illustrative.
Embodiments of the present disclosure include a method of forming a FinFET with a silicon germanium stressor. In addition, a FinFET structure obtainable from embodiments of the disclosed method, is discussed. The method can include, for example, forming a semiconductor fin on a buried insulator layer, and forming a gate structure on the semiconductor fin. A layer of silicon germanium (SiGe) can be formed on the buried insulator layer such that the formed SiGe layer contacts the semiconductor fin. The formed SiGe layer can be heated to a temperature at which germanium (Ge) diffuses into the semiconductor fin to form a SiGe stressor region.
Referring to the drawings,
A semiconductor layer 15 (shown in phantom) can be formed, e.g., by wafer bonding on buried insulator layer 14. “Wafer bonding” generally can refer to a process in which two semiconductor wafers are bonded together, forming a single substrate material. The bonded semiconductor wafers can be cut using any currently known or later developed semiconductor or SOI fabrication process. As one example, a semiconductor material can formed by implanting a bonded wafer with hydrogen and then annealing the wafer, causing it to split along the plane of the implanted hydrogen. Semicondcutor layer 15 can, together with substrate 12 and buried insulator layer 14, form a semiconductor-on-insulator (SOI) structure. Semiconductor layer 15 can be composed of, for example, silicon or another semiconductor material. In some embodiments, semiconductor layer 15 can be composed of SiGe with a relatively small fraction of germanium, e.g., approximately twenty percent. Following the formation of semiconductor layer 15, one or more semiconductor fins 16 can be formed therefrom via any currently known or later developed process of removing a portion of a semiconductor material. As discussed herein, “removing” can include any one of various material removal or polishing techniques now known or later developed, e.g., etching, a reactive ion etch (RIE), etc. RIE″ or “reactive ion etch” refers to a variation of plasma etching in which, during etching, a semiconductor wafer is placed on an RF powered electrode. Throughout RIE, the wafer may take on an electric potential which accelerates the etching species extracted from plasma toward the etched surface. Although three semiconductor fins 16 are shown in
Turning to
A gate dielectric 26 may be formed, e.g., by deposition or any other currently known or later process of forming a dielectric material, between semiconductor fin 16 and gate structure 18. Gate dielectric 26 can be a thin insulator which may be composed of, e.g., thermally grown silicon oxide (sometimes nitrided), or other insulative materials having a higher dielectric constant than silicon oxide. One or more spacers 28 can be formed adjacent to gate structure 18, e.g., by being deposited. Spacers 28 can electrically isolate gate structure 18 from source region 20 and drain region 22 of semiconductor fin 16. Spacers 28 can be composed of, e.g., an insulating material such as a nitride or an oxide compound, including, for example, the various insulators discussed elsewhere herein. Additionally, a nitride cap 30 can be formed, e.g., by deposition, above gate structure 18. The material composition of spacers 28 and/or nitride cap 30 can prevent the diffusion of germanium (Ge) into gate structure 18 during the heating processes used to diffuse Ge into semiconductor fin 16, embodiments of which are described in detail elsewhere herein.
Returning to the previous orientation, a silicon germanium (SiGe) layer 32 can be formed above buried insulator layer 14, as shown in
Turning to
The Ge particles can migrate or diffuse into semiconductor fins 16 by heating SiGe layer 32 to a predetermined temperature. For example, the diffusion of Ge from SiGe layer 32 can be a result of annealing SiGe layer 32. “Annealing” generally refers to a heat treatment process in which a structure, such as substrate 12, is subjected to intense heat, and then gradually cooled, in order to modify the physical properties of some or all of the materials and structures present on its surface. The heating of SiGe layer 32 thus causes Ge atoms to diffuse into semiconductor fins 16, thereby creating SiGe stressor region 36. Though SiGe layer 32 may be in contact with other components, e.g., buried insulator layer 14, Ge atoms will only diffuse into semiconductor fins 16 when subjected to heat. The migration of Ge atoms through the outer surface of semiconductor fins 16 can effectively cause the Ge within stressor region 36 to have a “gradient” structure. For example, the highest concentration of Ge within stressor region 36 can be along the exterior of semiconductor fin 16. Conversely, the lowest concentration of Ge can be proximate to gate structure 18, where stressor region 36 is most isolated from SiGe layer 32. To prevent the potential diffusion of Ge atoms into gate structure 18 (
As shown in
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
This written description uses examples to disclose the invention, including the best mode, and to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.
