A flash memory semiconductor device is a non-volatile storage device that can be electrically erased and reprogrammed. Flash memories are commonly used in memory cards, USB flash drives, and solid state drives for general storage and transfer of data between computers and other digital products. Flash memories typically store information in an array of memory cells made using floating gate transistors.
A floating gate transistor is a field effect transistor having a structure similar to a MOSFET (metal oxide semiconductor field effect transistor). Floating gate MOSFETs are distinguished from other MOSFETs because the floating gate transistor includes two gates instead of one. In addition to an upper control gate, a floating gate transistor includes an additional floating gate between the control gate and above the transistor channel, but completely electrically isolated by an insulating layer such as an oxide that completely surrounds the floating gate. This electrically isolated floating gate creates a floating node in DC (direct current) with a number of inputs for secondary gates such as the control gate, formed above the floating gate and electrically isolated from it. Because the floating gate is completely surrounded by highly resistive material, i.e. an insulating layer, any charge placed on the floating gate is trapped there and the floating gate remains unchanged for long periods of time until the floating gate MOSFET is erased. These devices, however, are regularly be erased.
To erase such a flash cell, a large voltage of the opposite polarity is applied between the control gate and the source, causing electrons to exit the floating gate through quantum tunneling. In this manner, the electrical charge is removed from the floating gate. It is therefore desirable to produce floating gate transistors which are easily erased, i.e. floating gate transistors in which the electrical charge is easily removed from the floating gate.
Embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawing.
It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Like numerals denote like features throughout the specification and drawing.
Each of the sets of figures includes an “A” figure illustrating a plan view, for example
Embodiments of the disclosure provide a method for forming a flash memory device. More particularly, various embodiments of the disclosure provide for forming split gate transistors which are formed in an array according to some embodiments. The method avoids the use of LOCOS (Local Oxidation of Silicon), which is a thermal oxidation process that is inherently difficult to control and which produces unreliable tips of the floating gate structures and has been known to cause loss and breakage of the underlying floating gates. The poor tip profile includes tips that are rounded and this causes failures in endurance of the device and in erase operations because sharp tips are required for a concentrated electric field to perform the erase operations. The method provided by the present disclosure avoids the use of LOCOS, as above, and uses a re-deposition of a polysilicon or other semiconductor film to form transistor floating gates with superior and reliably controlled tips. The floating gate has a well-controlled, sharp tip profile for superior electrical functionality. The sharp tip profile enables the floating gate transistor to be easily erased as it allows for high electric field and enables Fowler-Nordheim tunneling thereby avoiding errors in the erase operations. The superior electrical functionality provided by the sharp tip profile enables better control of floating gate-to-control gate capacitance and tunneling distance, and more degrees of freedom for the coupling ratio tuning and scaling.
The method used in embodiments of the disclosure provides for a process flow with a reduced amount of furnace processing operations. In various embodiments the process flow avoids the use of LOCOS and other furnace formed films, which reduces manufacturing time and cost.
First semiconductor layer 7 is formed of polysilicon in some embodiments, and the polysilicon may be doped or undoped. In other embodiments, first semiconductor layer 7 may be formed of silicon germanium, amorphous silicon or other suitable semiconductor materials. First semiconductor layer 7 includes a thickness 13 that may be about 1000 angstroms in some embodiments, and may range from about 500-1500 angstroms in other embodiments, although other thicknesses are used in other embodiments and the thickness may eventually be receded as will be shown later. First semiconductor layer 7 is formed using various deposition processes such as chemical vapor deposition, CVD, or other suitable film formation processes. Trenches 3 extend downwardly from surface 5 of first semiconductor layer 7, through first semiconductor layer 7 and through floating gate dielectric 9 and into substrate 11. Trenches 3 extend into substrate 11 by a depth 15 that may range from about 2000 A to about 6000 A in various embodiments. Trenches 3 may be formed by a patterning operation followed by an etching operation that etches through first semiconductor layer 7, floating gate dielectric 9 and into substrate 11 to form trenches 3 shown in cross-section in
A patterning and etching operation sequence is then carried out to convert the structure shown in
Discrete portions 45 of further semiconductor layer 33 overhang the associated adjacent STI structures 25. Discrete portions 45 of further semiconductor layer 33 combine with segment 29 of polished first semiconductor layer 19 to form T-shaped floating gate segment 49. Along one lateral direction such as shown in
In the lateral direction orthogonal to the view shown in
A dielectric is formed over the structures shown in
Control gate 65 is formed of polysilicon in some embodiments, but may be formed of other materials in other embodiments, and includes thickness 79 of about 1,500-2,500 angstroms, and thickness 79 may be about 2,000 angstroms in various embodiments, but other thicknesses are used in other embodiments. It can be seen that T-shaped floating gate segment 49 serves as the floating gate of the split gate floating gate transistor. In the direction orthogonal to the channel direction, i.e. the direction shown in
Overhang edges 51 provide a sharp tip that is well controlled and provides the aforementioned advantages.
It should be noted that the dimensions provided above are intended to serve as examples and are not limiting of the features and dimensions of the disclosure. Dimensions such as thicknesses are chosen in conjunction with the desired operational characteristics of the floating gate transistors and the dimensions of a particular feature are typically chosen in conjunction with the dimensions of associated features and design rules to provide high functioning floating gate transistor devices.
Although the cross-sectional views of the foregoing sequence of processing operations were shown with respect to a single transistor device to show additional detail and for clarity, it should be understood that the cross-sectional views represent only a portion of the plan view shown in the “A” figures. Although the processing sequence was described and illustrated in conjunction with a single transistor device, the processing sequence of the disclosure is used to simultaneously form a plurality of floating gate transistor devices in various arrays and other arrangements.
In some embodiments, a method for forming floating gate transistors is provided. The method comprises: forming trench openings in a substructure that includes a semiconductor layer over a floating gate oxide over a semiconductor substrate; filling the trench openings with a dielectric to form STI (shallow trench isolation) structures; planarizing to produce a coplanar upper surface that includes portions of upper surfaces of the STI structures and portions of a top surface of the semiconductor layer; depositing a further semiconductor layer over the coplanar upper surface; and patterning and etching the further semiconductor layer to produce discrete semiconductor portions of the further semiconductor layer, the discrete semiconductor portions having edges that overhang adjacent STI edges of the STI structures.
According to other aspects, an array of floating gate transistor is provided. Each floating gate transistor has a channel and a floating gate disposed over the channel, the floating gate having opposed lateral edges at opposed ends of the floating gate and, in a direction orthogonal to a channel direction. The floating gate includes opposed overhang edges, each including a vertical edge portion that forms a boundary with an associated adjacent STI (shallow trench isolation) structure and an overhang portion that extends outwardly past the vertical edge portion and overhangs the associated adjacent STI structure.
According to other aspects, a method for forming an array of floating gate transistors, is provided. The method comprises: forming trench openings in a substructure that includes a polysilicon layer over a floating gate dielectric over a substrate, the polysilicon layer having a first thickness; filling the trench openings with a dielectric to form STI (shallow trench isolation) structures; polishing to produce a coplanar upper surface that includes portions of upper surfaces of the STI structures and a receded top surface of the polysilicon layer, the polished polysilicon layer having a thickness less than the first thickness; and depositing a further polysilicon layer over the coplanar upper surface. The method also comprises patterning and etching the further polysilicon layer to produce polysilicon segments formed of the first and further polysilicon layers, the polysilicon segments having edges with portions that overhang adjacent STI edges of the STI structures; and forming a split-gate floating gate transistor using the polysilicon segments as associated floating gates.
The preceding merely illustrates the principles of the disclosure. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope. Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes and to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
This description of the exemplary embodiments is intended to be read in connection with the figures of the accompanying drawing, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
Although the disclosure has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended examples should be construed broadly, to include other variants and embodiments of the disclosure, which may be made by those skilled in the art without departing from the scope and range of equivalents of the disclosure.
This application is a regular application based on and claiming priority of U.S. provisional application Ser. No. 62/095,665, entitled “Floating Gate Transistors and Method for Forming the Same,” filed Dec. 22, 2014, the contents of which are hereby incorporated by reference as if set forth in their entirety.
Number | Date | Country | |
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62095665 | Dec 2014 | US |