Embodiments of the present disclosure relate generally to semiconductor packaging, and more particularly to frame cassettes with internal cover cases used for semiconductor packaging.
The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, improvement in integration density has resulted from iterative reduction of minimum feature size, which allows more components to be integrated into a given area.
While some integrated device manufacturers (IDMs) design and manufacture integrated circuits (IC) themselves, fabless semiconductor companies outsource semiconductor fabrication to semiconductor fabrication plants or foundries. Semiconductor fabrication consists of a series of processes in which a device structure is manufactured by applying a series of layers onto a substrate. This involves the deposition and removal of various dielectric, semiconductor, and metal layers. The areas of the layer that are to be deposited or removed are controlled through photolithography. Each deposition and removal process is generally followed by cleaning as well as inspection steps. Therefore, both IDMs and foundries rely on numerous semiconductor equipment and semiconductor fabrication materials, often provided by vendors. There is always a need for customizing or improving those semiconductor equipment and semiconductor fabrication materials, which results in more flexibility, reliability, and cost-effectiveness.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
In addition, source/drain region(s) may refer to a source or a drain, individually or collectively dependent upon the context. For example, a device may include a first source/drain region and a second source/drain region, among other components. The first source/drain region may be a source region, whereas the second source/drain region may be a drain region, or vice versa. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Some of the features described below can be replaced or eliminated and additional features can be added for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.
Overview
Packaging technologies were once considered just back-end processes. Times have changed. Computing workloads have evolved more over the past decade than perhaps the previous four decades. Cloud computing, big data analytics, artificial intelligence (AI), neural network training, AI inferencing, mobile computing on advanced smartphones, and even self-driving cars are all pushing the computing envelope. Modern workloads have brought packaging technologies to the forefront of innovation, and they are critical to a product's performance, function, and cost. These modern workloads have pushed the product design to embrace a more holistic approach for optimization at the system level.
Chip-on-Wafer-on-Substrate (CoWoS) is a wafer-level multi-chip packaging technology often used in conjunction with hybrid bonding. CoWoS is a packaging technology that incorporates multiple chips side-by-side on a silicon interposer in order to achieve better interconnect density and performance. Individual chips are bonded through, for example, micro-bumps on a silicon interposer, forming a chip-on-wafer (CoW) structure. The CoW structure is then subsequently thinner such that through-silicon-vias (TSVs) are exposed, which is followed by the formation of bumps (e.g., C4 bumps) and singulation. The CoW structure is then bonded to a package substrate forming the CoWoS structure. Since multiple chips or dies are generally incorporated in a side-by-side manner, the CoWoS is considered a 2.5-dimensional (2.5D) wafer-level packaging technology.
Integrated Fan-Out (InFO) is another wafer-level packaging technology. InFO is a packaging technology that incorporates high-density redistribution layers (RDLs) and through InFO via (TIVs) for high-density interconnect and performance for various applications, such as mobile devices, high performance computing, etc. A wafer is typically diced into individual known good dies (KGDs) after testing, and the KGDs are placed on a temporary carrier with a certain distance apart. RDLs are formed subsequently to enable higher number of external contacts without increasing the size of KGDs.
On the other hand, those multiple chips that are bonded to the interposer in a CoWoS structure or embedded in an InFO structure can each include stacking dies or chiplets (i.e., modular dies), with multi-layers, multi-chip sizes, and multi-functions. In one implementation, the stacking dies are bonded together using hybrid bonding (HB). Hybrid bonding is a process that stacks and bonds dies using both dielectric bonding layers and metal-to-metal interconnects in advanced packaging. Since no bumps like micro-bumps are used, hybrid bonding is regarded as a bumpless bonding technique. Hybrid bonding can provide improved integration density, faster speeds, and higher bandwidth. In addition to die-to-die bonding, hybrid bonding can also be used for wafer-to-wafer bonding and die-to-wafer bonding.
Stacking dies featuring ultra-high-density-vertical stacking (often using hybrid bonding) is sometimes referred to as System on Integrated Chips (SoIC) technologies. SoIC technologies can achieve high performance, low power, and minimum resistance-inductance-capacitance (RLC). SoIC technologies integrate active and passive chips that are partitioned from System on Chip (SoC), into a new integrated SoC system, which is electrically identical to native SoC, to achieve better form factor and performance. A die stack bonded together using hybrid bonding is sometimes, therefore, referred to as a SoIC die stack (“SoIC die stack” and “die stack” are used interchangeably throughout the disclosure).
The dielectric-to-dielectric interface in either hybrid bonding or fusion bonding requires water (H2O) as the bonding medium. Because of the presence of water as the bonding medium, silanol groups (i.e., Si—OH) exist at the surface of the silicon-containing dielectric (e.g., silicon dioxide, silicon oxynitride, etc.) layers at the dielectric-to-dielectric interface. In a polymerization process, the silanol groups (i.e., Si—OH) at both sides of the dielectric-to-dielectric interface polymerize to siloxane groups (i.e., Si—O—Si) and water (i.e., H2O) in accordance with Si—OH+Si—OH→Si—O—Si+H2O. As such, the top die and the bottom die are bonded together. In addition to serving as the bonding medium, water is also used to wash the wafters or chips (or dies) to be bonded to eliminate unwanted particles at the bonding surfaces.
Top dies are typically disposed on a frame before the bonding process using a pick-and-place tool. Multiple frames are accommodated in a frame container (e.g., a frame cassette) during the transportation thereof. Conventionally, multiple frames are placed in a frame cassette, one above another in the vertical direction. Particles originated from one frame may drop on the top surface of dies disposed on another frame below the frame. Particles originated from the frame cassette may also drop on the top surface of dies. In addition, volatile organic compounds (VOCs), originated from frames or the frame cassette itself, exist in the space inside the frame cassette. Moreover, particles may also be introduced by the airflow inside the frame cassette. Particles, volatile organic compounds, and airflow particles all contribute to the contamination of the top surfaces of the dies, resulting in bonding interfaces with voids, delamination, non-bonding, and the like.
In accordance with some aspects of the disclosure, a frame cassette used for semiconductor processing is provided. The frame cassette includes a housing and multiple cover cases disposed in the housing. Each of the cover cases is capable of accommodating a frame. In one embodiment, each cover case includes a bottom section, a top section parallel to the bottom section, and at least one sidewall extending, in a vertical direction, between and connecting the bottom section and the top section to form an enclosed space.
The cover cases prevent corresponding frames from being contaminated by, for example, the particles originated from other frames, the particles originated from the frame cassette, the particles originated from the airflow, and volatile organic compounds. Details of various aspects of the disclosure will be described below in detail with reference to
In the example shown in
In the example shown in
Each of the four cover cases 110a, 110b, 110c, and 110d is capable of accommodating or configured to accommodate a frame. In the example shown in
The frames 112a, 112b, 112c, and 112d (collectively, “112”) are placed in the cover cases 110a, 110b, 110c, and 110d, respectively, after being cleaned. The cover cases 110a, 110b, 110c, and 110d prevent the frames 112a, 112b, 112c, and 112d, respectively, from being contaminated by the particles originated from other frames, the particles originated from the frame cassette 100, the particle originated from the airflow, and volatile organic compounds.
In the example shown in
The frame bases 208a, 208b, and 208c are configured to support the frame 112a when the frame 112a is placed in the cover case 110a. In the example shown in
Due to the presence of the frame bases 208a, 208b, and 208c, the frame 112a is not in direct contact with the bottom section 206, thereby reducing, for example, contamination or scratches at the backside of the frame 112a. As shown in
As shown in
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It should be understood that the example shown in
In some embodiments, the cover case 110 is made of (i.e., the bottom section 206, the top section 204, and the sidewalls 202 are made of) an electrostatic discharge (ESD) material, which reduces static electricity to prevent particles from being attracted to the cover case 110. In one example, the cover case 110 is made of a metal. In another example, the cover case 110 is made of a plastic material such as polycarbonate (PC), polyetherimide (PEI), Entegris Barrier material (EBM), and the like. In yet another example, the cover case 110 is made of rubber. In another example, the cover case 110 is made of two or more of the materials mentioned above. It should be understood that these examples are not intended to be limiting, and other suitable materials may be employed in other embodiments as needed.
As mentioned above, volatile organic compounds (VOCs), originated from frames or the frame cassette itself, exist in the inner space 152 inside the frame cassette 100, as shown in
In the example shown in
In the example shown in
In the example shown in
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In some embodiments, the filter 1102 is a pleated filter which has folds or pleats, thereby increasing the surface area for better filtering. In other embodiments, the filter 1102 is a non-pleated or flat filter which provides maximum airflow and is suitable for relatively high airflow pressure. The filter 1102 can be made of paper, foam, carbon, aluminum, steel, fiberglass, plastic, or any other suitable materials.
In one embodiment, the cover case 110a includes two vent holes 602 (one as the inlet and the other as the outlet), and at least the vent hole 602 that serves as the inlet includes the filter 1102. It should be understood that this embodiment is not intended to be limiting.
The cover case 110a shown in
The humidity sensor 1202 is configured to measure the humidity of the air inside the cover case 110a. In one embodiment, the humidity is sent to a control system, which controls the humidity adjustment unit 1204 based on the measured humidity. In some implementations, the humidity can be read from outside the cover case 110a and the frame cassette 100 using, for example, wireless communication, optical detection, visual inspection, and the like.
In some embodiments, the humidity sensor 1202 is based on materials that can change chemically depending on the humidity, such as cobalt chloride film or test paper, the color of which changes accordingly as the humidity changes. In other embodiments, the humidity sensor 1202 is based on materials that can change physically (i.e., certain physical properties of the material change) depending on the humidity. In one example, the material is colored alcohol, and the volume of the colored alcohol changes accordingly as the humidity changes. In some other embodiments, the humidity sensor 1202 is based on materials that can change electrically (i.e., electrical signals associated with the material changes) depending on the humidity. In one example, the material is aluminum oxide film that can absorb water from the environment, and the capacitance or resistance of the aluminum oxide film changes accordingly as the humidity changes. While these embodiments and examples are discussed above, it should be understood that other types of humidity sensors (e.g., optical hygrometers) or other types of materials (e.g., polymers) can be employed in other embodiments.
The humidity adjustment unit 1204 is configured to adjust the humidity of the air inside the cover case 110a. In one embodiment, the humidity adjustment unit 1204 includes a humidifier to increase the humidity of the air inside the cover case 110a. In another embodiment, the humidity adjustment unit 1204 includes a dehumidifier to decrease the humidity of the air inside the cover case 110a. In yet another embodiment, the humidity adjustment unit 1204 includes both a humidifier to increase the humidity of the air inside the cover case 110a and a dehumidifier to decrease the humidity of the air inside the cover case 110a.
In the example shown in
The outlet 1308, which is below the minimum level, is in liquid communication with the nozzle 1310 through, for example, a conduit. When the controller sends a control signal to the humidifier 1302, water 1305 can be sprayed by the nozzle 1310 to increase the humidity of the air inside the cover case 110a. In one implementation, a switch (e.g., a solenoid) and a pump are controlled by the control signal to spray the water 1305 out of the nozzle 1310. In one embodiment, the opening area of the outlet 1308 is larger than 0.1 mm2.
The spill-prevention member 1312 is disposed on the top of the water tank 1304. The spill-prevention member 1312 can prevent the water 1305 from spilling, especially during the transportation of the cover case 110a and the frame cassette 100. In one implementation, the spill-prevention member 1312 is a sponge fixed to the water tank 1304.
It should be understood that more than one outlet 1308 and more than one nozzle 1310 can be employed in other embodiments. It should be understood that the humidifier 1302 may include additional components, such as heaters, piezoelectric vibrators, and the like, to allow for better delivery of the water 1305 in the water tank 1304.
In one embodiment, the relative humidity (RH) is between 0 and 100%. In another embodiment, the relative humidity is between 20% and 60%. In yet another embodiment, the relative humidity is about 40%.
At operation 1402, the humidity of the air inside the cover case 110a is measured. In one implementation, the humidity is measured by a humidity sensor (e.g., the humidity sensor 1202 shown in
At operation 1404, the humidity of the air inside the cover case 110a is adjusted based on the measured humidity. In one implementation, the humidity is adjusted by a humidity adjustment unit (e.g., the humidity adjustment unit 1204 shown in
For die-to-wafer bonding and die-to-die bonding, which involve stacking a die on a wafer, a die on an interposer, or a die on a die, the infrastructure to handle dies without particle adders, as well as the ability to bond dies, becomes a major challenge. Typically, back-end processes, such as dicing, die handling, and die transport on film frame, have to be adapted to front-end clean levels, allowing high bonding yields on a die level. For example, copper hybrid bonding is conducted in a cleanroom in a wafer fab, instead of in an outsourced semiconductor assembly and test (OSAT) facility.
Pick-and-place tools (sometimes also referred to as “pick-and-place systems”) are part of the infrastructure to handle dies in the context of die-to-wafer bonding and die-to-die bonding. A pick-and-place system is an automatic system that can pick a die (often referred to as a “top die”) and place it onto another die (often referred to as a “bottom die”) or a host wafer, often in a high-speed manner. A person may take the complexity and difficulty of such tasks of picking and placing a top die for granted. On the contrary, accurate alignment of dies, without comprising the high system throughput, is very challenging, especially considering that the alignment accuracies are on the order of microns (i.e., micrometers). If the position shift error cannot be further reduced, the critical size of hybrid bonding metal pads cannot be reduced, which in turn limits bonding density.
At operation 1502, a first frame (e.g., the frame 112a shown in
At operation 1504, a first wafer placed in a wafer container is transferred to the pick-and-place tool. Multiple bottom dies are disposed on the first wafer and correspond to the multiple top dies, respectively. In one implementation, the first wafer is handled by, for example, a transfer robot.
At operation 1506, top dies on the first frame are bonded to the corresponding bottom dies on the first wafer. In one embodiment, the top dies are bonded to the corresponding bottom dies using the pick-and-place tool.
It should be understood that the example method 1500 may include other operations. In one example, the first frame is wetted, using water, prior to transferring the first frame to the pick-and-place tool, and the first wafer is wetted, using water, prior to transferring the first wafer to the pick-and-place tool. In another example, the humidity inside the cover case is adjusted (e.g., using the method 1400 shown in
In accordance with some aspects of the disclosure, a frame cassette used for semiconductor processing is provided. The frame cassette includes: a housing; and a plurality of cover cases disposed in the housing. Each of the plurality of cover cases is capable of accommodating a frame and includes: a bottom section; a top section parallel to the bottom section; and at least one sidewall extending, in a vertical direction, between and connecting the bottom section and the top section to form an enclosed space.
In accordance with some aspects of the disclosure, a cover case used for semiconductor processing is used. The cover case includes: a bottom section; a top section parallel to the bottom section; and at least one sidewall extending, in a vertical direction, between and connecting the bottom section and the top section to form an enclosed space. The enclosed space is operable to accommodate a frame, and a plurality of top dies are disposed on the frame.
In accordance with some aspects of the disclosure, a method of semiconductor processing is provided. The method includes the following steps: transferring a first frame placed in a cover case disposed in a frame cassette to a pick-and-place tool, a plurality of top dies being disposed on the first frame, wherein the cover case is characterized by an enclosed space operable to accommodate the first frame; transferring a first wafer placed in a wafer container to the pick-and-place tool, a plurality of bottom dies being disposed on the first wafer and corresponding to the plurality of top dies, respectively; and bonding, by the pick-and-place tool, the plurality of top dies to the plurality of bottom dies, respectively.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Number | Date | Country | |
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63375538 | Sep 2022 | US |