Patent Application
20070202360
The invention relates generally to gallium nitride material devices and, more particularly, to gallium nitride material transistors and methods associated with the same.
Gallium nitride materials include gallium nitride (GaN) and its alloys such as aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN). These materials are semiconductor compounds that have a relatively wide, direct bandgap which permits highly energetic electronic transitions to occur. Gallium nitride materials have a number of attractive properties including high electron mobility, the ability to efficiently emit blue light, and the ability to transmit signals at high frequency, amongst others. Accordingly, gallium nitride materials are being investigated in many microelectronic applications such as transistors and optoelectronic devices.
Despite the attractive properties noted above, a number of challenges exist in connection with developing gallium nitride material-based devices. For example, it may be difficult to grow high quality gallium nitride materials on certain substrates, particularly silicon, due to property differences (e.g., lattice constant and thermal expansion coefficient) between the gallium nitride material and the substrate material. Also, it is has been challenging to form gallium nitride material devices meeting the property requirements for certain applications.
Applications for RF power transistors may have particularly demanding property requirements. For example, RF power transistors used in wireless communications (e.g., in wireless basestation applications) may need to meet property requirements related to output power, linearity, gain and efficiency.
Gallium nitride material transistors and methods associated with the same are provided.
In one aspect, a device adapted to receive an input signal and to transmit an output signal is provided. The device comprises at least one transistor structure to receive the input signal. The at least one transistor includes at least one active region formed in a gallium nitride material region. The at least one transistor structure is adapted to amplify the input signal to form the output signal. The output signal, when transmitted, has an RCE of less than or equal to −10 dB.
In another aspect, a device for generating a radio frequency (RF) output signal from an RF input signal is provided. The device comprises at least one transistor having at least one active region formed in a gallium nitride material layer. The at least one transistor arranged to receive the RF input signal and, when present, amplify the RF input signal to provide the RF output signal. The device includes at least one matching circuit adapted to transform at least one impedance of the device such that, when the device is loaded with a load, the RF output signal is capable of being transmitted with an RCE of less than or equal to −10 dB.
In another aspect, a method of generating an output signal for wireless transmission is provided. The method comprises receiving an input signal comprising information to be transmitted. The method further comprises amplifying the input signal via at least one transistor structure having at least one active region formed in a gallium nitride material region to provide the output signal. The method further comprises transmitting the output signal such that the output signal has an RCE of less than or equal to −10 dB.
Other aspects, embodiments and features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings. The accompanying figures are schematic and are not intended to be drawn to scale. In the figures, each identical, or substantially similar component that is illustrated in various figures is represented by a single numeral or notation. For purposes of clarity, not every component is labeled in every figure. Nor is every component of each embodiment of the invention shown where illustration is not necessary to allow those of ordinary skill in the art to understand the invention. All patent applications and patents incorporated herein by reference are incorporated by reference in their entirety. In case of conflict, the present specification, including definitions, will control.
The invention provides gallium nitride material transistors and methods associated with the same. The transistors may be used in power applications by amplifying an input signal to produce an output signal having increased power. The transistors may be designed to transmit the majority of the output signal within a specific transmission channel (defined in terms of frequency), while minimizing transmission in adjacent channels. This ability gives the transistors excellent linearity which results in high signal quality and limits errors in transmitted data. As described further below, the transistors may be designed to achieve low RCE (relative constellation error) values and low EVM (error vector magnitude) values (both measures of excellent linearity), while still operating at high drain efficiencies and/or high output powers. The transistors may also operate in compliance with spectrum mask requirements (e.g., requirements in ETSI EN 301 021 V1.6.1 (2003-02)). Such properties enable the transistors to be used in RF power applications including wideband power applications (e.g., WiMAX, WiBRO, and others) based on OFDM modulation.
When a structure (e.g., layer, region) is referred to as being “on”, “over” or “overlying” another structure, it can be directly on the structure, or an intervening structure (e.g., layer, region) also may be present. A structure that is “directly on” or “in contact with” another structure means that no intervening structure is present. It should also be understood that when a structure is referred to as being “on”, “over”, “overlying”, or “in contact with” another structure, it may cover the entire structure or a portion of the structure.
It should be understood that the transistor structure shown in
It should be understood that, in other embodiments of the invention, the transistor unit cell may include a different number of building block structures and/or have different types of electrode and pad connections.
In some embodiments, power transistor 40 is attached to a package to form a final packaged device. As described further below, other components (e.g., matching network components) may also be attached to the package. Bond wires may be used to make electrically connections between the components, the power transistor and the package (as needed). A single power transistor may be attached to a single package. However, it should also be understood that multiple power transistors may be attached to a single package.
The package may comprise suitable package material known in the art. In some embodiments, the package material is formed of a metal and/or a metal alloy. For example, the package may be formed of a copper/tungsten alloy coated with gold. In some cases, the package may comprise, at least in part, a ceramic material.
In some embodiments, transistors 40 may not be attached to a package. Instead, the transistors may be attached directly to a board, or to a heat sink. When attached to a board, other components may also be attached to the same board.
Transistors of the invention may operate in common source configuration. In this configuration, the source pads (and source electrodes) are connected to ground, the input signal from a source is received by the gate pads (and gate electrodes), and the output signal is transmitted from the drain pads (and drain electrodes) to a load driven by the transistor. However, it is possible, for the transistors to operate in other configurations.
The transistors typically are connected to an impedance matching network which transforms impedance, amongst other functions. The impedance matching network may include an input matching network (e.g., formed between the input signal source and the gate pads) and an output matching network (e.g., formed between the drain pads and the load). The input matching network is designed to transform the input impedance of the transistor to a desired impedance (e.g., to a larger impedance to ease any subsequent external matching). The output matching network is designed to transform the output impedance of the transistor to a desired impedance (e.g., to a larger impedance to ease any subsequent external matching). For example, the transformed input and output impedance may be between 1 ohms and 50 ohms. Transistors of the present invention may advantageously have a high impedance for a given RF output power value which may enable use of matching networks having simple designs.
The matching network can comprise any component or feature capable of transforming impedance. Such components include devices (e.g., capacitors, inductors, resistors) that transform impedance by a known amount. Thus, the devices may be connected to form a network that transforms the impedance as desired.
Suitable capacitors that may be used in the matching network include conventional capacitor components. Suitable inductors include the bond wires. A number of variables associated with the bond wires (e.g., number, composition, dimensions, proximity to adjacent wires) may be selected to achieve the desired effect.
The components may be mounted to the same entity as the transistor(s) (e.g., package, heat sink or board). In some cases, the components may be separate from the mounted transistors. It may also be possible to form certain components (e.g., capacitors) directly on the same semiconductor substrate as the transistor.
It should be understood that the matching network may include other components or features that transform impedance. For example, dimensions of certain transistor features (e.g., source and gate contact pads) may transform impedance and, thus, may be considered part of the matching network. In some embodiments, the bond wires may be connected to the package, itself, which can make the package part of the matching network. The matching network may also include other components not described herein that transform impedance.
As noted above, the matching network is designed to transform impedance to a desired value. The matching network also may be designed to help achieve desired device performance. For example, the matching network may be designed to effect linearity (e.g., RCE values), efficiency, gain and output power (or power density). In general, the matching network can be designed by arranging the components and features in a manner that achieves the desired result. Typically, device simulation tools and experimentation can be used to test and optimize the design.
A variety of matching network designs may be suitable. One suitable matching network is shown in the embodiment of
The output matching network includes an arrangement of components positioned between each respective drain pad and a package output lead (flange). The arrangement includes an inductor 4 which is a bond wire group connecting the transistor and the output lead.
In some embodiments, inductors 1-4 have an inductance between 50 picoHenry and 1000 picoHenry; and, in some embodiments, between 75 picoHenry and 350 picoHenry. For example, in one suitable matching network, inductor 1 is 103 picoHenry; inductor 2 is 150 picoHenry, inductor 3 is 300 picoHenry and inductor 4 is 290 picoHenry.
In some embodiments, capacitor 1-2 have a capacitance between about 5 picoFarad and 100 picoFarad. In some embodiments, capacitor 3 has a capacitance between about 50 picoFarad and 1000 picoFarad; and, in some embodiments, between 50 picoFarad and 500 picoFarad. For example, in one suitable matching network, capacitor 1 is 30 picoFarad, capacitor 2 is 25 picoFarad and capacitor 3 is 125 picoFarad.
The matching network shown in
As noted above, transistors of the invention can exhibit attractive electrical properties including excellent linearity, high efficiencies, high output power and high gain.
As known to those of skill in the art, linearity can be characterized by RCE (relative constellation error) measurements. In particular, RCE measurements may be used to characterize the linearity of transistors that are used in wideband applications (e.g., WiMAX, WiBro). In general, RCE is a measure of the modulation accuracy of a transmitter. It is determined as the RMS average of the magnitude error of each point in the constellation measured across multiple symbols, frames and packets.
RCE is typically reported in decibels (dB). Transistors of the invention may exhibit an RCE of less than or equal to about −10 dB. In some cases, the RCE may be less than or equal to −13 dB; in some cases, the RCE is less than or equal to −16 dB; in some cases, less than or equal to −18.5 dB; in some cases, less than or equal to −21.5 dB; in some cases, less than or equal to −25 dB; in some cases, less than or equal to −28.5 dB; and, in some cases, less than or equal to −31 dB. Other RCE values are also achievable.
The desired RCE value may depend on the “burst type”. Transistors of the invention may have RCE values less than or equal to value noted in the table for a given burst type. Such transistors comply with requirements defined in the IEEE 802.16-2004 standard which is incorporated herein by reference. In order to achieve high data transmission rates while maintaining lowest levels of transmission error rates, user data
streams are sliced in time, randomized or modulated and transmitted as “bursts” of energy.
WiMAX standard allows for each burst to be modulated in a variety of different types, namely, BPSK, QPSK, 16-QAM, or 64-QAM depending on the data transmission capacity needed. In general, BPSK is the least efficient way to transmit requiring lowest bandwidths while 64-QAM is the most efficient way requiring the most bandwidth.
The transistor may be designed to have a certain RCE value based on its application. RCE values may be controlled, in part, by the matching network, operating conditions and other design features (e.g., layer composition, gate length, gate pitch, amongst others). In some cases, an RCE of greater than −45 dB may be desired to limit sacrifices to other properties. Although, advantageously, transistors of the invention may exhibit a sufficiently low RCE for many RF power transistor applications, while also exhibiting sufficiently high efficiencies and output power, as described further below.
In some cases, the RCE varies by less than 10% over a range of 5 dB of output power. In some cases the RCE varies by less than 10% over a range of 5% efficiency. In some cases, the RCE varies by less than 10% over a range of 10% efficiency.
As known to those of skill in the art, linearity can be characterized by EVM measurements. In particular, EVM (error vector magnitude) measurements may be used to characterize the linearity of transistors that are used in wideband applications (e.g., WiMAX, WiBro). EVM is typically expressed in a percentage. For example, the EVM may be less than or equal to 5%; in some embodiments, less than or equal to 4%; in some embodiments, less than or equal to 2%; and, in some embodiments, less than or equal to 1%; or even less than or equal to 0.5%. In some cases, an EVM of greater than −0.1% may be desired to limit sacrifices to other properties. Although, advantageously, transistors of the invention may exhibit a sufficiently low EVM for many RF power transistor applications, while also exhibiting sufficiently high efficiencies and output power, as described further below.
Transistors of the invention may also be in compliance with spectrum mask requirements including the requirements in ETSI EN 301 021 V1.6.1 (2003-02) which is incorporated herein by reference. For example, transistors of the invention may be in compliance with the spectrum mass requirements shown in
Transistors of the invention may also be in compliance with the requirements in Federal Communications Commission document (FCC 04-258, Released Oct. 29, 2004) which is incorporated herein by reference, Those requirements include the following: the maximum out-of-band power of a digital transmitter operating on a single 6 MHz channel with an EIRP in excess of −9 dBW employing digital modulation for the primary purpose of transmitting video programming is attenuated at the 6 MHz channel edges at least 25 dB relative to the licensed average 6 MHz channel power level, then attenuated along a linear slope to at least 40 dB at 250 kHz beyond the nearest channel edge, then attenuated along a linear slope from that level to at least 60 dB at 3 MHz above the upper and below the lower licensed channel edges, and attenuated at least 60 dB at all other frequencies; and, for mobile digital stations, the attenuation factor is not less than 43+10 log (P) dB at the channel edge and 55+10 log (P) dB at 5.5 MHz from the channel edges.
In some embodiments, the maximum out-of-band integrated power is measured at 1 MHz and 3 MHz from the edge of the band (6.5 MHz and 8.5 MHz offset from the center of the channel). The channel power is measured in a 10 MHz BW, while the adjacent channel powers are measured in 1 MHz BW.
Efficiency (i.e., drain efficiency) is defined as the output power divided by the drain current multiplied by the drain voltage. Transistors of the invention may operate at efficiencies of greater than or equal to 20% (e.g., between 22% and 30%). In some embodiments, the transistors operate at efficiencies of greater than or equal to 30%; and, in some embodiments, the transistors operate at efficiencies of greater than or equal to 40%. High efficiencies may contribute to sacrificing other properties such as RCE and output power and, thus, in some cases, efficiencies of less than 45% may be desired. The efficiency may be controlled, in part, by the matching network, operating conditions and other design features (e.g., layer composition, gate length, gate pitch, amongst others).
Transistors of the invention may operate at these efficiencies with the above-noted RCE and EVM values. For example, the transistors may operate at an RCE of less than or equal to −10 dB and an efficiency of greater than or equal to 20% (e.g., between 20% and 45% or between 20% and 40%); or greater than or equal to 30%. In some cases, the transistors may operate at an RCE of less than or equal to −18.5 dB at a device efficiency of greater than or equal to 20%. It should be understood that transistors of the invention may have other combinations of efficiency and RCE values including any combinations of the values noted above.
Output power may be measured using standard techniques. It may be useful to express output power in terms of power density which is the output power divided by the gate periphery (W/mm). The output power depends largely on the size of the transistor. In some cases, the average output power is between about 0.5 W and about 40 W under OFDM modulation.
Transistors of the invention may have power densities of greater than or equal to 0.1 W/mm. In some embodiments, the power density may be greater than or equal to 0.5 W/mm; and, in some embodiments, the power density may be greater than or equal to 1.0 W/mm. In some cases, power densities of less than or equal to 10 W/mm may be desired to limit sacrifices to other properties such as RCE values and efficiency. The power density may be controlled, in part, by the matching network, operating conditions and other design features (e.g., layer composition, gate length, gate pitch, amongst others).
Transistors of the invention may operate at these power densities with the above-noted RCE and EVM values (and efficiency values).
Transistors of the invention may also operate at sufficient gains for RF power transistors markets (including wideband applications). Gain is defined as the output power divided by the input power and may be expressed in units of dB. Transistors of the invention may have a gain of greater than or equal to 5 dB. In some embodiments, the gain may be greater than or equal to 12 dB (e.g., between 12 and 15). In some cases, a gain of less than or equal to 18 dB may be desired to limit sacrifices to other properties.
Bias conditions also may be used to control RCE (EVM) values, efficiency and output power. For example, it has been discovered that operating under class AB conditions may be preferable in some cases. As known to those of skill in the art, class AB operation is when the transistor is biased in such a way that current flows in the device for 51%-99% of the input signal. Class AB is between class A which operates on 100% of the input signal and class B which operates on 50% of the input signal. It may be particularly preferred to operate in deep class AB as near to maximum linear power as possible. In some embodiments, it may be preferred to operate between 51% and 75% of the input signal; in some cases, between 51% and 60% (e.g., about 55%).
However, it should be understood that it may also be possible to achieve the desired linearity when operating under other classes if operation (other than AB) in some embodiments of the invention.
In some cases, the transistors are operated at drain voltages of up to 300 Volts. In some cases, the drain voltage may be up to 100 Volts or up to 50 Volts (e.g., 12 Volts, 28 Volts or 48 Volts). Suitable gate voltages may be between 0 Volts and −10 Volts.
The transistors of the invention may be operated in frequency ranges between about 500 MHz and about 10 GHz; and, in some cases, within a frequency range of between about 2 and about 6 GHz (e.g., 3.3-3.8 GHz; or 2.3-2.7 GHz; or about 5.8 GHz). It should be understood that, in these embodiments, the input and/or output signal of the transistors may be within these frequency ranges
In some cases, transistors of the invention may advantageously exhibit the above-noted property values (i.e., RCE, EVM, efficiency, output power, power density, gain) over a fairly wide frequency range. For example, the above-noted property values may be exhibited over a bandwidth of at least 100 MHz in some embodiments; or, in other embodiments, at least 200 MHz.
It should also be understood that transistors of the invention may operate simultaneously at the above-noted RCE and EVM values, while exhibiting the above-noted power densities, efficiencies and gains.
In some embodiments, device performance is not negatively impacted by changes in temperature. That is, devices of the invention may have good temperature stability.
The properties noted above enable transistors of the invention to be used in RF power applications. In particular, the transistors may be suitable for wideband power applications (e.g., WiMAX, WiBro, and others) based on OFDM modulation. However, it should be understood, that devices of the invention may be used in other applications.
Referring again to
In some cases, the gallium nitride material region includes only one gallium nitride material layer. In other cases, the gallium nitride material region includes more than one gallium nitride material layer. For example, the gallium nitride material region may include multiple layers (12a, 12b, 12c), as shown. In certain embodiments, it may be preferable for the gallium nitride material of layer 12b to have an aluminum concentration that is greater than the aluminum concentration of the gallium nitride material of layer 12a. For example, the value of x in the gallium nitride material of layer 12b (with reference to any of the gallium nitride materials described above) may have a value that is between 0.05 and 1.0 greater than the value of x in the gallium nitride material of layer 12a, or between 0.05 and 0.5 greater than the value of x in the gallium nitride material of layer 12a. For example, layer 12b may be formed of Al0.26Ga0.74N, while layer 12a is formed of GaN. This difference in aluminum concentration may lead to formation of a highly conductive region at the interface of the layers 12a, 12b (i.e., a 2-D electron gas region). In the illustrative embodiment, layer 12c may be formed of GaN.
Gallium nitride material region 12 also may include one or more layers that do not have a gallium nitride material composition such as other III-V compounds or alloys, oxide layers, and metallic layers.
The gallium nitride material region is of high enough quality so as to permit the formation of devices therein. Preferably, the gallium nitride material region has a low crack level and a low defect level. As described further below, transition layer 22 (particularly when compositionally-graded) may reduce crack and/or defect formation. Gallium nitride materials having low crack levels have been described in U.S. Pat. No. 6,649,287 incorporated by reference above. In some cases, the gallium nitride material region a crack level of less than 0.005 μm/μm2. In some cases, the gallium nitride material region has a very low crack level of less than 0.001 μm/μm2. In certain cases, it may be preferable for gallium nitride material region to be substantially crack-free as defined by a crack level of less than 0.0001 μm/μm2.
In some embodiments, gallium nitride materials having low dislocation densities may be preferred. Suitable gallium nitride materials and processes for forming the same are described in commonly-owned, co-pending U.S. patent application Ser. No. 10/886,506, filed Jul. 7, 2004, entitled “III-Nitride Materials Including Low Dislocation Densities and Methods Associated With the Same”.
In certain cases, the gallium nitride material region includes a layer or layers which have a monocrystalline structure. In some cases, the gallium nitride material region includes one or more layers having a Wurtzite (hexagonal) structure.
The thickness of the gallium nitride material region and the number of different layers are dictated, at least in part, by the requirements of the specific device. At a minimum, the thickness of the gallium nitride material region is sufficient to permit formation of the desired structure or device. The gallium nitride material region generally has a thickness of greater than 0.1 micron, though not always. In other cases, gallium nitride material region 12 has a thickness of greater than 0.5 micron, greater than 0.75 micron, greater than 1.0 microns, greater than 2.0 microns, or even greater than 5.0 microns.
As noted above, the device includes passivating layer 24 formed on the surface of gallium nitride material region 12. Suitable passivating layers (some of which also function as electrode-defining layers) have been described in commonly-owned, co-pending U.S. patent application Ser. No. 10/740,376, filed Dec. 17, 2003, entitled “Gallium Nitride Material Devices Including an Electrode-Defining Layer and Methods of Forming The Same”, which is incorporated herein by reference.
Suitable compositions for passivating layer 24 include, but are not limited to, nitride-based compounds (e.g., silicon nitride compounds), oxide-based compounds (e.g., silicon oxide compounds), polyimides, other dielectric materials, or combinations of these compositions (e.g., silicon oxide and silicon nitride). In some cases, it may be preferable for the passivating layer to be a silicon nitride compound (e.g., Si3N4) or non-stoichiometric silicon nitride compounds.
In certain preferred embodiments, substrate 20 is a silicon substrate. Silicon substrates may be preferred because they are readily available, relatively inexpensive and are of high crystalline quality.
As used herein, a silicon substrate refers to any substrate that includes a silicon surface. Examples of suitable silicon substrates include substrates that are composed entirely of silicon (e.g., bulk silicon wafers), silicon-on-insulator (SOI) substrates, silicon-on-sapphire substrate (SOS), and SIMOX substrates, amongst others. Suitable silicon substrates also include substrates that have a silicon wafer bonded to another material such as diamond, AlN, or other polycrystalline materials. Silicon substrates having different crystallographic orientations may be used. In some cases, silicon (111) substrates are preferred. In other cases, silicon (100) substrates are preferred.
It should be understood that other types of substrates may also be used including sapphire, silicon carbide, indium phosphide, silicon germanium, gallium arsenide, gallium nitride material, aluminum nitride, or other III-V compound substrates. However, in embodiments that do not use silicon substrates, all of the advantages associated with silicon substrates may not be achieved.
It should also be understood that though the illustrative embodiments include a substrate, other embodiments of the invention may not have a substrate. In these embodiments, the substrate may be removed during processing. In other embodiments, the substrate may also function as the gallium nitride material region. That is, the substrate and gallium nitride material region are the same region.
Substrate 20 may have any suitable dimensions and its particular dimensions are dictated, in part, by the application and the substrate type. Suitable diameters may include, but are not limited to, 2 inches (50 mm), 4 inches (100 mm), 6 inches (150 mm), and 8 inches (200 mm).
In some cases, it may be preferable for the substrate to be relatively thick, such as greater than about 125 micron (e.g., between about 125 micron and about 800 micron, or between about 400 micron and 800 micron). Relatively thick substrates may be easy to obtain, process, and can resist bending which can occur, in some cases, when using thinner substrates. In other embodiments, thinner substrates (e.g., less than 125 microns) are used. Though thinner substrates may not have the advantages associated with thicker substrates, thinner substrates can have other advantages including facilitating processing and/or reducing the number of processing steps. In some processes, the substrate initially is relatively thick (e.g., between about 200 microns and 800 microns) and then is thinned during a later processing step (e.g., to less than 150 microns).
In some preferred embodiments, the substrate is substantially planar in the final device or structure. Substantially planar substrates may be distinguished from substrates that are textured and/or have trenches formed therein (e.g., as in U.S. Pat. No. 6,265,289). In the illustrative embodiments, the regions/layers formed on the substrate (e.g., transition layer, gallium nitride material region, and the like) may also be substantially planar. As described further below, such regions/layers may be grown in vertical (e.g., non-lateral) growth processes. Planar substrates and regions/layers can be advantageous in some embodiments, for example, to simplify processing. Though it should be understood that, in some embodiments of the invention, lateral growth processes may be used as described further below.
Transition layer 22 may be formed on substrate 20 prior to the deposition of gallium nitride material region 12. The transition layer may accomplish one or more of the following: reducing crack formation in the gallium nitride material region 12 by lowering thermal stresses arising from differences between the thermal expansion rates of gallium nitride materials and the substrate; reducing defect formation in gallium nitride material region by lowering lattice stresses arising from differences between the lattice constants of gallium nitride materials and the substrate; and, increasing conduction between the substrate and gallium nitride material region by reducing differences between the band gaps of substrate and gallium nitride materials. The presence of the transition layer may be particularly preferred when utilizing silicon substrates because of the large differences in thermal expansion rates and lattice constant between gallium nitride materials and silicon. It should be understood that the transition layer also may be formed between the substrate and gallium nitride material region for a variety of other reasons. In some cases, for example when a silicon substrate is not used, the device may not include a transition layer.
The composition of transition layer 22 depends, at least in part, on the type of substrate and the composition of gallium nitride material region 12. In some embodiments which utilize a silicon substrate, the transition layer may preferably comprise a compositionally-graded transition layer having a composition that is varied across at least a portion of the layer. Suitable compositionally-graded transition layers, for example, have been described in commonly-owned U.S. Pat. No. 6,649,287, entitled “Gallium Nitride Materials and Methods,” filed on Dec. 14, 2000, which is incorporated herein by reference. Compositionally-graded transition layers are particularly effective in reducing crack formation in the gallium nitride material region by lowering thermal stresses that result from differences in thermal expansion rates between the gallium nitride material and the substrate (e.g., silicon). In some embodiments, when the compositionally-graded, transition layer is formed of an alloy of gallium nitride such as AlxInyGa(1-x-y)N, AlxGa(1-x)N, or InyGa(1-y)N, wherein 0≦x≦1,0≦y≦1. In these embodiments, the concentration of at least one of the elements (e.g., Ga, Al, In) of the alloy is typically varied across at least a portion of the cross-sectional thickness of the layer. For example; when the transition layer has an AlxInyGa(1-x-y)N composition, x and/or y may be varied; when the transition layer has a AlxGa(1-x)N composition, x may be varied; and, when the transition layer has a InyGa(1-y)N composition, y may be varied.
In certain preferred embodiments, it is desirable for the transition layer to have a low gallium concentration at a back surface which is graded to a high gallium concentration at a front surface. It has been found that such transition layers are particularly effective in relieving internal stresses within the gallium nitride material region. For example, the transition layer may have a composition of AlxGa(1-x)N, where x is decreased from the back surface to the front surface of the transition layer (e.g., x is decreased from a value of 1 at the back surface of the transition layer to a value of 0 at the front surface of the transition layer). The composition of the transition layer, for example, may be graded discontinuously (e.g., step-wise) or continuously. One discontinuous grade may include steps of AlN, Al0.6Ga0.4N and Al0.3Ga0.7N proceeding in a direction toward the gallium nitride material region.
In some cases, the transition layer has a monocrystalline structure.
It should be understood that, in some embodiments, transition layer 22 has a constant (i.e., non-varying) composition across its thickness.
The source, drain and gate electrodes may be formed of any suitable conductive material such as metals (e.g., Au, Ni, Pt), metal compounds (e.g., WSi, WSiN), alloys, semiconductors, polysilicon, nitrides, or combinations of these materials. In particular, the dimensions of the gate electrode can be important to device performance. In the illustrative embodiment, via 26 formed in the passivating layer defines (at least in part) the gate electrode dimensions. Thus, by controlling the shape of the via, it is possible to define desired gate dimensions. Suitable via and gate dimensions have been described in U.S. patent application Ser. No. 10/740,376, incorporated by reference above.
In some embodiments, electrodes may extend into the gallium nitride material region. For example, electrode material (e.g., metal) deposited on the surface of the gallium nitride material region may diffuse into the gallium nitride material region during a subsequent annealing step (e.g., RTA) when forming the electrode. In particular, the source and drain electrodes may include such a portion diffused into the gallium nitride material region. As used herein, such electrodes are still considered to be formed on the gallium nitride material region.
Source, gate and drain pads may be formed of any suitable conductive material such as metals (e.g., Au, Ni, Pt), metal compounds (e.g., WSi, WSiN), alloys, semiconductors, polysilicon, nitrides, or combinations of these materials. In some embodiments, the pads are formed of the same material as the corresponding electrodes.
The device shown in
It should be understood that the transistor structure may include other layers. For example, the transistor structure may include additional features not shown in
In some embodiments, other layers (e.g., intermediate layers) may be present. Suitable intermediate layers, for example, have been described and illustrated in U.S. Pat. No. 6,649,287, which was incorporated by reference above. In other embodiments of the invention, layer(s) shown herein may not be present. Other variations to the structures and devices shown herein would be known to those of skill in the art and are encompassed by the present invention.
Structures and devices of the present invention may be formed using methods that employ conventional processing techniques. In general the stack of material layers is formed on a substrate which is later processed (e.g., diced) to form the desired final structure (e.g., transistor).
For example, the layers and regions of the transistor structure of
Transition layer 22 and gallium nitride material region 12 may be deposited, for example, using metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydride vapor phase epitaxy (HVPE), amongst other techniques. The preferred technique may depend, in part, on the composition of the layers. An MOCVD process may be preferred. A suitable MOCVD process to form a transition layer (e.g., a compositionally-graded transition layer) and gallium nitride material region over a silicon substrate has been described in U.S. Pat. No. 6,649,287 incorporated by reference above. When the semiconductor material region has different layers, in some cases it is preferable to use a single deposition step (e.g., an MOCVD step) to form the entire gallium nitride material region. When using the single deposition step, the processing parameters are suitably changed at the appropriate time to form the different layers. In certain preferred cases, a single growth step may be used to form the transition layer and the gallium nitride material region.
When present, the stress-absorbing layer may be formed using techniques described in U.S. patent application Ser. No., 10/879,703 which is incorporated by reference above.
Passivating layer 24 may be deposited using any suitable technique. The technique used, in part, depends on the composition of the passivating layer. Suitable techniques include, but are not limited to CVD, PECVD, LP-CVD, ECR-CVD, ICP-CVD, evaporation and sputtering. When the passivating layer is formed of a silicon nitride material, it may be preferable to use PECVD to deposit the layer.
When present, via 26 may be formed within the passivating layer using an etching technique. A plasma etching technique is preferably used to form the via with controlled dimensions
Source, drain and gate electrodes may be deposited on the gallium nitride material region using known techniques such as an evaporation technique. In cases when the electrodes include two metals, then the metals are typically deposited in successive steps. The deposited metal layer may be patterned using conventional methods to form the electrodes. In some embodiments, an annealing step (e.g., RTA) may also be used in which the deposited electrode material diffuses into the gallium nitride material region, particularly when forming source and drain electrodes.
Suitable techniques for forming the passivating layer, via and electrodes have been described in commonly owned, co-pending U.S. patent application Ser. No. 10/740,376, which is incorporated herein by reference above.
Source, drain and gate electrode pads may also be deposited and patterned using known techniques.
In some embodiments, an isolation region may be formed which electrical isolates the active region. Suitable processes for forming isolation region have been described in commonly owned, co-pending U.S. patent application Ser. No. 10/879,795, filed Jun. 28, 2004, entitled “Gallium Nitride Material Structures Including Isolation Regions and Methods”, which is incorporated herein by reference above.
The above-described processes are used to form a semiconductor wafer including the desired material layers and features. The wafer may be further processed using conventional techniques to produced the desired structure. In some methods, the wafer may be thinned from its backside. A metallic layer (e.g., gold) may then be deposited on the backside. The wafer may be diced to form transistors (e.g., die) which can be further processed. When mounting on a package, the transistor may be placed in the package and subjected to a heating step sufficient to weld the transistor to the packaging material. In other embodiments, the transistors are mounted to other entities (e.g., a heat sink) using known techniques.
It should be understood that the invention encompasses other methods than those specifically described herein. Also, variations to the methods described above would be known to those of ordinary skill in the art and are within the scope of the invention.
The following examples are not limiting and are presented for purposes of illustration.
A high electron mobility transistor (HEMT) having a design similar to the structures illustrated in
The transistor was designed for operating at 3.3-3.9 GHz (WiMAX applications). The following test conditions were used (unless otherwise noted): case temperature of 25±3 degrees Celsius; single carrier OFDM waveform 64-QAM ¾; 8 burst; 20 msec frame; 15 msec frame data; 3.5 MHz channel bandwidth; Peak/Avg=10.3 dB @ 0.01% probability on CCDF; frequency=3400-3600 MHz; Pout=38 dBm; Vdd=28V; Idq=750 mA.
The example establishes that transistors of the invention can exhibit excellent properties including linearity properties.
Having thus described several aspects of at least one embodiment of this invention, it is to be appreciated various alterations, modifications, and improvements will readily occur to those skilled in the art. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description and drawings are by way of example only.
This application claims priority to U.S. Patent Application Ser. No. 60/723,824, filed on Oct. 4, 2005 which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60723824 | Oct 2005 | US |
