Galvanic isolation device

Abstract

A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.

Description

BACKGROUND

This relates generally to transmission of data in high voltage systems, and more particularly to galvanic isolation devices for the transmission of data.

Galvanic isolation is a principle of isolating functional sections of electrical systems to prevent current flow from one section to another. In order to prevent current flow, no direct conduction path is permitted. Energy or information can still be exchanged between the sections by other means, such as capacitance, induction, or electromagnetic waves, or by optical, acoustic, or mechanical means.

Galvanic isolation may be used where two or more electric circuits must communicate, but their grounds may be at different potentials. It is an effective method of breaking ground loops by preventing unwanted current from flowing between two units sharing a ground conductor. Galvanic isolation is also used for safety, preventing accidental current from reaching ground through a person's body.

Integrated, capacitive-based, galvanic isolators allow information to be transmitted between nodes of a system at different voltage levels using a high voltage (HV) capacitive barrier along with a differential transmitter and receiver on either side of that barrier. The HV capacitors may be integrated as discrete capacitors, or combined within the transmitter and receiver integrated circuits. In the latter case, each integrated circuit (IC) has a HV capacitor constructed in the IMD (inter-metal dielectric) layers that form the top layers of each IC. HV capacitors are typically implemented on each IC within a single package and connected by bond wires to create a composite capacitor formed from two series capacitors elements. This redundancy provides an increased level of safety, because even if one cap fails, a second capacitor provides isolation.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual block diagram of an example galvanic isolation device.

FIGS. 2A, 2B and 3 are views of an example galvanic isolation device embodied with two stacked integrated circuit dies.

FIGS. 4A-4B are cross sectional views illustrating alternative isolation layer embodiments.

FIGS. 5A-5F are cross sectional views illustrating fabrication of an isolated semiconductor region.

FIG. 6 is a cross sectional view of another example galvanic isolation device with air gaps.

FIGS. 7A and 7B are a cross sectional view and a top view of another example galvanic isolation device embodied with a single IC die.

FIG. 8 is a flow chart illustrating fabrication of a galvanic isolation device.

FIG. 9 is a block diagram of an example system that includes a galvanic isolation device.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

In this drawings, like elements are denoted by like reference numerals for consistency.

In an embodiment, a transmitter integrated circuit (IC) die may be stacked on top of a receiver die that may also include additional application circuitry. The die attach material between the transmitter and the receiver may be a single or a multi-layer “re-enforced isolation” dielectric film. Multiple, dielectrically isolated capacitors may be formed between the two die using bottom plates formed in the top-layer metal under the passivation of the lower die and top plates that may be formed within an isolated semiconductor region on the top die or by a metallic conductive plate formed on the top die.

Galvanic isolation is a principle of isolating functional sections of electrical systems to prevent current flow from one section to another. In order to prevent current flow, no direct conduction path is permitted. Energy or information can still be exchanged between the sections by other means, such as capacitance, induction, or electromagnetic waves, or by optical, acoustic, or mechanical means. The general operation of capacitor based galvanic isolation devices is described in “Digital Isolator Design Guide,” SLLA284A, revised November 2014, which is incorporated by reference herein. A quad-channel isolator that withstands 8 kv peak voltage is available from Texas Instruments; see, for example, “ISO7841x High-Performance, 8000-Vpk Reinforced Quad-Channel Digital Isolator,” revised April 2016.

Capacitive coupling uses a changing electric field to transmit information across an isolation barrier. The material between the capacitor plates is a dielectric insulator and forms the isolation barrier. The plate size, distance between the plates, and the dielectric material determine the electrical properties.

A capacitive isolation barrier provides efficiency, in both size and energy transfer, and immunity to magnetic fields. The former enables low-power and cost-effective integrated isolation circuits. The latter enables operation in saturated or dense magnetic field environments.

Capacitive coupling does not pass steady-state signals and requires clock-encoded data. Unlike a transformer, a single sided capacitive coupling has no differential signal and noise, and the signal may share the same transmission path. This requires that the signal frequencies be well above the expected frequency of noise so that the barrier capacitance presents low impedance to the signal and high impedance to the noise. A differential coupling topology may be used to provide improved noise rejection.

In conventional capacitor based galvanic isolation devices, the HV (high voltage) isolation capacitors may be implemented as discrete capacitors, or combined within the transmitter and receiver integrated circuits. In the latter case, each integrated circuit (IC) may have an HV capacitor constructed in the IMD (inter-metal dielectric) layers that form the top layers of each IC. HV capacitors are usually implemented on each IC within a single package and connected by bond wires to create a composite capacitor formed from two series capacitors elements. These HV capacitors may be fabricated using expensive process additions that may add up to seven layers of additional IMD and metal layers on top of each die in which a complete isolation capacitor is fabricated. This isolation extension process (ISO process) may only be offered on limited processes nodes available in a semiconductor foundry, and as such this may exclude the galvanic isolation feature on products that are taking advantage of the offerings of the latest technologies. This process node restriction drives some applications to incur the cost of three IC die in the isolation device package.

Thus, as base fabrication processes advance, isolation capabilities cannot follow process advances without incurring a significant development effort for each new process node. The number of die, lateral spacing to enable proper standoff voltage and bond wires may force larger package footprints than desired. In prior devices, each isolator die may be subjected to the full withstand voltage, both laterally and vertically within the surface dielectrics of that die.

FIG. 1 is a conceptual block diagram of an example galvanic isolation device 100. This example device may use an ON-OFF Keying (OOK) modulation scheme to transmit digital data from a transmit input (TX in) port across a dielectric isolation barrier 110 using capacitive coupling with capacitor plates 136, 137 on each side of isolation barrier 110. A transmitter 101 may send a high-frequency carrier across barrier 110 to represent one digital state and may send no signal to represent the other digital state, for example. A receiver 102 demodulates the signal in detection circuit 116 after the signal passes through signal conditioning circuit 115 and produces a receiver output signal (RX out) through a buffer stage 117. In this example, output buffer 117 is a tri-state buffer; the output goes to high impedance when the EN pin is low.

Device 100 may also incorporate known or later developed circuit techniques to maximize common mode transient immunity (CMTI) performance and minimize radiated emissions produced by the high-frequency carrier and IO buffer switching. Transients may be a concern in capacitive coupling of signals. Differential transfer across the isolation barrier of the input single-ended logic signal allows the use of low-level signals and small coupling capacitance. The small coupling capacitance appears as high impedance to lower-frequency common-mode noise and with the common-mode noise rejection of the receiver provides transient immunity.

In this example, OOK modulator 111 may modulate the TX IN signal with the aid of a clock signal provided by oscillator 112 using known or later developed modulation techniques, for example. The modulated signal may then be provided to differential buffers 113a, 113b and then conditioned by conditioning circuitry 114 using known or later developed conditioning techniques to prepare the differential signals for capacitive coupling across dielectric isolate barrier 110.

In some embodiments, device 100 may use both a high-signaling rate and low-signaling rate channel to provide transfer of steady-state information. The high signaling-rate channel does not need to be encoded and it may transmit data transitions across the barrier after a single-ended-to-differential conversion. The low signaling-rate channel may encode the data in a pulse-width modulated format, for example, and transmit the data across the barrier differentially, ensuring the accurate communication of steady-state conditions such as a long string of 1s or 0s.

FIG. 2A is a cross sectional view of an example galvanic isolation device 200 embodied with two stacked back IC dies 201, 202 separated by a reinforced isolation film 210. FIG. 2B is a top view of the top die 201. Bottom die 202 may be mounted on a lead frame support pan 221. The lead frame may have a set of leads 222 that may be coupled to upper die 201 via bond wires 224, for example. In order to prevent voltage breakdown across the lead frame, a distance 226 between leads 222 and support pan 221 should be sufficient to prevent arcing of the maximum expected voltage specified for isolation device 200. The lead frame may also have a set of leads 223 that may be coupled to lower die 202 via bond wires 225, for example. Various configurations of lead frames are known.

Bottom die 202 may include communication circuitry such as circuits 115-117 described in FIG. 1. The communication circuitry may be either a transmitter or a receiver, depending on the direction of signal flow across the isolation layer. Bottom die 202 may also include additional application circuitry for a particular application, as described in more detail below. Bottom die 202 also includes a set of capacitor plates 237 that may be formed in a top metal layer of die 202.

Top die 201 may include communication circuitry such as circuits 111-114 described in FIG. 1. The communication circuitry may be either a transmitter or a receiver, depending on the direction of signal flow across the isolation layer. Top die 201 may also include additional application circuitry for a particular application. Top die 201 also includes a set of capacitor plates 236 that are juxtaposed with the set of capacitor plates 237 in bottom die 202 but separated by dielectric isolation layer 210 to form a set of coupling capacitors 231,232 between top die 201 and bottom die 202.

In this example, the capacitor plates 236 in top die 201 are formed by highly doped semiconductor regions that are electrically isolated from the rest of top die 201 by dielectric filed trenches, such as indicated at 233. In this example, an array of four vertical capacitors 231, 232 is formed between the two die; two that are labeled “A” and two that are labeled “B.” Diagonally positioned “A” capacitors may be interconnected and used for coupling one of the differential signals from die 201 to die 202 and the opposite diagonal positioned “B” capacitors may be interconnected and used for coupling the other differential signal from die 201 to die 202. Each pair of capacitors may be differentially driven and then differentially received with an interface circuit as described in more detail with regard to FIG. 1. Such diagonally connected arrays may be referred to as “common centroid arrays” and are commonly used to compensate for process differences across a region of a die. While an array of four capacitors is illustrated here, other embodiments may use larger cross-coupled arrays, while another embodiment may use only a single capacitor for each differential signal, for example.

FIG. 3 is a more detailed cross sectional view of a portion of FIG. 2A that illustrates vertical capacitor 231 in more detail. Upper die 201 may include a number of various semiconductor layers, such as a heavily doped P+ substrate layer 335, a P+ doped buried layer (P+ BL), a lightly P doped epitaxial layer (P− epi), and a heavily doped P+ source/drain contact layer (P+ SD), for example. As described in more detail below, a portion of P+ substrate layer 335 may be electrically isolated from the rest of layer 335 by dielectric filled trenches 233 to form a conductive plate 236. In this example, dielectric filled trenches 233 are approximately 50 μm wide, for example. Conductive plate 236 may act as a top plate of vertical capacitor 231. An interconnect trace 334 may be patterned on a metal layer of die 201 to connect conductive plate 236 to communication circuitry 311. In this example, communication circuitry 311 is a transmitter with one output driving plate 236 of vertical capacitor 231 and an inverted output differentially driving vertical capacitor 232, referring again to FIG. 2A.

Additional semiconductor layers may be formed above P+ layer 335; these various layers may all be P doped to varying levels. The sequential stacking and composition of the various layers are unimportant in this example. Each IC manufacturing process may use different stacks of materials, for example; sometimes with and sometimes without a P+ buried layer (BL). In the layer stackup, the bottom region 236 of top die 201 is the top plate of the capacitor, and a way is needed to connect to it from the surface metal trace 334 on top of the top die. If the bottom of the top die is P, then a path is needed through all P-doped silicon and metal between top metal 334 and conductive plate 236 of top die 201. An N-doped layer should not be in-between, because that would form a diode.

In an example IC process, the P+ S/D layer is commonly used as the source and drain of P-channel MOSFETs (metal oxide semiconductor field-effect transistor) and it is available for other uses, such as contacting the bottom of the wafer. These P-channel MOSFETs are usually built in N-well. In this example, the N-well may be either omitted from the process or masked (blocked) in the region of the vertical capacitors.

In this example, top die 201 may be approximately 10 mils thick or about 254 u thick; however, in other embodiments it may be thicker or thinner, for example, depending on the fabrication process. This example illustrates a P doped die 201. In another embodiment, the die may be N doped, for example. In either case, the conductive plate region 236 needs to be doped to a high enough level to be conductive.

Bottom die 202 may have a bottom plate 237 of vertical capacitor 231 formed in a top metal layer of die 202. Usually, a die may have several layers of metal for interconnect and power provisioning. Each metal layer may be separated from the next by an inter-metal dielectric (IMD) layer 303, which is usually silicon oxide, silicon nitride, or another insulating film, for example. A passivation layer is usually formed over the top metal layer for protection against corrosion.

Bottom plate 237 is connected to communication circuitry such as signal conditioning circuit 315 and differential receiver 316. Differential receiver 316 receives an inverted differential signal from the other vertical capacitor 232, referring back to FIG. 2A. A lateral shield 338 and vertical shield 339 may be grounded or connected to another voltage source, for example, to reduce emissions from vertical capacitor 231. Lateral shield 338 may be an N+ doped region, for example. Vertical shield 339 may be patterned from one or more metal layers, for example.

In this example, the communication circuitry includes a differential transmitter in top die 201 with an output connected to the top plate 236 of vertical capacitor 231 and a differential receiver in bottom die 201 with an input connected to the bottom plate 237 of vertical capacitor 231. In another embodiment, this arrangement may be reversed with a receiver in the top die and a transmitter in the bottom die, for example.

Dielectric isolation layer 210 may include several layers in order to provide redundancy and increased voltage breakdown protection. Dielectric isolation layer 210 may be formed by depositing one or more layers of film, such as traditional epoxy, prefabricated polymer sheet film, inkjet printed plastic, etc. Each layer may be applied as a liquid that hardens to allow additional layers to be added. Isolation layer 210 may also include a layer of adhesive so that it can also function as a die attach layer. For example, an adhesive layer may be applied as a liquid to either one of dies 201 or 202 that hardens after placement of the other die 201, 202.

In this embodiment, isolation layer 210 includes multiple layers to form a re-enforced dielectric isolation die attach film that is approximately 50 to 100 μm thick. In some embodiments, isolation layer 210 may be configured to extend beyond an edge of bottom die 202.

In another embodiment, a top die may be fabricated in a similar configuration to bottom die 202 in which an array of top conductive plates is fabricated in a top metal layer of the top die. In this case, the top die may be flipped and then bonded to the dielectric isolation layer such that the array of top conductive plates is juxtaposed with the array of lower conductive plates to form vertical capacitors for coupling signals across the dielectric isolation layer. In this case, “through silicon vias” (TSV) may be used to connect communication circuitry in the top die to deposited metal bond pads on the backside of the top die, which is now the “new” top side of the top die.

In another embodiment, the top die may be in a normal orientation and TSVs may be used to connect to top conductive plates that are fabricated from a metal layer, or other conductive layer, that is deposited on the bottom side of the top die, for example.

FIGS. 4A-4B are cross sectional views illustrating examples of alternative isolation layer embodiments. In some embodiments, isolation layer 410 of device 400 may be extended beyond one or more edges of bottom die 202 as illustrated at 411 in FIG. 4A in order to provide enhanced voltage arcing protection. In this case, the film may be a prefabricated stack of dielectric layers that is then affixed to lower die 202, for example.

In some embodiments, isolation layer 410 of device 401 may be extended over and down one or more edges of bottom die 202 as illustrated at 412 in FIG. 4B in order to provide enhanced voltage arcing protection. In this case, isolation layer 410 may be applied as one or more layers using an inkjet printing technique, for example. Fabrication of three dimensional structures using ink jet printers or similar printers that can “print” various polymer materials is known and not described in further detail herein. For example, see “3D printing,” Wikipedia, Sep. 4, 2014. Printing allows for the rapid and low-cost deposition of thick dielectric and metallic layers, such as 0.1 μm-1000 μm thick, for example, while also allowing for fine feature sizes, such as 20 μm feature sizes, for example.

In some embodiments, micro-drop deposition of dielectric material may be used to form one or more layers of isolation layer 410. Electrohydrodynamic jet printing may be used to perform micro-drop deposition, for example.

In some embodiments, isolation layer 410 may cover the entire top surface of bottom die 202. In this case, provisions would need to be made to provide openings at the bond pads of wire bonds 225.

In some embodiments, the isolation layer may include silicon, in the form of non-conductive silicon compounds, such as SiO2 or SiN (silicon nitride), or other materials used as IC passivation or materials used for the inter-metal dielectric.

In another embodiment, the isolation layer may include two or more individual layers of dielectric material with a metallic layer between two of the layers of dielectric material. In this case, the metallic layer acts as an intermediate capacitor plate and thereby each coupling capacitor (similar to 231) may act as two capacitors in series.

FIGS. 5A-5F are cross sectional views illustrating fabrication of an isolated semiconductor region, such as region 236 in FIG. 3. As described with regard to region 236, a portion of substrate 535 may be electrically isolated by dielectric filled trenches from the rest of substrate 535 to form a conductive plate for a vertical capacitor, such as plate 236 of vertical capacitor 231, as shown in FIG. 3. Various embodiments of isolated regions and methods for fabricating them are described in U.S. Pat. No. 9,419,075, “Wafer Substrate Removal,” Dan Carothers et al, which is incorporated by reference herein. An example process for fabricating an isolated region will now be described herein.

Initially, a semiconductor wafer 500 may be fabricated as shown in FIG. 5A using known or later developed fabrication techniques. The wafer includes a substrate 535 and may include multiple layers on top of the substrate. For example, in an epitaxial (epi) layer 540, various transistors may fabricated to form circuitry, such as communication circuitry 311 as shown in FIG. 3. Additional metal, IMD, and passivation layers (not shown) may be fabricated on top of epi layer 540. In this example, the wafer is initially approximately 750 μm thick.

The wafer may then be patterned and etched to form deep trenches, such as indicated at 541 in FIG. 5B, using known or later developed etching technology. These trenches may from rectangular, square, circular, or other configurations, such as trench 233 as shown in FIG. 2B. These trenches need to be at least as deep as the final thickness of the wafer after grinding, but other than that the depth is not critical. In this example, the trenches may be approximately 50-100 μm wide, for example.

The trenches are then filed with a suitable dielectric that can support the isolated regions after the wafer is back-ground to its final thickness. In this embodiment, the trenches may be filed using an inkjet process as indicated at 542 in FIG. 5C.

After the trenches are filed, a back-grind operation may be performed using known or later developed grinding techniques to produce a wafer that is approximately 600 μm thick in this embodiment. This causes the trenches to extend completely through substrate 635 and thereby form isolated regions as indicated at 536 in FIG. 5D. These regions may be similar to isolated regions 236 in FIG. 2B, for example.

In some embodiments, one or more metal layers may be deposited, patterned and etched to form straps or metal interconnect traces that cross the trenches, as indicated at 543 in FIG. 5E. These may be used to form interconnects, such as interconnect 334 shown in FIG. 3.

After wafer fabrication is complete, the wafer may be sawn or scribed to singulate the dies from each other using known or later developed sawing or scribing techniques, as indicated at 544 in FIG. 5F.

FIG. 6 is a cross sectional view of another example galvanic isolation device 600 with air gaps 640. This device may be similar to device 200 of FIG. 2A, but with the addition of air gaps 640 to minimize undesirable lateral coupling between vertical capacitors 231-232. In this embodiment, air-dielectric gaps may be fabricated above isolation layer 610 by selective printing of die attach layer 641. Die attach layer 641 may be selectively printed using inkjet printing, for example. Alternatively, die attach layer 641 may be uniformly applied to a wafer and then patterned and etched using known or later developed semiconductor fabrication techniques.

FIGS. 7A and 7B are a cross sectional view and a top view of another example galvanic isolation device 700 embodied with a single IC die. Dielectric isolation layer 710 may be a stack of N-layers of dielectric that are physically separate from the composite of the silicon die structure 202 beneath. The uppermost layer of dielectric stack 710 may have a printed conductive pattern 736 to form the top plates of vertical capacitors 231-232, as shown in FIG. 7B. In this case, an inkjet printing process may be used, for example. In this case, since a second die is not provided that contains communication circuitry, an external communication circuit may be use to provide a differential signal to couple through vertical capacitors 231, 232, for example.

Alternatively, upper plates 736 may be formed by a subtractive process where a conductive film is evaporated, sputtered, or otherwise deposited on the uppermost dielectric layer and then that layer is masked and etched. In such an approach, the dielectric and plate “assembly” may be mass produced and processed as an independent non-silicon sheet that is then diced and added to the lower die 202.

FIG. 8 is a flow chart illustrating fabrication of a galvanic isolation device such as device 200 of FIG. 2A. As described above in more detail, an IC die (such as die 202 in FIG. 2A) may be fabricated as indicated at 802 to include an array of conductive plates in a top metal layer of the die. This IC die may be referred to as the “lower die” or “bottom die” because an “upper die” will be stacked on top of it. Each conductive plate will act as a lower plate of a vertical capacitor that may be used to couple signals produced by communication circuitry in the upper die to communication circuitry in the lower die, or vice versa. These conductive plates in the lower die may be referred to herein as “lower conductive plates.”

The lower conductive plates do not necessarily need to be fabricated in a metal layer of the bottom die. For example, to take advantage of the layer(s) of oxide in the IMD as additional isolation insulation, the bottom lower conductive plates may be a heavy doped diffusion under the IMD and passivation.

A dielectric isolation layer, such as isolation layer 210 in FIG. 2A, may be placed over a portion of the lower die as indicated at 804 to completely cover the array of lower conductive plates. In some embodiments, the dielectric layer may extend beyond one or more edges of the lower die in order to provide additional voltage breakdown capability between the upper die and the lower die. The dielectric isolation layer may include several layers in order to provide redundancy and increased voltage breakdown protection. The dielectric isolation layer may be formed by depositing one or more layers of film, such as traditional epoxy, prefabricated polymer sheet film, inkjet printed plastic, etc. The isolation layer may also include a layer of adhesive so that it can also function as a die attach layer. In this embodiment, the isolation layer includes multiple layers to form a re-enforced dielectric isolation die attach film that is approximately 50 to 100 μm thick.

As described above in more detail above, an upper IC die (such as die 201 in FIG. 2A) may be fabricated as indicated at 806 to include an array of conductive plates fabricated in isolated semi-conductive regions in the substrate of the die. This IC die may be referred to as the “upper die” or “top die” because it will be stacked on top of the lower die. Each conductive plate will act as an upper plate of the vertical capacitor that may be used to couple signals produced by communication circuitry in the upper die to communication circuitry in the lower die, or vice versa. These conductive plates in the upper die may be referred to herein as “upper conductive plates.”

The upper die may then be stacked on top of the lower die as indicated at 808 such that the array of upper conductive plates is juxtaposed with the array of lower conductive plates, but separated by the dielectric isolation layer. As described above, the dielectric isolation layer may include a layer of “die attach” adhesive, or a die attach adhesive may be added at this time.

The stacked dies may then be mounted on a lead frame, such as lead frame 221 as shown in FIG. 2A, as indicated at 810. Wire bonding may then be performed to provide connections between bond pads on the upper die and the lead frame and between the lower die and the lead frame, as illustrated in FIG. 2A.

The finished assembly may then be packaged as indicated at 812 using known or later developed packaging techniques, such as encapsulation in mold compound to form a small outline integrated circuit (SOIC) package, a flat pack, a ball grid array, etc.

In another embodiment, a separate dielectric isolation layer, such as isolation layer 710 in FIG. 7A, may be fabricated to include an array of conductive plates arranged to align with the array of conductive plates in the bottom die as upper capacitor plates, as indicated at 820. The dielectric and plate “assembly” may be mass produced and processed as an independent non-silicon sheet that is then diced and added to the lower die 202, for example. In this case, the isolation layer indicated in 804 and the second die indicated in 806 are not needed.

In another embodiment, a dielectric isolation layer, such as isolation layer 710 in FIG. 7A, may be placed over a portion of the lower die as indicated at 804 to completely cover the array of lower conductive plates. In some embodiments, the dielectric layer may extend beyond one or more edges of the lower die in order to provide additional voltage breakdown capability between the upper die and the lower die. The dielectric isolation layer may include several layers in order to provide redundancy and increased voltage breakdown protection. The dielectric isolation layer may be formed by depositing one or more layers of film, such as traditional epoxy, prefabricated polymer sheet film, inkjet printed plastic, etc. The uppermost layer of this dielectric stack may have a printed conductive pattern, such as 736 in FIG. 7B, to form the top plates, as indicated at 808. In this case, an inkjet printing process may be used, for example. In this case, an upper die as indicated at 806 is not needed.

In another embodiment, the assembly flow may involve stacking from the bottom up. In this case, the lower die may be placed on the leadframe, the dielectric added, the top die added, followed by wirebonding and then package molding.

System Example

FIG. 9 is a block diagram of an example system that includes a galvanic isolation device 953, such as described in more detail with reference to FIGS. 1-8. In this example, a system node 951 is operating in voltage domain 1. Node 951 may be any sort of system control node and may include a microcontroller, signal processor, computer system, etc. It may be a single IC, or it may be a large system. In other examples, node 951 may be a sensor device, a slave device, a master device, etc. that needs to communicate with a node in another voltage domain. Interface circuit 952 includes a galvanic isolation device 953 to provide galvanic isolation between voltage domain 1 and voltage domain 2. In this example, interface circuit 952 converts single ended data signals Din and Dout produced by node 951 into differential RS-485 signals.

In this example, the entire interface circuit 952 may be operated in a low-voltage system. However, in a multi-node distributed RS-485 network, different nodes may be referenced to grounds at different potential, in which case isolation enables communication by level shifting between those ground potentials.

Due to the simplicity of the galvanic isolation device as described in more detail above, it is possible to integrate the isolator function 953 into the transceiver circuit 952, thus providing an application-specific isolator device featuring low-cost and low component count. Other example interface devices may produce an RS-232 interface, a Serial Peripheral Interface (SPI) bus, or any number of other known or later developed communication channels, for example.

An example use for embodiments described herein is to transmit data between two circuits at different voltages. This could be as simple as an on-off command, or more complex such as control parameters, measurement data, audio, video, file transfer, or any other data. Various applications may include communicating information for diverse isolation applications such as: multi-channel digital isolators, isolated gate drive, modulated analog for isolation amplifiers, modulated analog information for isolated secondary side feedback, isolated ADCs where the delta sigma modulator digital stream is sent over the isolation barrier, power delivery over an isolation barrier. All of these are communicating information digitally using mostly high frequency RF carrier frequencies.

Example embodiments may provide safety isolation between two circuits. For example, one circuit could be a power controller connected to the power mains (120VAC or 240VAC) and the other could be a device with human interface (cell phone, tablet, game, computer terminal, etc.) In these uses, for safety reasons, standards organizations like UL require multiple insulating layers such that if one fails, the second is still intact to prevent electrocution. Usually, this is called “double insulation” or “reinforced isolation.” In various embodiments, multiple dielectric isolation layers provide this extra margin of safety.

Example embodiments enable reinforced safety isolation through the use of multiple film and surface IC oxide layers in combination with the use of cheap IC processes for the top and bottom IC dies. The breakdown voltage rating is scalable by simply increasing the thickness and/or dielectric characteristics of the dielectric isolation layer without needing any change to the top and bottom dies.

Thus, embodiments may provide galvanic isolation using inexpensive film that may be applied between stacked IC dies during the assembly process of the isolation device. The IC dies that are used to embody the isolation device may be fabricated using essentially any semiconductor processing technology, based on what is best for customer applications. This may result in higher levels of feature integration. Vertical die placement may result in a smaller package size as compared to prior devices that used lateral die placement. Voltage stress is confined to the isolation layer film only and is not transferred to the upper or lower die circuitry. Voltage breakdown may be scaled by the isolation film thickness and number of layers.

OTHER EMBODIMENTS

In other embodiments, appropriate scaling of the thickness, number of layers, and composition of the dielectric isolation layer between the upper and lower die may allow voltage breakdown ratings of several hundred volts, several kilovolts, up to a range of approximately 20 kv, for example.

In some embodiments, a single communication channel may be provided as described herein. In other embodiments, a pair of communication channels may provide two way communication. In other embodiments, multiple communication channels may exist on the same die.

As disclosed herein, two die may be stacked with a dielectric isolation layer between and vertical capacitors formed by a bottom plate in one of the dies and a top plate in the other die. Various semiconductor processes may be used to fabricated top and bottom dies that may be stacked in an example upward facing orientation or in a flip-chip orientation, depending on where on each die a conductive layer is formed for the capacitor plate. The conductive plates may be formed in either an isolated semiconductor region or fabricated from metallic layers, for example.

In another embodiment, three or more dies may be stacked, with dielectric isolation layers between each pair. In this case, the middle dies may have conductive plates formed on both a top surface and a bottom surface of the die to form vertical coupling capacitors with adjacent stacked dies.

While silicon based IC die are described herein, other embodiments may be based on germanium, gallium arsenide, silicon carbide, allotropes of carbon such as graphene, and other known or later developed semiconductor materials.

In this description, the term “couple” and derivatives thereof mean an indirect, direct, optical, and/or wireless electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, through an indirect electrical connection via other devices and connections, through an optical electrical connection, and/or through a wireless electrical connection.

Although method steps may be presented and described herein in a sequential fashion, one or more of the steps shown and described may be omitted, repeated, performed concurrently, and/or performed in a different order than the order shown in the drawings and/or described herein. Accordingly, example embodiments are not limited to the specific ordering of steps shown in the drawings and/or described herein.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A method of fabricating a galvanic isolation device, the method comprising: fabricating a first integrated circuit (IC) including first conductive plates proximate a surface of the first IC and coupled to first circuitry within the first IC;placing a dielectric isolation layer, including a die attach material, on a portion of the surface of the first IC, the dielectric isolation layer completely covering the first plates;placing second conductive plates on the dielectric isolation layer; andwith the die attach material, mounting a second IC to the first IC, a first one of the second conductive plates being juxtaposed with a first one of the first conductive plates separated from the first one of the first conductive plates by the dielectric isolation layer to form a first capacitor, and a second one of the second conductive plates being juxtaposed with a second one of the first conductive plates and separated from the second one of the first conductive plates by the dielectric isolation layer to form a second capacitor, and the second conductive plates being proximate a surface of the second IC;in which placing the dielectric isolation layer includes selectively printing the die attach material to form air gaps between the first and second capacitors.

2. The method of claim 1, wherein placing the second conductive plates includes depositing a conductive material on the dielectric isolation layer using a three dimensional (3D) printing process.

3. The method of claim 1, wherein placing the dielectric isolation layer includes performing a three dimensional printing process, and the dielectric isolation layer covers: an edge of the first IC; and the portion of the surface of the first IC.

4. The method of claim 1, wherein placing the dielectric isolation layer includes performing micro-drop deposition.

5. The method of claim 1, wherein placing the dielectric isolation layer includes: placing one or more layers of liquid material on the surface of the first IC, and allowing the layers to harden before placing the second conductive plates.

6. The method of claim 1, wherein placing the dielectric isolation layer includes applying a liquid that hardens after placing the second conductive plates.