1. Field of the Invention
The present invention relates generally to transistors, and, more particularly to a GaN transistor with reduced output capacitance.
2. Description of the Related Art
Conventional transistor devices generally experience some level of transistor power dissipation due to conduction loss and switching loss. When transistors operate at higher frequencies, it becomes even more important to reduce switching loss. Additionally, in hard switching circuits, charging and discharging the output capacitor in every switch cycle influences the power dissipation of the transistor device.
Output capacitance (“Coss”) is the summation of gate-drain capacitance and source-drain capacitance.
a) depicts a cross-sectional view of a conventional GaN transistor 101 when the drain-source voltage is at 0 volts. As shown, the GaN transistor 101 includes a substrate 109, buffer layers 110 formed on the substrate 109, and a two dimensional electron gas (“2DEG”) formed just below a barrier layer 104. Furthermore, the GaN transistor 101 includes a source electrode 102, a gate electrode 103, a drain electrode 105, a field plate 106 and a dielectric film 107.
In operation, when the drain-source voltage is at 0 volts, the Coss components of the GaN transistor 101 include a capacitor (“C1”) between the gate 103 and the drain side 2DEG 111, a capacitor (“C2”) between the field plate 106 and the drain side 2DEG 111, and a capacitor (“C3”) between the substrate 109 and the drain side 2DEG 111. When the drain-source voltage is at 0 volts, the capacitors C1, C2, and C3 are at their highest values.
b) depicts a cross-sectional view of the conventional GaN transistor 101 when the drain-source voltage is a high voltage. As drain-source voltages increase, the drain side 2DEG 111 depletes toward the drain contact 105; C1 and C2 approach zero; and C3 decreases.
A primary objective of this invention is to reduce the output capacitance Coss of a transistor while maintaining gate width, which effectively reduces power dissipation, and, therefore, increases frequency capability in RF amplifiers that include such transistors.
Embodiments described below address the problems discussed above and other problems, by providing manufacturing method of GaN semiconductor devices that include an isolation region in the transistor device that removes a portion of the 2DEG to reduce output capacitance Coss of the device.
The GaN transistor disclosed includes a substrate layer, one or more buffer layer disposed on a substrate layer, a barrier layer disposed on the buffer layers, and a two dimensional electron gas (2DEG) formed at an interface between the barrier layer and the buffer layer. Furthermore, a gate electrode is disposed on the barrier layer and a dielectric layer is disposed on the gate electrode and the barrier layer. The GaN transistor includes one or more isolation regions formed in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG in order to reduce output capacitance Coss of the GaN transistor.
Furthermore, a method for fabricating a GaN transistor device as described herein includes the steps of forming at least one buffer layer on a substrate layer; forming a barrier layer on the at least one buffer layer with a two dimensional electron gas (2DEG) disposed at an interface between the barrier layer and the buffer layer; forming a gate electrode on the barrier layer; and forming a first isolation region in a portion of the interface between the at least one buffer layer and the barrier layer to remove the 2DEG from the portion of the interface where the isolation region is formed.
The features, objects, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:
a) illustrates a cross-sectional view of a conventional GaN transistor when drain-source voltage is at 0 volts.
b) illustrates a cross-sectional view of a conventional GaN transistor when drain-source voltage is at a high voltage.
a) illustrates a schematic top view of a GaN transistor with reduced Coss in accordance with an exemplary embodiment of the present invention.
b) illustrates a cross-sectional view A-A of the GaN transistor of
c) illustrates a cross-sectional view B-B of the GaN transistor of
a)-4(e) depict a fabrication process of a GaN transistor of the present invention with reduced Coss.
The figures are not necessarily drawn to scale and the elements of similar structures or functions are generally represented by like reference numerals for illustrative purposes throughout the figures. The figures are only intended to facilitate the description of the various embodiments described herein; the figures do not describe every aspect of the teachings disclosed herein and do not limit the scope of the claims.
In the following detailed description, reference is made to certain embodiments. This detailed description is merely intended to teach a person of skill in the art further details for practicing preferred aspects of the present teachings and is not intended to limit the scope of the claims. Therefore, combinations of features disclosed in the following detailed description may not be necessary to practice the teachings in the broadest sense, and are instead taught merely to describe particularly representative examples of the present teachings. It is to be understood that other embodiments may be employed and that various structural, logical, and electrical changes may be made.
a)-3(c) illustrate a GaN device 201 with reduced Coss according to a first exemplary embodiment of the present invention. As shown in
a) and 3(b) illustrate the GaN device 201 that further includes a source electrode 202, a gate electrode 203, a drain electrode 205 and a field plate 206. In order to reduce Coss of capacitor C2, which was discussed above with reference to
As further shown in
It should be appreciated that each of isolation regions 301, 302, and 303 are formed in the buffer layer 210 of the GaN device 201 and that the 2DEG is removed where the isolation regions are formed. In particular,
In view of
It is noted that forming isolation regions 301, 302 and 303 results in an increased Rds(on). Accordingly, in one refinement of the exemplary embodiment, the area of the isolation regions are optimized to minimize power dissipation. In this instance, the product of Rds(on) and Eoss can be used as a figure of merit in this optimization. The optimal percentage area for the isolation area depends upon the voltage rating of the device, and the materials and layout parameters of the device.
a)-(e) illustrate an exemplary manufacturing process for a GaN device with reduced output capacitance Coss according to an exemplary embodiment of the present invention. As shown in
Next, as shown in
As shown in
The above description and drawings are only to be considered illustrative of specific embodiments, which achieve the features and advantages described herein. Modifications and substitutions to specific process conditions can be made. For example, in addition to GaN technology, the present invention can be applied to LDMOS as well by depleting or not creating similar patterns in the LDD. Accordingly, the embodiments of the invention are not considered as being limited by the foregoing description and drawings.
This application claims the benefit of U.S. Provisional Application No. 61/859,508, filed on Jul. 29, 2013, the entire disclosure of which is hereby incorporated by reference.
Number | Date | Country | |
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61859508 | Jul 2013 | US |