1. Field of the Invention
Embodiments of the invention generally relate to a baffle plate used to improve film deposition uniformity in a deposition processing chamber.
2. Description of the Background Art
Liquid crystal displays or flat panels are commonly used for active matrix displays such as computer and television monitors. Plasma enhanced chemical vapor deposition (PECVD) is generally employed to deposit thin films on a substrate such as a transparent substrate for flat panel display or semiconductor wafer. PECVD is generally accomplished by introducing a precursor gas or gas mixture into a vacuum chamber that contains a substrate. The precursor gas or gas mixture is typically directed downwardly through a distribution plate situated near the top of the chamber. The precursor gas or gas mixture in the chamber is energized (e.g., excited) into a plasma by applying radio frequency (RF) power to the chamber from one or more RF sources coupled to the chamber. The excited gas or gas mixture reacts to form a layer of material on a surface of the substrate that is positioned on a temperature controlled substrate support. Volatile by-products produced during the reaction are pumped from the chamber through an exhaust system.
Flat panels processed by PECVD techniques are typically large, often exceeding 370 mm×470 mm. Large area substrates approaching and exceeding 4 square meters are envisioned in the near future. Gas distribution plates (or gas diffuser plates) utilized to provide uniform process gas flow over flat panels are relatively large in size, particularly as compared to gas distribution plates utilized for 200 mm and 300 mm semiconductor wafer processing.
After the n-type doped silicon layer 104n is formed, selected portions thereof are ion implanted to form p-type doped regions 104p adjacent to n-type doped regions 104n. The interfaces between n-type regions 104n and p-type regions 104p are semiconductor junctions that support the ability of the thin film transistor to act as a switching device. By ion doping portions of semiconductor layer 104, one or more semiconductor junctions are formed, with an intrinsic electrical potential present across each junction.
A gate dielectric layer 108 is deposited on the n-type doped regions 104n and the p-type doped regions 104p. The gate dielectric layer 108 may comprise, for example, silicon dioxide (SiO2), silicon nitride (SiN), or silicon oxynitride (SiON), deposited using an embodiment of a PECVD system in accordance with this invention. In one embodiment, the gate dielectric layer 103 is a silicon dioxide (SiO2) layer, deposited using TEOS (tetraethylorthosilicate) and oxygen. TEOS is a liquid source precursor and can be vaporized to be carried into the process chamber. TEOS oxide film is known to have better comformality than silane oxide in the semiconductor industry.
A gate metal layer 110 is deposited on the gate dielectric layer 108. The gate metal layer 110 comprises an electrically conductive layer that controls the movement of charge carriers within the thin film transistor. The gate metal layer 110 may comprise a metal such as, for example, aluminum (Al), tungsten (W), chromium (Cr), tantalum (Ta), or combinations thereof, among others. The gate metal layer 110 may be formed using conventional deposition techniques. After deposition, the gate metal layer 110 is patterned to define gates using conventional lithography and etching techniques. After the gate metal layer 110 is formed, an interlayer dielectric 112 is formed thereon. The interlayer dielectric 112 may comprise, for example, an oxide such as silicon dioxide. Interlayer dielectric 112 may be formed using conventional deposition processes. The interlayer dielectric 112 is patterned to expose the n-type doped regions 104n. The patterned regions of the interlayer dielectric 112 are filled with a conductive material to form contacts 120. The contacts 120 may comprise a metal such as, for example, aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), indium tin oxide (ITO), zinc oxide (ZnO) and combinations thereof, among others. The contacts 120 may be formed using conventional deposition techniques.
Thereafter, a passivation layer 122 may be formed thereon in order to protect and encapsulate a completed thin film transistor 125. The passivation layer 122 is generally an insulator and may comprise, for example, silicon oxide or silicon nitride. The passivation layer 122 may be formed using conventional deposition techniques. While
A temperature controlled substrate support assembly 238 is centrally disposed within the processing chamber 202. The support assembly 238 supports a glass substrate 240 during processing. In one embodiment, the substrate support assembly 238 comprises an aluminum body 224 that encapsulates at least one embedded heater 232.
Generally, the support assembly 238 has a lower side 226 and an upper side 234. The upper side 234 supports the glass substrate 240. The lower side 226 has a stem 242 coupled thereto. The stem 242 couples the support assembly 238 to a lift system (not shown) that moves the support assembly 238 between an elevated processing position (as shown) and a lowered position that facilitates substrate transfer to and from the processing chamber 202. The stem 242 additionally provides a conduit for electrical and thermocouple leads between the support assembly 238 and other components of the system 200.
A bellows 246 is coupled between support assembly 238 (or the stem 242) and the bottom 208 of the processing chamber 202. The bellows 246 provides a vacuum seal between the chamber volume 212 and the atmosphere outside the processing chamber 202 while facilitating vertical movement of the support assembly 238.
The support assembly 238 generally is grounded such that RF power supplied by a power source 222 to a gas distribution plate assembly 218 positioned between the lid assembly 210 and substrate support assembly 238 (or other electrode positioned within or near the lid assembly of the chamber) may excite gases present in the process volume 212 between the support assembly 238 and the distribution plate assembly 218. The RF power from the power source 222 is generally selected commensurate with the size of the substrate to drive the chemical vapor deposition process. The precursor gas or gas mixture in the chamber is energized (e.g., excited) into a plasma by applying radio frequency (RF) power to the chamber from one or more RF sources coupled to the chamber. The excited gas or gas mixture reacts to form a layer of material on a surface of the substrate 240 that is positioned on a temperature controlled substrate support assembly 238.
The support assembly 238 additionally supports a circumscribing shadow frame 248. Generally, the shadow frame 248 prevents deposition at the edge of the glass substrate 240 and support assembly 238 so that the substrate does not stick to the support assembly 238. The support assembly 238 has a plurality of holes 228 disposed therethrough that accept a plurality of lift pins 250. The lift pins 250 are typically comprised of ceramic or anodized aluminum.
The lid assembly 210 provides an upper boundary to the process volume 212. The lid assembly 210 typically can be removed or opened to service the processing chamber 202. In one embodiment, the lid assembly 210 is fabricated from aluminum (Al). The lid assembly 210 includes a pumping plenum 214 formed therein coupled to an external pumping system (not shown). The pumping plenum 214 is utilized to channel gases and processing by-products uniformly from the process volume 212 and out of the processing chamber 202.
The lid assembly 210 typically includes an entry port 280 through which process gases provided by the gas source 204 are introduced into the processing chamber 202. The entry port 280 is also coupled to a cleaning source 282. The cleaning source 282 typically provides a cleaning agent, such as dissociated fluorine, that is introduced into the processing chamber 202 to remove deposition by-products and films from processing chamber hardware, including the gas distribution plate assembly 218.
The gas distribution plate assembly 218 is coupled to an interior side 220 of the lid assembly 210. The gas distribution plate assembly 218 is typically configured to substantially follow the profile of the glass substrate 240, for example, polygonal for large area flat panel substrates and circular for wafers. The gas distribution plate assembly 218 includes a perforated area 216 through which process and other gases supplied from the gas source 204 are delivered to the process volume 212. The perforated area 216 of the gas distribution plate assembly 218 is configured to provide uniform distribution of gases passing through the gas distribution plate assembly 218 into the processing volume 212.
The gas distribution plate assembly 218 typically includes a diffuser plate (or distribution plate) 258 suspended from a hanger plate 260. The diffuser plate 258 and hanger plate 260 may alternatively comprise a single unitary member. A plurality of gas passages 262 are formed through the diffuser plate 258 to allow a predetermined distribution of gas passing through the gas distribution plate assembly 218 and into the process volume 212. The hanger plate 260 maintains the diffuser plate 258 and the interior surface 220 of the lid assembly 210 in a spaced-apart relation, thus defining a plenum 264 therebetween. The plenum 264 allows gases flowing through the lid assembly 210 to uniformly distribute across the width of the diffuser plate 258 so that gas is provided uniformly above the center perforated area 216 and flows with a uniform distribution through the gas passages 262.
The flared openings 406 promote plasma ionization of process gases flowing into the processing region 212. Moreover, the flared openings 406 provide larger surface area for hollow cathode effect to enhance plasma discharge. In one embodiment, the diameter of the restrictive section 422 is 1.40 mm (or 0.055 inch). The length of the restrictive section 422 is 14.35 mm (or 0.565 inch). The conical opening 406 has a diameter of 7.67 mm (or 0.302 inch) on the second side 420 of the diffuser plate 258. The flaring angle of the flared opening 406 is 22 degree. The length of the flared opening is 16.13 mm (or 0.635 inch).
As the size of substrate continues to grow in the TFT-LCD industry, especially, when the substrate size is at least about 100 cm by about 100 cm (or about 10,000 cm2), film thickness uniformity value of some films becomes too large to meet the stringent requirement of some device manufacturers for large area plasma-enhanced chemical vapor deposition (PECVD). For example, gate dielectric thickness uniformity requirement is below 2-3% for some manufacturers and could not be achieved by the existing designs of gas distribution plates.
Therefore, there is a need for an improved gas distribution plate assembly that improves the control of film properties, such as film thickness uniformity.
Embodiments of a gas distribution plate for distributing gas in a processing chamber are provided. In one embodiment, a gas distribution plate assembly for a plasma processing chamber having a cover plate comprises a diffuser plate having an upstream side, a downstream side facing a processing region, and a plurality of gas passages formed through the diffuser plate, and a baffle plate, placed between the cover plate of the process chamber and the diffuser plate, having a plurality of holes extending from the upper surface to the lower surface of the baffle plate, wherein the plurality of holes have at least two sizes.
In another embodiment, a plasma processing chamber with a cover plate comprises a diffuser plate having an upstream side, a downstream side facing a processing region, and a plurality of gas passages formed through the diffuser plate, and a baffle plate, placed between the cover plate of the process chamber and the diffuser plate, having a plurality of holes extending from the upper surface to the lower surface of the baffle plate, wherein the plurality of holes have at least two sizes.
In another embodiment, a method of depositing a thin film on a substrate comprises placing a substrate in a process chamber having a cover and with a diffuser plate having an upstream side, a downstream side facing a processing region, and a plurality of gas passages formed through it, and a baffle plate, placed between the cover plate of the process chamber and the diffuser plate, having a plurality of holes extending from the upper surface to the lower surface of the baffle plate, wherein the plurality of holes have at least two sizes, flowing process gas(es) through the baffle plate and the diffuser plate toward a substrate supported on a substrate support, creating a plasma between the diffuser plate and the substrate support, and depositing a thin film on the substrate in the process chamber.
The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.
The invention generally provides a gas distribution assembly for providing gas delivery within a processing chamber. The invention is illustratively described below in reference to a plasma enhanced chemical vapor deposition system configured to process large area substrates, such as a plasma enhanced chemical vapor deposition (PECVD) system, available from AKT, a division of Applied Materials, Inc., Santa Clara, Calif. However, it should be understood that the invention has utility in other system configurations such as etch systems, other chemical vapor deposition systems and any other system in which distributing gas within a process chamber is desired, including those systems configured to process round substrates.
We have determined that the uniformity of reactive plasma distribution in the process chamber can be improved by adding a baffle plate 257 to the gas distribution plate assembly 218, as shown in
The holes 253 across the baffle plate 257 have more than one size. The holes 253 should distribute symmetrically across the baffle plate to increase the gas distribution uniformity. The holes 253 are typically cylindrical; however, other shapes of holes can also be used. Different sizes of holes could be placed across the baffle plate 257 symmetrically to control the gas distribution uniformity. In one embodiment, the baffle plate 257 has holes 253 with at least two sets of sizes, small pinholes and large holes. The small pinholes are needed to transport high-flow-rate gas mixture from upstream to downstream without building up pressure in the blocker plate upstream plenum 264. Building up pressure in the blocker plate upstream plenum 264 could result in recombination of reactive radicals, such as the fluorine radicals from the remote plasma clean source. Large holes are used to adjust the film deposition thickness uniformity and profile across the substrate. These large holes alone are not enough for high gas flow, such as flow rate >3000 sccm, to pass through. For example during remote plasma clean (RPS) clean, the cleaning gas flow rate is about 4000 sccm. Sufficient numbers of small pinholes would prevent the pressure build up in the block plate upstream plenum 264. The small pinholes could be all at one size or at more than one size. In one embodiment, the diameters of the small pinholes are kept below 1.27 mm (or 0.05 inch). The large holes could also be at one size or at more than one size. In one embodiment, the diameters of these the large holes are between about 1.59 mm (or 1/16 inch) to about 6.35 mm (or ¼ inch).
The total cross-sectional areas of the small pinholes should be kept to larger than 1 inch2 to ensure enough pass-through for the gas mixture, such as cleaning gas species generated by a RPS (remote plasma source) unit. In one embodiment, the diameters of the large holes are kept greater than 1.56 mm (or 1/16 inch).
The process of depositing a thin film in a process chamber is shown in
The distance between the baffle plate and the diffuser plate is 12.55 mm (or 0.494 inch). The thickness of the baffle plate is 1.37 mm (or 0.054 inch). The diffuser plate is similar to the one used for
The addition of the baffle plate does not appear to affect other TEOS oxide film properties. Table 1 compares stress, refractive index (RI), Si—O peak position, and wet etch rate.
The refractive index (RI), film stress, Si—O peak position data and wet etch rate (WER) data all show similar values for three types of baffle plates. The Si—O peak position is measured by FTIR (Fourier Transform Infrared Spectroscopy). Wet etch rate is measured by immersing the samples in a BOE (buffered oxide etch) 6:1 solution.
In addition to TEOS oxide film, the effect of the baffle plate on other types of dielectric film has also been investigated.
The results show that SiN film thickness across the substrate is not affected by the addition of a baffle plate with small pinholes and large holes such as the one used for depositing TEOS film in
The refractive index (RI), film stress, N—H/Si—H ratio data and wet etch rate (WER) data all show similar values for substrates deposited with or without a baffle plate with small pinholes and large holes as used in
The results show that using a baffle plate with small pinholes and large holes improves the TEOS oxide thickness uniformity and does not affect the other film properties of the TEOS film. The results also show that using the same baffle plate with small pinholes and large holes does not affect the film thickness uniformity and other film properties of SiN film. The difference could be due to the fact that TEOS is a liquid source and also has a higher molecular weight.
Gas distribution plates of gas distribution plate assembly that may be adapted to benefit from the invention described above are described in commonly assigned U.S. patent application Ser. No. 09/922,219, filed Aug. 8, 2001 by Keller et al., U.S. patent application Ser. No. 10/140,324, filed May 6, 2002 by Yim et al., and U.S. Ser. No. 10/337,483, filed Jan. 7, 2003 by Blonigan et al., U.S. Pat. No. 6,477,980, issued Nov. 12, 2002 to White et al., U.S. patent application Ser. No. 10/417,592, filed Apr. 16, 2003 by Choi et al., and U.S. patent application Ser. No. 10/823,347, filed on Apr. 12, 2004 by Choi et al., which are hereby incorporated by reference in their entireties.
Although the processes and examples used are for making thin film transistor devices, the concept of the invention can be used for making OLED application, solar panel substrates and other applicable devices.
Although several preferred embodiments which incorporate the teachings of the present invention have been shown and described in detail, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.