Patent Application
20240429096
The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to a gate cut of a self-aligned contact (SAC) post replacement metal gate (RMG).
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each device and each interconnect becomes increasingly significant.
Embodiments of the invention are directed to a semiconductor device. A non-limiting example of the semiconductor device includes gate regions interleaved between interlayer dielectric (ILD) regions, field effect transistor (FET) structures extending across the gate regions and the ILD regions, source and drain (S/D) regions, shared between the gate regions, at exterior ones of the ILD regions, dielectric material between the FET structures and bisecting the gate regions and the ILD regions, liner material and contacts. The liner material is disposed on opposite sides of the dielectric material in the gate regions and not in the ILD regions. The contacts are formed about the FET structures in the exterior ones of the ILD regions and across the dielectric material at an interior one of the ILD regions.
Embodiments of the present invention are directed to a method of semiconductor device fabrication. A non-limiting example of the method includes forming a self-aligned cap (SAC) over field effect transistor (FET) structures, patterning a gate cut etch mask for opening gates, spacers and interlayer dielectric (ILD) of the FET structures, etching material exposed by the gate cut etch mask to a depth deeper than a bottom of the gates to form an opening, forming an overhang of the gate cut etch mask over the ILD, depositing a liner material on sidewalls of the gates and the spacers but not on the ILD under the overhang in the opening, removing the gate cut etch mask and filling a remainder of the opening with dielectric material.
Embodiments of the present invention are directed to semiconductor device. A non-limiting example of the semiconductor device includes a substrate, which includes vertical fins and first dielectric material interposed between the vertical fins, field effect transistor (FET) structures on the vertical fins, first liner material disposed over the FET structures and side portions of the first dielectric material, interlayer dielectric (ILD) disposed on the first liner material, second dielectric material extending through the ILD and into the first dielectric material and columnar liner material interposed between the first dielectric material and the second dielectric material and between respective lower portions of the ILD and the second dielectric material.
Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings.
The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term “coupled” and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.
In the accompanying figures and following detailed description of the described embodiments, the various elements illustrated in the figures are provided with two or three digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.
For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, a post RMG gate cut process removes all exposed materials including those of a gate stack and interlayer dielectric (ILD). The cut area is then filled with a silicon nitride (SiN) liner followed by silicon dioxide (SiO2). It has been found, however, that some devices, such as static random access memory (SRAM) devices, require shared sources and drains (S/D). Hence, S/D contacts in these or other cases need to extend across the gate cut.
As gate pitch continues to get smaller over time, it is becoming difficult to do non-selective S/D contact etching. This is because such etching presents a shorting risk to the proximal gates. As such, a self-aligned contact (SAC) cap is typically formed on those proximal gates to prevent gate to S/D contact shorting event. Presently, selective S/D contact etching (so called SAC etching) is required but the SAC etching tends not to etch the SiN in gate cut (CT) regions.
It is therefore necessary to develop a structure and method to form CT SiN only in gate regions and not in ILD regions. This would allow for open S/D contact across CT regions.
Turning now to an overview of the aspects of the invention, one or more embodiments of the invention address the above-described shortcomings of the prior art by providing a method of semiconductor device fabrication an SAC cap is formed, a gate cut mask, which opens a gate, spacers and SiO2 ILD, is lithographically patterned, exposed material is etched to a depth deeper than a bottom of the gate, the SiO2 ILD is selectively etched to form an overhang of the mask over the remaining SiO2 ILD, an SiN liner is deposited on gate and spacer sidewalls but not on sidewalls of the SiO2 under the mask such that the SiN liner partially fills the opening made by the gate cut, the mask is removed and the remainder of the opening is filled with SiO2. This results in a semiconductor device structure having a metal gate, which is cut after formation of the SAC cap. The mask extends across the gate, the spacers and the ILD and the gate cut process removes all exposed material to a depth below the bottom of the gate. The cut region is filled with SiN liner and SiO2 gap fill material and the SiN liner is present only next to the gate and the spacer but not on the SiO2 ILD.
The above-described aspects of the invention address the shortcomings of the prior art by providing for a semiconductor device structure in which an SiN liner is not present next to the SiO2 ILD. This makes the post RMG gate cut compatible with SAC processing.
Turning now to a more detailed description of aspects of the present invention,
The semiconductor device 101 includes gate regions 110, 111, an interior ILD region 112, exterior ILD regions 113, 114 and spacers 115. The gate regions 110, 111 are interleaved between the interior ILD region 112 and the exterior ILD regions 113, 114. The spacers 115 are interleaved between the exterior ILD region 113 and the gate region 110, between the gate region 110 and the interior ILD region 112, between the interior ILD region 112 and the gate region 111 and between the gate region 111 and the exterior ILD region 114. The semiconductor device 101 further includes FET structures 116, 117 extending across the gate regions 110, 111, across the interior ILD region 112 and the exterior ILD regions 113, 114 and across the spacers 115 and S/D regions 118, 119 that are shared between the gate regions 110, 111 at the exterior ILD regions 113, 114. The FET structures 116, 117 can include or be provided as nanosheet stacks 1161, 1171 and can include RMG materials in the gate regions 110, 111 and epitaxy in the interior ILD region 112 and the exterior ILD regions 113, 114.
The semiconductor device 101 also includes dielectric material 120, liner material 121, first contacts 122, 123 and a second contact 124. The dielectric material 120 can include SiO2 or another similar material and extends between the FET structures 116, 117 and bisects each of the gate regions 110, 111, the interior ILD region 112, each of the exterior ILD regions 113, 114 and the spacers 115. The FET structure 116 can include or be provided as an n-doped FET (nFET) structure at a first side of the dielectric material 120 and the FET structure 117 can include or be provided as a p-doped FET (pFET) structure at a second side of the dielectric material 120. A width W1 of the dielectric material 120 bisecting the exterior ILD regions 113, 114 exceeds a width W2 of the dielectric material 120 bisecting the gate regions 110, 111. The liner material 121 can include SiN or another similar material and is disposed on opposite sides of the dielectric material 120 in the gate regions 110, 111 (and in the regions associated with the spacers 115) and not in the interior ILD region 112 or the exterior ILD regions 113, 114. The first contacts 122, 123 are formed about portions of the FET structures 116, 117 in the exterior ILD regions 113 and associated with the S/D regions 118, 119. The second contact 124 can be provided as a CT contact and extends across the dielectric material 120 at the interior ILD region 112.
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Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. Although various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings, persons skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functionality is maintained even though the orientation is changed. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include an indirect “connection” and a direct “connection.”
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The phrase “selective to,” such as, for example, “a first element selective to a second element,” means that the first element can be etched and the second element can act as an etch stop.
The terms “about,” “substantially,” “approximately,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.
The term “conformal” (e.g., a conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer.
The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which the semiconductor material being grown (crystalline overlayer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the source gases can be controlled and the system parameters can be set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. An epitaxially grown semiconductor material can have substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} orientated crystalline surface can take on a {100} orientation. In some embodiments of the invention, epitaxial growth and/or deposition processes can be selective to forming on semiconductor surface, and cannot deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.
As previously noted herein, for the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. By way of background, however, a more general description of the semiconductor device fabrication processes that can be utilized in implementing one or more embodiments of the present invention will now be provided. Although specific fabrication operations used in implementing one or more embodiments of the present invention can be individually known, the described combination of operations and/or resulting structures of the present invention are unique. Thus, the unique combination of the operations described in connection with the fabrication of a semiconductor device according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.
In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators and selectively doped regions are built up to form the final device.
The flowchart and block diagrams in the Figures illustrate possible implementations of fabrication and/or operation methods according to various embodiments of the present invention. Various functions/operations of the method are represented in the flow diagram by blocks. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the Figures. For example, two blocks shown in succession can, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.
