Claims
- 1. A method for fabricating a gate device, comprising:
forming an elongated projection on a substrate, the elongated projection protruding from a surrounding area of the substrate and including an access channel for the gate device; forming a first terminal and a second terminal coupled to the access channel in the elongated projection; and forming a gate structure operable to control the access channel to selectively couple the first terminal to the second terminal.
- 2. The method of claim 1, wherein the elongated projection comprises substrate material and is formed by patterning and etching the substrate.
- 3. The method of claim 1, wherein the gate structure is disposed over the first and second terminals and the access channel.
- 4. The method of claim 1, wherein the gate structure is disposed over the access channel between the first and second terminals.
- 5. The method of claim 1, wherein the first and second terminals are formed in the elongated projection.
- 6. A method for fabricating a memory cell, comprising:
forming an elongated projection on a substrate, the elongated projection protruding from a surrounding area of the substrate and including an access channel for the memory cell; forming a first terminal and a second terminal coupled to the access channel in the elongated projection; forming a storage node coupled to the first terminal for the memory cell; forming a bit line coupled to the second terminal for the memory cell; and forming a gate structure operable to control the access channel to selectively couple the bit line to the storage node.
- 7. The method of claim 6, wherein the elongated projection comprises substrate material and is formed by patterning and etching the substrate.
- 8. The method of claim 6, wherein the first and second terminals are formed within the elongated projection.
- 9. The method of claim 8, wherein the first terminal is formed at a first edge of the elongated projection and the second terminal is formed at a second, opposite edge of the elongated projection.
- 10. The method of claim 9, wherein the first and second terminals are formed by doping portions of the first and second edges of the elongated projection.
- 11. The method of claim 6, wherein the first and second terminals are formed adjacent to the elongated projection.
- 12. The method of claim 11, wherein the first terminal is formed adjacent to a first edge of the elongated projection and the second terminal is formed adjacent to a second, opposite edge of the elongated projection.
- 13. The method of claim 12, wherein the terminals are formed by depositing a conductive layer adjacent to the elongated projection and removing an excess portion of the conductive layer to isolate a first remaining portion of the conductive layer as the first terminal and to isolate a second remaining portion of the conductive layer as the second terminal.
- 14. The nethod for fabricating a memory array, comprising:
forming a plurality of elongated projections on a substrate, the elongated projections each protruding from a surrounding area of the substrate and including an access channel for each of a plurality of memory cells; forming a first terminal and a second terminal for each memory cell, the first and second terminals coupled to the access channel for the memory cell; forming a storage node for each memory cell, the storage node coupled to the first terminal for the memory cell; forming a bit line structure for each memory cell, the bit line structure coupled to the second terminal for the memory cell; and forming a gate structure for each memory cell, the gate structure operable to control the access channel to selectively couple the bit line to the storage node.
- 15. The method of claim 14, wherein the elongated projection comprises substrate material and is formed by patterning and etching the substrate.
- 16. The method of claim 14, wherein the first and second terminals are formed within the elongated projection.
- 17. The method of claim 16, wherein the first terminal is formed at a first edge of the elongated projection and the second terminal is formed at a second, opposite edge of the elongated projection.
- 18. The method of claim 17, wherein the first and second terminals are formed by doping portions of the first and second edges of the elongated projection.
- 19. The method of claim 14, wherein the first and second terminals are formed adjacent to the elongated projection.
- 20. The method of claim 19, wherein the first terminal is formed adjacent to a first edge of the elongated projection and the second terminal is formed adjacent to a second, opposite edge of the elongated projection.
- 21. The method of claim 20, wherein the first and second terminals for the memory cells are formed by depositing a conductive layer adjacent to the elongated projections and removing an excess portion of the conductive layer to isolate a first remaining portion of the conductive layer as the first terminals and to isolate a second remaining portion of the conductive layer as the second terminals.
RELATED APPLICATION
[0001] This application is related to copending U.S. application Ser. No.______, entitled “Gate Device with Access Channel Formed in Discrete Post and Method” (Attorney's Docket No.______ TI-28216 and copending U.S. application Ser. No. , entitled “Method for Two-Sided Fabrication of a Memory Array” (Attorney's Docket No. TI-23232).
Provisional Applications (1)
|
Number |
Date |
Country |
|
60102359 |
Sep 1998 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
09405737 |
Sep 1999 |
US |
Child |
10001441 |
Oct 2001 |
US |