Patent Application
20150262905
The invention relates, in general, to a cooling apparatus and, more specifically, to an apparatus for cooling electronic devices, and to a method of manufacturing the apparatus.
This section introduces aspects that may help facilitate a better understanding of the inventions. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Active electronic, optical or other device components can generate heat, and the heat is dissipated so that the components can operate at a desired temperature and/or so that the components will continue to operate over a desired lifetime. An inability to adequately dissipate the internally generated heat can limit capacities and/or functionalities of such components and/or can result in the premature failure of such components. For example, thermal dissipation limitations have impacted computer chips and their design and architecture.
One embodiment is an apparatus. The apparatus comprises an integrated circuit, the integrated circuit comprises a substrate having a planar surface, a plurality of active electronic and/or optical devices located over the planar surface in the integrated circuit, and, a planar channel having a hollow interior and being located between the active electronic and/or optical devices, and the substrate. A portion of a segment of the planar channel is formed of metal or graphene.
In any such embodiments, the portion can form a top surface or a bottom surface of the segment of the planar channel.
In any such embodiments, the portion can form between 25 percent and 75 percent of a surface of a cross section of the segment of the planar channel.
In any such embodiments, the integrated circuit can include a second substrate and the interior of the planar channel is located between the substrates.
In any such embodiments, the portion can be connected to a ground body of the integrated circuit.
In any such embodiments, can further comprise a pump connected to move a liquid through the channel.
In any such embodiments, can further comprise a heat exchanger configured to receive fluid from the channel and being located external to the integrated circuit.
In any such embodiments, can further comprise a pump connected to move the fluid through the channel and from the channel to the heat exchanger.
Another embodiment is method that comprises forming an integrated circuit. Forming the integrated circuit includes providing a substrate having a planar surface, forming a plurality of active electronic and/or optical devices located over the planar surface in the integrated circuit, and, forming a planar channel having a hollow interior and being located between the active electronic and/or optical devices, and the substrate, wherein a portion of a segment the planar channel is formed of metal or graphene.
In any such embodiments, forming the integrated circuit can further include providing a second substrate 107a and the interior of the planar channel is located between the substrates.
In any such embodiments, forming the integrated circuit can further include forming a metal and/or doped semiconductor path connecting the portion to a surface of the substrate.
In any such embodiments, forming the integrated circuit can further include forming a ground body and connecting the portion the ground body.
Any such embodiments can further include connecting a pump configured to move a liquid through the channel.
Any such embodiments can further include providing a heat exchanger configured to receive fluid from the channel and being located external to the integrated circuit.
Some such embodiments can further include connecting a pump to move the fluid through the channel and from the channel to the heat exchanger.
Another embodiment is an apparatus comprising an integrated circuit having a substrate with at least one heat-generating component thereon, a channel located adjacent to the substrate and in a vicinity of the at least one of the heat-generating component, wherein the channel is configured to carry a dielectric fluid there-through; and a grounding system. The grounding system includes an electrically conductive layer located on at least one wall of the channel and configured to electrically connect to the dielectric fluid in the channel. The grounding system includes a ground body adjacent to the substrate, and one or more ground-path structures located in the substrate and electrically connecting the electrically conductive layer to the ground body.
In some such embodiments, at least a segment of the electrically conductive layer, located on the at least one wall of the channel and configured to electrically connect to the dielectric fluid in the channel, is formed of graphene. In some such embodiments, at least a portion of the ground-path structure includes a structure that traverses the channel and contacts the he dielectric fluid in the channel. In some such embodiments, the structure traversing the channel is a via structure that passes through the substrate and contacts the ground body.
The embodiments of the disclosure are best understood from the following detailed description, when read with the accompanying FIGUREs. Some features in the figures may be described as, for example, “top,” “bottom,” “vertical” or “lateral” for convenience in referring to those features. Such descriptions do not limit the orientation of such features with respect to the natural horizon or gravity. Various features may not be drawn to scale and may be arbitrarily increased or reduced in size for clarity of discussion. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
In the Figures and text, similar or like reference symbols indicate elements with similar or the same functions and/or structures.
In the Figures, the relative dimensions of some features may be exaggerated to more clearly illustrate one or more of the structures or features therein.
Herein, various embodiments are described more fully by the Figures and the Detailed Description. Nevertheless, the inventions may be embodied in various forms and are not limited to the embodiments described in the Figures and Detailed Description of Illustrative Embodiments.
The description and drawings merely illustrate the principles of the inventions. It will thus be appreciated that those skilled in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the inventions and are included within its scope. Furthermore, all examples recited herein are principally intended expressly to be for pedagogical purposes to aid the reader in understanding the principles of the inventions and concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the inventions, as well as specific examples thereof, are intended to encompass equivalents thereof. Additionally, the term, “or,” as used herein, refers to a non-exclusive or, unless otherwise indicated. Also, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
Embodiments of the disclosure can facilitate the use of inter- or intra-component embedded cooling systems, where a dielectric cooling fluid is circulated within or in a vicinity of one or more heat-generating device components. Providing an electrical grounding system connected to a channel circulating the dielectric fluid helps prevent the accumulation of an electrical charge (e.g., tribological charging), and thereby avoid detrimental effects associated with charge accumulation.
The term “dielectric fluid,” as used herein, refers to a fluid having electrical insulating properties and cooling properties, e.g., a dielectric liquid. Example dielectric fluids include, but are not limited to, fire-resistant and/or non-flammable fluids such as pure water (e.g., deionized or distilled liquid water) or fluorine containing refrigerants (e.g., R134a, R22, FC77 refrigerants). Non-limiting example dielectric fluids that are not fire-resistance and are flammable include hydrocarbons such as n-butane or n-pentane. In some embodiments, the dielectric fluid has a dielectric constant or relative permittivity of at least about 50, and, in some embodiments, at least about 100. In some embodiments, the dielectric fluid has a dielectric constant or relative permittivity of at least about 50, and in some embodiments, at least about 100 (at standard condition of 1 atmosphere and 20° C.). In some embodiments, the dielectric fluid has an electrical conductivity of less than about 100E-6 S/m and in some cases less than about 5×10−6 S/m (at standard conditions). In some embodiments, to facilitate heat absorption a dielectric fluid is selected that changes phase from liquid to vapor when absorbing heat from the heat-generating component. That is the dielectric fluid is a two-phase dielectric fluid. In some embodiments, the dielectric fluid is a single (e.g., liquid) phase dielectric fluid, where the sensible heat rise of the liquid absorbs heat from the heat-generating component. In some embodiments, the dielectric fluid heat absorption occurs via both the sensible heat rise (single phase) and the liquid-to-vapor phase change (two-phase) when absorbing heat from the heat-generating component.
Tribological charging refers to the formation of a static electrical charge when a dielectric fluid flows within an electrically-insulating channel at a sufficiently high mass flow rate. One skilled in the pertinent arts would be familiar with conditions where a dielectric fluid can undergo static electric charging (e.g., tribological charging). In some embodiments, the static tribological charge can accumulate on walls of a channel until it reaches a level whereby it can overcome the electrical resistance to ground. The sudden discharge of such a static electric charge can cause damage to the device component or cause the device component to malfunction.
As part of the present disclosure, it was recognized that locating grounding pathways of an electrical grounding system in the vicinity of heat-generating device components being cooled by a dielectric fluid can beneficially reduce the formation of local tribological static charges. It was also recognized that providing a grounding path system in the vicinity of device components helps to mitigate the accumulation of relatively small static electric charges that may not be sufficient to damage the components, but nevertheless may cause the components to malfunction.
For example, for a large resistance to ground, significant levels of charge can develop (e.g., greater than about 10 kV and in some example), and, sudden discharge can lead to the creation of pin hole defects in the channel walls as a discharge arcs through the channel walls to ground. For example, for device components of integrated circuits, even a small local build-up of a tribological static charge (e.g., less than 1 kV or less than 100 V, or less than 10 V, or less than 1 V in some embodiments) may be sufficient to cause electric arcing over the short distances of conductors carrying electrical signals in the circuit and may this create physical defects or malfunctions in device components. The presence of a small local static charge may be sufficient to alter the normal function of device components. For instance, the presence of a static charge in the vicinity of a transistor component of an integrated circuit chip may alter the electric potential between a source, drain or gate of the transistor, and thus may alter the operation of the transistor. Or, the presence of a static charge could alter the information traveling through an electrical interconnection between transistors or between transistors and memory components (e.g., SRAM or DRAM components) of a device. Or, the presence of a static charge could alter the impedance along the interconnection between device components.
One embodiment of the disclosure is an apparatus.
As illustrated the apparatus 100, comprises an integrated circuit 105. The integrated circuit 105 comprises a substrate 107a having a planar surface 108a and a plurality of active electronic and/or optical devices 110 located over the planar surface 108a in the integrated circuit 105. The integrated circuit 105 also comprises a planar channel 115 having a hollow interior 115a and being located between the active electronic and/or optical devices 110, and the substrate 107a. A portion 122 of a segment 116 of the planar channel 115 is formed of metal or graphene.
In some embodiments, as illustrated in
It is thought that, at least in some embodiments, accumulated charges will have difficulty in migrating through a dielectric fluid 117 in the channel 115 and therefore surface charges preferably pass very close to the graphene or metal portion 122 to be charge-dissipated. Therefore, in some embodiments, to facilitate the removal of charge, it is preferred that a large percentage of the segment 116 be composed of the graphene or metal portion 122. In some embodiments, for example, the portion 122 forms between 25 percent and 75 percent of a surface, e.g., surface 116a or 116b, of a cross section of the segment 116 of the planar channel 115. In some embodiments as illustrated in
As further illustrated in
As further illustrated in
To facilitate charge dissipation, the portion 122 can be connected to a ground body 126 of the integrated circuit 105. For instance, in some embodiments, the metal and/or doped semiconductor path 130 can connect the portion 122 to the ground body 126. In some embodiments, the ground body 126 can be located between the active devices 110 and the channel 115 and may act to electrically shield the active devices 110 against such arcing. In other embodiments, the ground body 126 can be located on a side of the substrate 107b that is opposite the side of the substrate 107a that the active devices 110 are located on, to avoid having dissipating static charge accumulating near regions of the circuit 105, where such charge could interfere with the operation of the devices 110. In some embodiments, to further facilitate charge dissipation, the portion 122 can be connected to a ground body 126 or multiple ground bodies at regular intervals, e.g., via multiple paths 130.
Using similar reference numbers to depict similar features,
Some embodiments of the apparatus 100 such as depicted in
The term integrated circuit as used herein refers to any physically integrated device having a plurality of active electronic and/or active optical components, e.g., transistor(s), light-emitting diode(s), optical amplifier(s), and/or laser(s) integrated onto a solid substrate. For example, the integrated circuit 105 can include a portion of a single integrated circuit die or chip having electronic or optical components 110, 112 capable of generating heat during operation. One of ordinary skill in the pertinent art would understand that an active device is a device that is capable of adjustably controlling the flow or charge carriers and requiring a separate power source (e.g., a non-signal power source) to perform its function. Non-limiting example electrical active devices include field effect transistor devices such as NMOS, PMOS, CMOS transistors; memory devices such as SRAM, DRAM, EEPROM. One of ordinary skill would understand how active and passive device components can be fabricated on or in a semiconductor substrate or other solid substrate 107 to form an integrated circuit. In some embodiments, for example, the integrated circuit 105 can include an assembly of such electronic integrated circuits. In some embodiments, for example, the integrated circuit 105 can include one or more photonic integrated circuits having heat-generating components 110, 112 such as one or more lasers, thermo-optic and/or electro-optic phase shifters, optical amplifiers or other components familiar to those skilled in the relevant arts. In some embodiments, for example, the integrated circuit 105 can include an assembly of both active electronic and active photonic components on the same integrated circuit (e.g., an optoelectronic circuit). In still other embodiments, the integrated circuit can be or include a radio frequency monolithic microwave integrated circuit.
In some embodiments, at least one of the ground-path structures (e.g., structure 130) can be or include a via that, for example, passes through at least a portion of a thickness 134 of the substrate 110. For instance, in some embodiments, the via 130 can be or include a copper or tungsten plug and surrounding barrier layer as familiar to those skilled in the art. In some embodiments, at least one of the ground-path structures (e.g., structure 132) can be or include a through-substrate fully or partially metal-filled via. In some embodiments, the through-substrate via 132 can span the entire thickness 134 of the substrate 107, or in some embodiments, a plurality of substrates. In some such embodiments, a portion of the through-substrate via 132 may be open into or pass through the channel 115 and directly contact the dielectric fluid 117 to thereby provide a further a low resistance ground path, e.g., metal path, for the discharge of electrical charges carried on the moving dielectric fluid.
In some embodiments, to facilitate the electrical connection and reduce the potential for electric charge build-up, the ground-path structure 130, 132, can directly contact both the electrically conductive layer 122 and the ground body 126. For instance, in some embodiments, one end 136 of the ground path structure 130 can contact the electrically conductive layer 122 and the opposite end 138 of the structure 130 can contact the ground body 126.
In some embodiments, to facilitate the electrical connection and reduce the potential for electric charge build-up, at least a portion (e.g., side 140 of conductive layer 122 in
In some embodiments, to facilitate a low resistance grounding path with high electrical conductivity, at least one electrically conductive layer 122 can be a metal layer, for example copper, tungsten, silver, a metal alloy or other conductor (e.g., doped or heavily doped semiconductor, graphene, or a doped carbon nanotube dispersion) familiar to those skilled in the pertinent arts.
In some embodiments, to improve the flow of the dielectric fluid 117 flowing through the channel 115, the electrically conductive layer 122 can be embedded in a wall (e.g., wall 124) of the channel. For instance, in some embodiments, a conductive layer 122 can be formed in a trench 142 of a channel wall (e.g., wall 124). In some embodiments, the side 140 of layer 122 faces the fluid 117 and is flush with adjacent other surfaces 144 of the wall 122 thereby reducing the flow resistance of the dielectric fluid 117 flowing through the channel 115 as compared to embodiments without such a flush construction of different portions of the surfaces of the channel 115.
In some embodiments, the conductive layer 122 can be buried in the channel wall 124 so as to not directly contact the dielectric fluid 117. In some such embodiments, a doped semiconductor portion 146 (e.g., an N-type or P-type doped semiconductor portion) of the substrate 107 can electrically connect at least one of the layers 122 (e.g., a metal, doped or heavily doped semiconductor, graphene, or a dispersion of doped carbon nanotubes) to the dielectric fluid 117. Then, the doped semiconductor portion 146 of the substrate 107 can be located between the electrically conductive layer 122 and the dielectric fluid 117 and contacts both of the layer 122 and the moving fluid 117 during operation.
In some embodiments, to facilitate a low resistance grounding path, at least one electrically conductive layer 122 can be or include a portion 148 of the substrate 107 that is doped semiconductor (e.g., doped with N-type or P-type dopants). In some embodiments, forming electrically conductive layers 122 as a doped portion of the substrate 107 can facilitate fabrication of the grounding system 120 by avoiding the need to form, e.g., a metal conductive layer 122 on or in the channel wall 124. Additionally, in some embodiments, the doped portion 148 of the substrate 107 can be flush with the other portions 144 and thereby facilitate the flow of the fluid 117 through the channel 115. However, doped semiconductor may have decreased thermal conductivity with respect to some metals and metal alloys, and therefore a metal conductive layer 122 may be preferred in some embodiments. Alternatively charge-dopant types may be selected to increase electrical conductivity of the layer 122 without decreasing thermal conductivity.
In some embodiments, at least one of the low resistance ground-path structures (e.g., structure 150) can be or include a portion 148 of the substrate 107 that is doped, for example, with N-type (e.g., silicon doped with P or As atoms) or P-type (e.g., silicon doped with B atoms) dopants. In some embodiments, forming the ground-path structures 150 as heavily doped semiconductor portions of the substrate 107 can facilitate fabrication of the grounding system 120 by avoiding the need to form, e.g., a metal ground-path structure.
As illustrated in
In some embodiments, as illustrated in
In some embodiments, as illustrated in
In some embodiments, the substrate 107 can be or include silicon, silicon-on-insulator, silicon carbide, diamond or other semiconductor or ceramic material layers. In some embodiments, the heat generating active device components 110, 112 can each be or include one or more integrated circuits. For example, in some embodiments, the heat generating active device components 110, 112 configured as one or more integrated circuits can include electronic integrated circuit 110, photonic integrated circuit 112, or hybrid combinations of such circuits on a common substrate 107. Embodiments of the heat generating active device components 110, 112, can include active electronic and/or optical components, or passive components which internally generate heat. For instance, the integrated circuit 105 include heat generating active device components 110, 112 each configured as a plurality of integrated circuit chips mounted on a circuit board substrate 107, and such integrated circuit chips can be interconnected in a parallel array to form a multicore central processing unit.
Returning to
As illustrated in
In some embodiments, to reduce possible interference with heat transfer from the heat generating active device components 110, 112 to the fluid 117, the side 140 of the electrically conductive layer 122 facing the fluid 117 occupies is about 10 percent or less, and in some embodiments, about 1 percent or less, of a total surface area of the wall 124 of the channel 115 that the layer 122 is located on. In some embodiments as illustrated in
As illustrated in
In still other embodiments, to facilitate providing multiple paths to ground along the channel 115, there can be a plurality of conductive layers 122 each located on multiple different walls 124, 156 of the channel 115, with each of the layers 122 being connected to one of the ground-path structures (e.g., at least one of structures 130, 132).
As further illustrated in
Based upon the disclosure one skilled in the pertinent art would appreciate how more than two integrated circuits 105, 305 could be stacked together with at least one channel 115 and one grounding system 120 being located between adjacent pairs of integrated circuits 105, 305.
One skilled in the pertinent art would appreciate how, in some embodiments, the two or more integrated circuits 105, 305 on different substrates 107, 307 can be interconnected with each other to form to form a three dimensional multi-core central processing unit.
Returning to
Another embodiment of the disclosure is a method.
In some embodiments, forming the integrated circuit 105 (step 405) further includes a step 417 of providing a second substrate 107a wherein the interior 116 of the planar channel 115 is located between the substrates 107a, 107b.
In some embodiments, forming the integrated circuit 105 (step 405) further includes a step 420 of forming a metal and/or doped semiconductor path 130 connecting the portion to a surface (e.g., surface 108a or 108b) of the substrate (e.g., substrate 107a or 107b).
In some embodiments, forming the integrated circuit 105 (step 405) further includes a step 422 of forming a ground body 126 and connecting the portion 122 to the ground body 126.
Some embodiments of the method further include a step 430 of connecting a pump 170 configured to move a liquid 117 through the channel 115. Some embodiments of the method further include a step 435 of providing a heat exchanger 175 configured to receive fluid 117 from the channel 115 and being located external to the integrated circuit 105. In some cases, connecting the pump 170 in step 430 includes moving the fluid 117 through the channel 115 and from the channel 115 to the heat exchanger 175.
Another embodiment of a method of manufacturing an apparatus is illustrated in the flow diagram presented in
Embodiments of the method of manufacturing the apparatus 100 can comprise a step 515 of forming a grounding system 120. Forming the grounding system 120 (step 515) can include a step 520 of forming an electrical conductive layer 122 located on at least one wall 124 of the channel 115 and configured to electrically connect to the dielectric fluid 117 in the channel 115. Forming the grounding systems 120 (step 515) can include a step 525 of forming a low-resistance ground body 126 adjacent to the substrate 107. Forming the grounding systems 120 (step 515) can include a step 530 of forming one or more low resistance ground-path structures (e.g., one or more of structure 130 or structure 132) located in the substrate 107 and electrically connecting the electrically conductive layer 122 to the ground body 126.
In some embodiments of the method of manufacturing the apparatus 100, forming the channel (step 510) can includes forming a gap between a first portion 160 of the substrate 107 and a second portion 162 of the substrate 107, such that the gap can include or be the channel 115 (see e.g.,
In some embodiments, forming the electrically conductive layer 122 (step 520) includes forming a metal or graphene or carbon nanotube or other material layer on one side 140 of the substrate (e.g., substrate portion 162), e.g. prior to coupling two substrates 107, 307 together as part of step 510. One skilled in the art would be familiar with material deposition procedures (e.g., electroless or electrolytic deposition, chemical or physical deposition) to form the layer 122
In some embodiments, forming the electrically conductive layer (step 520) include doping a portion 148 of one side 140 of the substrate 107 with N-type or P-type dopants. One skilled in the pertinent art would be familiar with dopant implantation and thermal annealing procedures to form the doped portion 148.
In some embodiments, forming the electrically conductive layer 122 (step 520) includes embedding the layer in the side 140 of the substrate 107. For instance, in some embodiments a trench 142 can be formed in the substrate (e.g., by lithographic patterning and etching procedures) and a material layer 122 deposited in the trench 142.
In some embodiments, forming the ground body 126 adjacent to the substrate 107 (step 525) includes depositing a conductive material layer (e.g., a metal or graphene layer or carbon nanotube dispersion layer) at or near a top-side 215 or a bottom side 220 of the substrate 107 (
In some embodiments, forming the low-resistance ground-path structure 130, 132 (step 530) includes forming a metal-containing via that passes through at least a portion of a thickness 134 of the substrate 107 (
Although the present disclosure has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the scope of the invention.
The U.S. Government has a paid up license related to the subject matter of this application and may have the right in limited circumstances to require the patent owner to license others on reasonable terms as provided for by the terms of Contract No. HR0011-13-2-0009 awarded by DARPA under Sub-award No. 5710003438.
