I. Definition
As used herein, “III-Nitride” or “III-N” refers to a compound semiconductor that includes nitrogen and at least one group III element such as aluminum (Al), gallium (Ga), indium (In), and boron (B), and including but not limited to any of its alloys, such as aluminum gallium nitride (AlxGa(1-x)), indium gallium nitride (InyGa(1-y)N), aluminum indium gallium nitride (AlxInyGa(1-x-y)N), gallium arsenide phosphide nitride (GaAsaPbN(1-a-b)), aluminum indium gallium arsenide phosphide nitride (AlxInyGa(1-x-y)AsaPbN(1-a-b)), for example. III-N also refers generally to any polarity including but not limited to Ga-polar, N-polar, semi-polar, or non-polar crystal orientations. A III-N material may also include either the Wurtzitic, Zincblende, or mixed polytypes, and may include single-crystal, monocrystalline, polycrystalline, or amorphous structures. Gallium nitride or GaN, as used herein, refers to a III-N compound semiconductor wherein the group III element or elements include some or a substantial amount of gallium, but may also include other group III elements in addition to gallium. A III-N or a GaN transistor may also refer to a composite high voltage enhancement mode transistor that is formed by connecting the III-N or the GaN transistor in cascade with a lower voltage group IV transistor.
In addition, as used herein, the phrase “group IV” refers to a semiconductor that includes at least one group IV element such as silicon (Si), germanium (Ge), and carbon (C), and may also include compound semiconductors such as silicon germanium (SiGe) and silicon carbide (SiC), for example. Group IV also refers to semiconductor materials which include more than one layer of group IV elements, or doping of group IV elements to produce strained group IV materials, and may also include group IV based composite substrates such as single-crystal or polycrystalline SiC on silicon, silicon on insulator (SOI), separation by implantation of oxygen (SIMOX) process substrates, and silicon on sapphire (SOS), for example.
It is noted that, as used herein, the terms “low voltage” or “LV” in reference to a transistor or switch describes a transistor or switch with a voltage range of up to approximately fifty volts (50V). It is further noted that use of the term “midvoltage” or “MV” refers to a voltage range from approximately fifty volts to approximately two hundred volts (approximately 50V to 200V). Moreover, the term “high voltage” or “HV,” as used herein, refers to a voltage range from approximately two hundred volts to approximately twelve hundred volts (approximately 200V to 1200V), or higher.
II. Background Art
Group III-V heterostructure field-effect transistors (HFETs), such as gallium nitride (GaN) or other III-Nitride based high mobility electron transistors (HEMTs), may be desirable for use in high power and high performance circuit applications due to their high efficiency and high-voltage capability. III-Nitride and other group III-V HEMTs operate using polarization fields to generate a two-dimensional electron gas (2DEG) allowing for high current densities with low resistive losses. Because the 2DEG can arise naturally near the interface of a III-Nitride channel layer and an overlying III-Nitride barrier layer having a larger bandgap than the channel layer, III-Nitride HEMTS typically conduct without the application of a gate potential.
In some implementations, it may be advantageous or desirable to implement a buffer layer underlying the III-Nitride channel and barrier layers using a III-Nitride material also having a larger bandgap than the channel layer. For example, use of a larger bandgap buffer layer under the channel layer may reduce the conductivity of the buffer layer, thereby reducing leakage current through the HEMT. However, such an implementation may undesirably result in a naturally arising secondary 2DEG at the interface of the channel layer and the underlying buffer layer having the larger bandgap.
The present disclosure is directed to a group III-V device including a buffer termination body, substantially as shown in and/or described in connection with at least one of the figures, and as set forth more completely in the claims.
The following description contains specific information pertaining to implementations in the present disclosure. One skilled in the art will recognize that the present disclosure may be implemented in a manner different from that specifically discussed herein. The drawings in the present application and their accompanying detailed description are directed to merely exemplary implementations. Unless noted otherwise, like or corresponding elements among the figures may be indicated by like or corresponding reference numerals. Moreover, the drawings and illustrations in the present application are generally not to scale, and are not intended to correspond to actual relative dimensions.
As illustrated by
The present application is directed to group III-V heterostructure field-effect transistors (HFETs), such as III-Nitride or other group III-V HEMTs, configured to reduce or substantially suppress formation of an undesirable secondary 2DEG, or an undesirable 2DHG, corresponding to secondary 2DEG 119, in
Referring to
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It is noted that the structures shown in
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In one implementation, transition body 322 may include a nucleation layer (nucleation layer not shown in
Examples of using a compositionally graded transition body, as well as use of intermediate layers, stress reducing layers, and various interlayers are disclosed in U.S. Pat. No. 6,649,287, entitled “Gallium Nitride Materials and Methods”, and issued on Nov. 18, 2003; U.S. Pat. No. 6,617,060, also entitled “Gallium Nitride Materials and Methods”, and issued on Sep. 9, 2003; U.S. Pat. No. 7,339,205, entitled “Gallium Nitride Materials and Methods Associated with the Same”, and issued on Mar. 4, 2008; U.S. patent application Ser. No. 12/928,946, entitled “Stress Modulated Group III-V Semiconductor Device and Related Method”, and filed on Dec. 21, 2010; U.S. patent application Ser. No. 13/397,190, entitled “III-Nitride Heterojunction Devices Having a Multilayer Spacer”, and filed on Feb. 15, 2012; and U.S. patent application Ser. No. 11/531,508, entitled “Process for Manufacture of Super Lattice Using Alternating High and Low Temperature Layers to Block Parasitic Current Path”, and filed on Sep. 13, 2006; and U.S. patent application Ser. No. 13/405,180, entitled “III-Nitride Semiconductor Structures with Strain Absorbing Interlayer Transition Modules”, and filed on Feb. 24, 2012. The above-referenced patents and patent applications are hereby incorporated fully by reference into the present application.
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In one implementation, AlGaN buffer termination body 342 may take the form of a single AlGaN layer of substantially uniform composition. However, in other implementations, AlGaN buffer termination body 342 may be formed as a compositionally graded layer, such as a compositionally graded AlGaN or other III-Nitride or group III-V layer having a smaller bandgap at top surface 347 and a larger bandgap at bottom surface 343. For example, in implementations in which the buffer termination body is formed of AlGaN, as depicted in
Referring to
In some implementations, as shown in
In some implementations, it may be advantageous or desirable to include one or more impurity graded layers in AlGaN buffer termination body 342 of either or both of structures 340-1 and 340-2 and/or AlGaN buffer layer(s) 332. Examples of impurity graded layers are disclosed in U.S. Pat. No. 8,796,738, entitled “Group III-V Device Structure Having a Selectively Reduced Impurity Concentration”, and issued on Aug. 5, 2014. This patent is hereby incorporated fully by reference into the present application.
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It is noted that in certain implementations, it may be desirable to form AlGaN barrier layer 356 over a spacer layer (or layers) disposed between AlGaN barrier layer 356 and GaN channel layer 354. Examples of using such spacer layer(s) are disclosed in U.S. Pat. No. 8,659,030, entitled “III-Nitride Heterojunction Devices Having a Multilayer Spacer”, and issued on Feb. 25, 2014. This patent is hereby incorporated fully by reference into the present application. Moreover, in some implementations, it may be advantageous or desirable to use a thin layer of AlN or high Al content AlGaN in conjunction with AlGaN barrier layer 356 to aid in confinement of 2DEG 355.
Channel layer 354 and barrier layer 356 are depicted as respective GaN and AlGaN layers for exemplary purposes only. More generally, channel layer 354 and barrier layer 356 can be implemented using any suitable III-Nitride or other group III-V layers for which barrier layer 356 has a bandgap sufficiently larger than the bandgap of channel layer 354 to produce 2DEG 355. In addition, and to reduce or substantially suppress an undesirable secondary 2DEG, or an undesirable 2DHG, from forming in heterostructure 352, buffer termination body 342 is situated between buffer layer 332 and channel layer 354, and has a bandgap smaller than the bandgap of buffer layer 332 and larger than the bandgap of channel layer 354.
For example, in implementations in which channel layer 354 takes the form of a GaN channel layer including substantially no aluminum, leakage in buffer layer 332 may be advantageously reduced when buffer layer 332 is implemented as an AlGaN buffer layer having an aluminum concentration of approximately four percent (4%), or greater. In such an implementation, buffer termination body 342 may be a compositionally graded AlGaN layer having an aluminum concentration of approximately 1% or less at top surface 347 and an aluminum concentration of from approximately 2% to approximately 4% at bottom surface 343.
It is noted that, as used herein, the expression “substantially suppress an undesirable secondary 2DEG” refers to the fact although a secondary 2DEG, or a 2DHG, may appear at or near the interface of channel layer 354 and buffer termination body 342, that secondary 2DEG, or 2DHG, is not an effective conduction channel. That is to say, the available density of charge carrier states that could be filled at or near the interface of channel layer 354 and buffer termination body 342 is less than approximately 10% of the available density of electron states formed in desirable 2DEG 355. As a result, that weak (or ineffective) secondary 2DEG, or 2DHG, has negligible affect on the performance of the resulting HEMT, and is therefore characterized as being substantially suppressed.
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In some implementations, it may be advantageous or desirable to form buffer termination body 342 of either or both of structures 350-1 and 350-2 so as to have a thin sharp grade. For example, buffer termination body 342 and channel layer 354 may be formed such that thickness 348 of buffer termination body 342 is less than or approximately equal to thickness 358 of channel layer 354. In such implementations, the sum of thickness 348 and thickness 358 may be expected to be sufficiently thin to be punch-through resistant. Thus, buffer termination body 342 can be configured such that it reduces or substantially suppresses the undesirable formation of a secondary 2DEG at or near its interface with channel layer 354, while concurrently providing improved punch-through capability and reduced device leakage.
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Thus, the present application discloses group III-V HEMTs configured to reduce or substantially suppress formation of an undesirable secondary 2DEG. Such reduction or substantial suppression is achieved by situating a buffer termination body having a bandgap larger than that of a channel layer and smaller than that of a buffer layer, between the channel layer and the buffer layer. As a result, the polarization charges at the interface of the channel layer and buffer termination body do not form an effective secondary 2DEG. Moreover, the buffer termination body is configured to have a larger bandgap than the channel layer in order to continue to provide improved punch-through capability and reduced device leakage.
From the above description it is manifest that various techniques can be used for implementing the concepts described in the present application without departing from the scope of those concepts. Moreover, while the concepts have been described with specific reference to certain implementations, a person of ordinary skill in the art would recognize that changes can be made in form and detail without departing from the scope of those concepts. As such, the described implementations are to be considered in all respects as illustrative and not restrictive. It should also be understood that the present application is not limited to the particular implementations described herein, but many rearrangements, modifications, and substitutions are possible without departing from the scope of the present disclosure.
The present application claims the benefit of and priority to a provisional application entitled “Compositionally Graded HEMT Buffer Termination,” Ser. No. 61/897,525 filed on Oct. 30, 2013. The disclosure in this provisional application is hereby incorporated fully by reference into the present application.
Number | Date | Country | |
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61897525 | Oct 2013 | US |