BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a sectional diagram of a semiconductor package disclosed by U.S. Pat. No. 5,726,079;
FIGS. 2A to 2C are sectional diagrams of a semiconductor package disclosed by U.S. Pat. No. 6,458,626;
FIG. 3 is a sectional diagram of a semiconductor package disclosed by U.S. Pat. No. 6,444,498;
FIGS. 4A to 4F are diagrams showing a heat-dissipating package structure and the fabrication method thereof according to a first embodiment of the present invention;
FIGS. 5A and 5B are diagrams showing a heat-dissipating package structure according to a second embodiment of the present invention;
FIG. 6 is a sectional diagram of a heat-dissipating package structure according to a third embodiment of the present invention; and
FIGS. 7A and 7B are sectional diagrams of a heat-dissipating package structure according to a fourth embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those skilled in the art after reading the disclosure of this specification. The present invention can also be performed or applied by other different embodiments. The details of the specification may be on the basis of different points and applications, and numerous modifications and variations can be made without departing from the spirit of the present invention.
First Embodiment
FIGS. 4A to 4F are diagrams showing a heat-dissipating package structure and a fabrication method thereof according to a first embodiment of the present invention.
As shown in FIG. 4A, a semiconductor chip 41 is mounted and electrically connected to a chip carrier 42. A heat-dissipating member 44 having an interface layer 43 on the surface thereof is mounted to the semiconductor chip 41. Therein, the planar size of the heat-dissipating member 41 does not exceed that a predetermined package size to be formed.
The chip carrier 42 may be a BGA substrate or an LGA substrate. The semiconductor chip 41 may be a flip-chip semiconductor chip, the active surface thereof being electrically connected to the chip carrier 42 through a plurality of conductive bumps 410.
The interface layer 43 may be a P.I. tape adhered to the heat-dissipating member 44, an epoxy resin coated on the heat-dissipating member 44, or an organic layer made of such as wax formed on the heat-dissipating member 44. Thus, the adhesion between the interface layer 43 and the encapsulant formed subsequently for encapsulating the semiconductor chip 41 is stronger than that between the interface layer 43 and the heat-dissipating member 44, such that the interface layer and the extra encapsulant located on the interface layer can be removed through a removing process.
As shown in FIG. 4B, the chip carrier 42 with the semiconductor chip 41 and the heat-dissipating member 44 having the interface layer 43 is disposed in a mold cavity (not shown) for performing a subsequent molding process. As a result, an encapsulant 45 encapsulating the heat-dissipating member 44 having the interface layer 43 and the semiconductor chip 41 is formed. As a spacing height exists between the interface layer 43 and the top wall of the mold cavity, the semiconductor chip 41 is prevented from being pressed by the mold after being engaged. In addition, the adhesion between the heat-dissipating member 44 and the semiconductor chip 41 needs not precisely controlled, thereby improving the product yield and the product reliability.
As shown in FIG. 4C, a cutting process is performed to cut the chip carrier 42 and the circumference of the encapsulant 45 according to a predetermined package size. Since the heat-dissipating member 44 will not be cut, the problem of burrs and wearing the cutting tools caused from cutting the heat-dissipating member is prevented to allow the cutting cost to be reduced consequently
As shown in FIG. 4D, an oblique angle is formed on the top edge of the encapsulant 45 around the heat-dissipating member 44 through such as a chamfer grinding process so as to partially expose the edge of the heat-dissipating member 44 having the interface layer 43. In the present embodiment, the encapsulant 45 is grinded until the top corner edge of the heat-dissipating member 44 is exposed.
As shown in FIG. 4E, a removing process is performed so as to remove the encapsulant 45′ located on the interface layer 43. In addition, as the adhesion between the interface layer 43 made of such as a P.I. tape, an epoxy resin or an organic layer and the encapsulant 45 is larger than that between the interface layer 43 and the heat-dissipating member 44, the interface layer 43 and the encapsulant 45′ located on the interface layer 43 can both be removed through the removing process, thereby exposing the top surface of the heat-dissipating member 44. Referring to FIG. 4F, which is a top view of FIG. 4E, heat generated by the semiconductor chip 42 can be dissipated to the outside through the heat-dissipating member 44.
Through the above fabrication method, a semiconductor package structure is obtained, which comprises: a chip carrier 42; a semiconductor chip 41 mounted to and electrically connected to the chip carrier 42; a heat-dissipating member 44 mounted on the semiconductor chip 41; an encapsulant 45 formed on the chip carrier 42 for encapsulating the semiconductor chip 41 and the heat-dissipating member 44, an oblique angle being formed on the top edge of the encapsulant 45 surrounding the heat-dissipating member 44 and the upper surface of the heat-dissipating member 44 being exposed from the encapsulant 45.
Second Embodiment
FIG. 5A is a sectional diagram of a heat-dissipating package structure according to a second embodiment of the present invention and FIG. 5B is a top view of the heat-dissipating package structure of FIG. 5A. In the present embodiment, when a chamfer grinding process is performed on the encapsulant 55 so as to form the oblique angle on the top edge of the encapsulant 55, the heat-dissipating member 54 is also grinded through the grinding process for facilitating the removal of the interface layer on the heat-dissipating member and the encapsulant located on the interface layer.
Third Embodiment
FIG. 6 is a sectional diagram of a heat-dissipating package structure according to a third embodiment of the present invention. In the present embodiment, the interface layer 63 is made of such as Au or Ni. Thus, the adhesion between the interface layer 63 and the heat-dissipating member 64 is larger than that between the interface layer 63 and the encapsulant 65′. Therefore, the encapsulant 65′ located on the interface layer 63 is removed through a removing process while the interface layer 63 remains on the heat-dissipating member 64 and exposed from the encapsulant 65. Thus, heat generated by the semiconductor chip 61 is dissipated to the outside through the heat-dissipating member 64 and the interface layer 63.
Fourth Embodiment
FIGS. 7A and 7B are sectional diagrams showing a heat-dissipating package structure according to a fourth embodiment of the present invention. In the present embodiment, a wire-bonding semiconductor chip 71 is mounted to a chip carrier 72 through its non-active surface, and electrically connected with the chip carrier 72 through a plurality of bonding wires 76. A supporting object 77 such as a scraped chip or a heat-dissipating member is mounted on the active surface of the semiconductor chip 71. Further, a heat-dissipating member 74 having an interface layer 73 is mounted on the supporting object 77. The interface layer 73 may be selected as a P.I. tape, an epoxy resin, an organic layer and so on for making the adhesion between the interface layer 73 and the encapsulant 75 larger than that between the interface layer 73 and the heat-dissipating member 74. Thus, both the interface layer 73 and the encapsulant 75 located on the interface layer 73 can be removed during the removing process so as to expose the heat-dissipating member 74 from the encapsulant, as shown in FIG. 7A. Alternatively, the interface layer 73 can be selected as a metal layer made of such as Au and Ni for making the adhesion between the interface layer 73 and the heat-dissipating member 74 larger than that between the interface layer 73 and the encapsulant 75. Thus, the encapsulant located on the interface layer 73 is removed during the removing process and the interface layer 73 is exposed from the encapsulant, as shown in FIG. 7B.
Therefore, the heat-dissipating package structure and fabrication method thereof mainly comprises the steps of mounting and electrically connecting a semiconductor chip to a chip carrier; mounting a heat-dissipating member having an interface layer on the semiconductor chip; forming an encapsulant that encapsulates the semiconductor chip and the heat-dissipating member having the interface layer on the chip carrier; subsequently, cutting the chip carrier and the encapsulant according to a predetermined package size and forming an oblique angle on the top edge of the encapsulant to partially expose the edge of the heat-dissipating member having the interface layer; and removing the encapsulant located on the interface layer of the heat-dissipating member, thereby forming a heat-dissipating package structure. During the molding process, as there exists a spacing between the interface layer and the top wall of the mold cavity, the formed encapsulant can cover the interface layer, thereby preventing damages to the semiconductor chip pressed by the mold and the problem of flash. Meanwhile, since the cutting line does not pass the heat-dissipating member, the problem of burrs and wearing of cutting tools can be prevented and accordingly the cutting cost can be reduced.
The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention, Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.
Patent Application
20080006933
