Patent Application
20070295994
Prior to description of specific embodiments of the present invention, effects of the present invention are described with reference to
The buffer layer 2 made of undoped AlGaN substantially functions as an insulator when the AlN mole fraction is over 0.2. Differently from the conventional structure, a conductive layer is not present between the collector region 3 and the substrate 1. Because of the structure, the base-collector breakdown voltage is not limited by a thickness in the depth direction of the collector region 3, and the base-collector breakdown voltage can be improved by making larger a distance between the base electrode 8 and the collector electrode 12.
By forming the emitter region 4 and the collector contact region 6 with In0.2Ga0.8N, a conduction-band discontinuity ΔEc in the emitter-base junction and in the base-collector junction is substantially reduced to zero, and also a valence-band discontinuity ΔEv can be set to about 1.8 eV, which is an extremely larger as compared to the thermal energy kT (26 meV at a room temperature, wherein K denotes a Boltzmann constant and T denotes an absolute temperature). Therefore, a reverse injection of holes from the base region to the emitter region can be reduced to a substantially ignorable level as compared to that in a conventional homo-junction bipolar transistor. Therefore, the current gain can advantageously be made higher than 50 as required in the actual use. It is to be noted that, although the same effect can be provided when the InN mole fraction in InGaN used for the emitter region and the collector region is 0.1 or more, when the mole fraction is over 0,3, a dislocation density increases due to the lattice mismatch leading to increase of a recombination current. As a result, the current gain drops to 50 or below, and therefore the InN mole fraction is desirably in the range from 0.1 to 0.3. An example of change in a current gain dependent on the InN mole fraction is shown in
Furthermore, by employing the large valence band discontinuity ΔEv as described above, it is possible to make an acceptor density in the base region larger as compared to a donor density in the emitter region. For instance, even when B (boron) is used as an acceptor in the base region 8 and the density is set to, for instance, about 3×1019 cm−3 which is about 100 times higher than the typical donor density of 3×1017 cm−3 in the emitter region 4, degradation of the current gain can be reduced to an extremely low level. Because of the feature, reduction of a base resistance, which is difficult in a conventional p-type GaN base, can easily and advantageously be realized.
Next, a lateral hetero-junction bipolar transistor and a process for manufacturing the bipolar transistor are described below with reference to the related drawings.
As a first embodiment of the present invention, an example of an npn-type hetero-junction bipolar transistor having the structure of InGaN/polycrystalline Si/InGaN is described. The device and a process for producing the device are described with reference to
A method of manufacturing the transistor according to the present invention is described below with reference to
Then, Si is ion-implanted to the emitter region 4 using a SiON film or a film of metal such as Ni as a mask (Refer to
Then, Si is ion-implanted to regions to be processed to the emitter contact region 5 and to the collector contact region 6 using the same mask as that used for formation of the emitter region. In this step, the ion dose is determined so that the donor densities in the emitter contact region 5 and the collector contact region 6 are equal to or more than 1.0×1019 cm31 3 and less than 1.0×1020 cm−3. Although Si is implanted also to a portion of the buffer layer 2 made of undoped Al0.2Ga0.8N, Si in the buffer layer 2 made of undoped Al0.2Ga0.8N is little activated, and the effect is ignorable. Then the Si implanted to the emitter region 4, the emitter contact region 5 and the collector contact region 6 is annealed for activation. Furthermore, an n-type electrode made of Ti, Ni, or the like is formed on the emitter contact region 5 as well as on the collector contact region 6 by the lift-off method (Refer to
Then the SION film 7 is deposited above the entire surface, and the emitter region 4 and the collector region 3 for forming a base are removed by means of photolithography and dry etching. In this step, even when etching is performed under the condition that the In0.2Ga0.8N is larger in etching rate than Al0.2Ga0.8N, it is difficult to lower the selectivity to zero. Thus, the buffer layer 2 made of undoped Al0.2Ga0.8N is over-etched. However, when the over-etched depth is not more than a thickness of the buffer layer 2 (namely 0.5 μm in this embodiment), no problem occurs (Refer to
Then, by means of the chemical vapor deposition, B-doped polycrystalline Si (with the activated B density of 3×1019 cm−3) are implanted to the entire surface. Then the polycrystalline Si is left only in the base region 8 by photolithography and dry etching (Refer to
Then, the SiON film 7 is again deposited (Refer to
In this embodiment, the buffer layer 2 made of undoped Al0.2Ga0.8N is an insulating body. Differently from the conventional technique, a conductive layer is not provided between the collector region 3 and the substrate 1, so that the base-collector breakdown voltage is not limited by a thickness (1.5 μm in this embodiment) in the depth direction of the collector region 3, and the base-collector withstand voltage can be set to 1 kV by widening the distance between the base region 8 and the collector contact region 12, for instance, to 15 μm.
Furthermore, in the embodiment, it is possible to realize an ideal double hetero-junction structure in which a conduction-band discontinuity ΔEc in the emitter-base junction and in the base-collector junction is substantially zero and a valence-band discontinuity ΔEv is about 1.8 eV, and therefore reverse injection of holes from the base region to the emitter region can be reduced to an ignorable level as compared to that in a conventional homo-junction bipolar transistor, so that the current gain can advantageously be improved.
In contrast to a low hole density of 1.0×1017 cm31 3 or less at a room temperature in a conventional p-type GaN layer, in the embodiment described above, it is possible to realize an extremely high density of holes of 3×1019 cm−3 with polycrystalline Si. Because of the feature, reduction of a base resistance, which has been difficult in the conventional p-type GaN base, can advantageously and easily be realized.
In a second embodiment of the present invention, a plurality of lateral hetero-junction bipolar transistors are formed on a substrate. A plurality of lateral hetero-junction bipolar transistors described in the first embodiment above are provided with the buffer layer 2 made of undoped Al0.2Ga0.8N in common on a chip as shown in
With the second embodiment of the present invention, it is possible to realize a base-collector breakdown voltage and a current gain sufficient for practical use, and also to realize a lateral high power bipolar transistor with a reduced base resistance.
A third embodiment of the present invention provides a semiconductor having a structure in which a polycrystalline Si layer is provided between a semiconductor alloy layer made of GaN or containing GaN as a main ingredient and an ohmic electrode.
In the third embodiment, a relation between a width of the semiconductor alloy layer (Eg4) and that of the polycrystalline Si layer (Eg5) is Eg>Eg5. Furthermore it is required to employ a semiconductor made of a compound of elements belonging to III to V groups which is not decomposed at the temperature for formation of the polycrystalline Si film (in the range from 600° C. to 800° C.) and also which has a low vapor pressure of V group element. Namely, as an element belonging to the V group, P, As, and Sb are not allowable, and N should be employed. There are AlN, GaN, and InN as materials for substrates based on a compound of elements belonging to III to V groups in which N is employed as an element belonging to V group, but in a case of AlGaN with the AlN mole fraction of over 0.5, the material functions like an insulator, and in that case, doping control required for a semiconductor is difficult. On the other hand, in a case of InGaN with the InN mole fraction of over 0.5, In tends to be re-evaporated from the surface at the temperature required for formation of a polycrystalline Si film, which disadvantageously causes surface roughening. For the reasons as described above, materials made of GaN or containing GaN as a main ingredient (represented by AlxGayIn(1-x-y)N) are optimal III-V compound semiconductors in combination with polycrystalline Si. In the AlxGayIn(1-x-y)N, preferably the following conditions should be satisfied: 0≦x<0.5 and 0≦y≦1.
In the embodiment, the semiconductor alloy layer, the polycrystalline Si layer, and the conductor layer are laminated in the vertical direction, but the layers are arrayed in the horizontal direction.
A semiconductor alloy is a base material, and the polycrystalline Si layer should homogeneously cover the base material for reduction of a contact resistance, and therefore a thickness of the polycrystalline Si layer should be 10 nm or more.
In this embodiment, a height of a Schottky barrier between an n-type semiconductor containing GaN or GaN as a main ingredient and a metal is around 0.7 eV, which is large. In contrast, a contact resistance between polycrystalline Si and a metal can be reduced to an ignorable level by doping polycrystalline Si at a high density of 1×1019 cm31 3. In addition, since conduction-band discontinuity between the n-type semiconductor made of GaN or containing GaN as a main ingredient and the polycrystalline Si is small, namely around 0.3 eV, the contact resistance between the n-type semiconductor made of GaN or containing GaN as a main ingredient and the metal can be made smaller by inserting the polycrystalline Si on the interface.
A specific example of the present invention is an application to a light emitting diode. More specifically, the application of polycrystalline Si to a semiconductor made of a GaN-based compound is further applied to a light emitting diode made of In0.2Ga0.8N. This example is described below with reference to
The conventional light emitting diode made of In0.2Ga0.8N as shown in
In contrast, the light emitting diode made of In0.2Ga0.8N according to the present invention as shown in
With the embodiment described above, a temperature rise during operations of the light emitting diode made of In0.2Ga0.8N can be suppressed, which advantageously makes it possible to maintain the quantum efficiency at a high level. The light emitting diode according to the third embodiment of the present invention is described above, but it is needless to say that the present invention can be applied to any GaN-based optical device such as a semiconductor laser or to any GaN-based electronic device such as a junction type field-effect transistor in the same way.
A fourth embodiment of the present invention is, like in the third embodiment of the present invention, an example of a semiconductor device in which a polycrystalline Si layer is present between a semiconductor alloy layer made of GaN or containing GaN as a main ingredient and an ohmic electrode.
A specific example is an application of the present invention to an ultrahigh-speed LSI (large Scale Integrated Circuits). That is, in the example, the polycrystalline Si applied to the GaN-based compound semiconductor used in the first embodiment is applied to a field-effect transistor (FET) containing GaN in the n-type channel. This example is described with reference to
At first, a buffer layer 72 made of undoped AlGaN (with AiN and AlGa alloy laminated and also with the thickness of 0.2 μm), a buffer layer 73 made of undoped GaN buffer (with the thickness of 0.3 μm), an etch-stop layer 74 made of undoped AlGaN (with the AlN mole fraction of 0.05 and with the thickness of 0.1 μm), a layer 75 made of undoped GaN (with the thickness of 1 μm), and a layer 76 made of undoped AlGaN (wi the AlN mole fraction of 0.25 and with the thickness of 3 μm) are grown by metal organic chemical vapor deposition on the Si (111) substrate 71. A Si (111) surface is used for the substrate 71, and therefore both GaN and AlGaN are hexagonal. In addition, on an interface between the layer 75 made of undoped GaN and the layer 76 made of undoped AlGaN, a two-dimensional electron gas (sheet electron concentration of 1×1013 cm−2 and electron mobility of 2000 cm2/Vs) are formed in association with spontaneous polarization and piezo polarization. Then, an SiO2 film 78 (with the thickness of 0.5 μm) is deposited by means of chemical vapor deposition (Refer to
Next, the SiO2 of the sample is placed in contact with a surface of the Si (100) substrate 79, and the surfaces are fused to each other by applying a load at the temperature of 1000° C. (Refer to
Then the Si (100) substrate 79 is adhered to a glass substrate, and the Si (iii) substrate 71 is thinned from the rear surface down to the thickness of 50 μm with a polishing machine (Refer to
Then, the Si (111) substrate 71 other than in the region for formation of the n-channel GaN FET 96, the buffer layer 72 made of undoped AlGaN, the buffer layer 73 made of undoped GaN buffer, the etch-stop layer 74 made of undoped AlGaN, a layer 75 made of undoped GaN (with the thickness of 1 μm), and the layer 76 are removed by photolithography and dry etching. Then, by chemical vapor deposition, a SiO2 film 80 (with the thickness of 0.5 μm) is formed substantially isotropically, and the SiO2 film 80 in a region for formation of the Si CMOSFET 92 is removed by photolithography and dry etching. Then, a p-type Si well 81 and an n-type Si well 82 are formed by photolithography, ion-implanting, and annealing for activation. In addition, a trench for device isolation is formed by photolithography and dry etching, and a region for device isolation 83 by deposition of SiO2 film and etching back the film (Refer to
Then, a gate insulating film 84 (SiO2) and a gate electrode 85 (polycrystalline Si) are formed by chemical vapor deposition, photolithography, and dry etching (Refer to
Then, a high concentration n-type Si region 86 and a high concentration p-type Si region 87 are formed by photolithography, ion implanting, and annealing for activation. An n-type ohmic electrode 88, an a p-type ohmic electrode 89 are formed to prepare a Si CMOSFET 92 having an n-channel Si MOSFET 90 and a p-channel Si MOSFET 91 (Refer to
Then, the entire surface is coated with SiO2 by chemical vapor deposition, and SiO2 in a region for formation of an n-channel GaN FET 96 is removed by photolithography and dry etching. Then, a portion of the Si(111) substrate 71, a portion of the undoped AlGaN buffer layer 72, and a portion of the undoped GaN buffer layer 73 are removed by dry etching. Then a remaining portion of the layer 73 made of undoped GaN buffer is removed by wet etching to have the etch stop layer 74 made of undoped AlGaN exposed (
Then, a refractory metal (WSi) is deposited by sputtering, and a gate electrode 93 is formed by photolithography and dry etching. Then a high concentration n-type GaN region 94 is formed using the gate electrode as a mask by Si ion implanting and annealing for activation. Then polycrystalline Si is deposited on the entire surface with the polycrystalline Si 95 left only on the high concentration n-type GaN region 94 as a buffering layer for lowering a contact resistance with the ohmic electrode (Refer to
Then, SiO2 is deposited on the entire surface by chemical vapor deposition, and the SiO2 is removed only from the region for formation of a p-type Ge FET 102 by photolithography and dry etching. Then a buffer layer 97 made of undoped SiGe (with the thickness of 0.5 μm) and a layer 98 made of p-type Ge (with the thickness of 0.2 μm) are selectively grown by the ultra-high vacuum chemical vapor deposition (Refer to
Then, a refractory metal (WSi) is deposition by sputtering, and a gate electrode 99 is formed by photolithography and dry etching. A high concentration p-type Ge/SiGe region 100 is formed by photolithography, ion implanting, and annealing for activation. Then polycrystalline Si is deposited on the entire surface, and the polycrystalline Si 101 is left only on the high concentration p-type Ge/SiGe region 100 as a buffering layer for lowering a contact resistance with the ohmic electrode (Refer to
Finally, the inter-layer SiO2 film 78 is deposited, and after a contact hole is formed by photolithography, Al is deposited on the entire surface, an Al wiring 106 is formed by photolithography and dry etching. Furthermore, a hybrid LSI comprising the Si CMOSFET 92 having the n-channel Si MOSFET 90 and 91 p-channel Si MOSFET 91 and a ultrahigh speed complementary FET having the n-channel GaN FET 96 and the p-channel Ge FET 102 is prepared (Refer to
With the embodiment described above, by using polycrystalline Si on an interface between an n-type GaN having a high contact resistance and an ohmic electrode, it is possible to lower the contact resistance so as to achieve ultrahigh speed operations, and also it is possible to employ common processes for Si LSIs such as a process for forming wirings using polycrystalline Si and Al and a process for forming the wirings by dry etching without using manufacturing processes of semiconductors made of compounds such as GaN not suitable for high-density integration in semiconductor devices such as alloy electrodes, Au wiring, and formation of liftoff thereof. Therefore, even when GaN is applied to an n-channel semiconductor, it is possible to realize a high-speed LSI without dropping the integration density. Differently from semiconductors made of compounds of group-V materials such as GaAs, GaP, and GaSb having a high vapor pressure, re-evaporation of N does not occur in GaN even at a high temperature of around 1100° C., and compatibility with the Si LSI process is excellent, and the features contribute to realization of the hybrid LSIs in this embodiment. In this embodiment, a semiconductor contacting polycrystalline Si is described, and it is needless to say that the same effects as those provided in the third embodiment can be achieved by using an alloy containing GaN as a main ingredient.
Description of reference numerals in the figures are provided below.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-173730 | Jun 2006 | JP | national |
