Patent Grant
9035354
1. Field of the Invention
The present invention relates to high frequency transistors and in particular relates to microwave field effect transistors (FETs) that incorporate nitride-based active layers.
2. Description of the Related Art
The present invention relates to transistors formed of nitride semiconductor materials that can make them suitable for high power, high temperature, and/or high frequency applications. Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide application in semiconductor devices for lower power and (in the case of Si) lower frequency applications. These more common semiconductor materials may not be well suited for higher power and/or high frequency applications, however, because of their relatively small bandgaps (e.g., 1.12 eV for Si and 1.42 for GaAs at room temperature) and/or relatively small breakdown voltages.
GaAs based HEMTs have become the standard for signal amplification in civil and military radar, handset cellular, and satellite communications. GaAs has a higher electron mobility (approximately 6000 cm2/V-s) and a lower source resistance than Si, which may allow GaAs based devices to function at higher frequencies. However, GaAs has a relatively small bandgap (1.42 eV at room temperature) and relatively small breakdown voltage, which may prevent GaAs based HEMTs from providing high power at high frequencies.
In light of the difficulties presented by Si and GaAs, interest in high power, high temperature and/or high frequency applications and devices has turned to wide bandgap semiconductor materials such as silicon carbide (2.996 eV for alpha SiC at room temperature) and the Group III nitrides (e.g., 3.36 eV for GaN at room temperature). These materials typically have higher electric field breakdown strengths and higher electron saturation velocities as compared to gallium arsenide and silicon.
A device of particular interest for high power and/or high frequency applications is the high electron mobility transistor (HEMT), which is also known as a modulation doped field effect transistor (MODFET) or a Heterostructure Field Effect Transistor (HFET). These devices may offer operational advantages under a number of circumstances. They are typically characterized by the presence of a two-dimensional electron gas (2DEG) formed at the heterojunction of two semiconductor materials with different bandgap energies, where the smaller bandgap material has a higher electron affinity compared to the larger bandgap material. The 2DEG, which forms due to the presence of an accumulation layer in the smaller bandgap material, can contain a very high sheet electron concentration in excess of, for example, 1013 carriers/cm2 even though the material is nominally undoped. Additionally, electrons that originate in the wider-bandgap semiconductor transfer to the 2DEG, allowing a high electron mobility due to reduced ionized impurity scattering.
This combination of high carrier concentration and high carrier mobility can give the HEMT a very large transconductance and may provide a performance advantage over metal-semiconductor field effect transistors (MESFETs) for high-frequency applications, although MESFETs continue to be suitable for certain applications based on factors such as cost and reliability.
High electron mobility transistors fabricated in the gallium nitride (GaN) material system have the potential to generate large amounts of RF power because of the combination of material characteristics that includes the aforementioned high breakdown fields, their wide bandgaps, large conduction band offset, and/or high saturated electron drift velocity. In addition, polarization of GaN-based materials contributes to the accumulation of carriers in the 2DEG region.
GaN-based HEMTs have already been demonstrated. U.S. Pat. No. 6,316,793, to Sheppard et al., which is commonly assigned and is incorporated herein by reference, describes a HEMT device having a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an aluminum gallium nitride barrier layer on the gallium nitride layer, and a passivation layer on the aluminum gallium nitride active structure.
Improvements in the manufacturing of GaN semiconductor materials have focused interest on the development of GaN HEMTs for high frequency, high temperature and high power applications. GaN-based materials have large bandgaps, and high peak and saturation electron velocity values [B. Belmont, K. Kim and M. Shur, J. Appl. Phys. 74, 1818 (1993)]. GaN HEMTs can also have 2DEG sheet densities in excess of 1013/cm2 and relatively high electron mobility (up to 2000 cm2/V-s) [R. Gaska, J. W. Yang, A. Osinsky, Q. Chen, M. A. Khan, A. O. Orlov, G. L. Snider and M. S. Shur, Appl. Phys. Lett., 72, 707 (1998)]. These characteristics may allow GaN HEMTs to provide high power at higher frequencies.
A conventional GaN HEMT structure 110 is illustrated in
Typically, the channel layer 114 includes GaN while barrier layer 116 includes AlGaN. Because of the presence of aluminum in the crystal lattice, AlGaN has a wider bandgap than GaN. Thus, the interface between a GaN channel layer 114 and an AlGaN barrier layer 116 forms a heterostructure or heterojunction where energy bands are deformed due to, for example, Fermi level alignment and polarization in the material.
In addition, in a nitride-based device, the conduction and valence bands in the barrier layer 116 are further distorted due to polarization effects. This very important property of the heterostructures in the III-Nitride system may be essential for the high performance of the GaN HEMT. In addition to the accumulation of electrons due to the bandgap differential and band offset between the barrier and channel layers, the total number of free electrons is enhanced greatly by pseudomorphic strain in the barrier layer relative to the channel. Due to localized piezoelectric effects, the strain causes an enhanced electric field and a higher electron concentration than would, typically, be possible were the strain not present.
Electrons in the 2DEG sheet charge region 115 demonstrate high carrier mobility. Moreover, because the sheet charge region is extremely thin, the carriers are subject to reduced impurity scattering that may improve the device's noise characteristics.
The source to drain conductivity of this device structure is modulated by applying a voltage to the gate electrode 122. When a reverse voltage is applied, the conduction band beneath the gate is elevated, with the result that the conduction band Ec in the vicinity of the sheet charge region 115 becomes elevated above the Fermi level, and a portion of the sheet charge region 115 is depleted of carriers, thereby preventing or reducing the flow of current from source 118 to drain 120.
By forming the barrier layer 116 from AlN, certain advantages can be achieved. The 2.4% lattice mismatch between AlN (AlyGa1-yN for y=1) and GaN results in an increased and even maximum possible piezoelectric charge at the interface between the two layers. Using an AlN barrier layer also reduces the piezoelectric scattering between the layers that can limit the 2DEG mobility.
However, the high lattice mismatch between AlN and GaN dictates that the thickness of the AlN layer should be less than 50 Å. If the layer is thicker, the device can experience problems with its ohmic contacts, the material quality in the layer begins to degrade, the device's reliability decreases, and the material is more difficult to grow. However, a HEMT with a 50 Å or less AlN layer may be susceptible to high gate leakage.
Although GaN-based HEMTs have demonstrated exceptional power densities, a number of technical challenges still remain to be overcome before the devices can achieve commercial success. For example, one problem that may limit the performance and lifetime of certain GaN-based HEMTs is free carrier trapping, which may occur when carriers migrate away from the 2DEG region and become trapped in a surface dielectric region or in a buffer region beneath the channel. Such trapping may result in degradation in performance and/or reliability of a device.
Some attempts have been made to improve confinement of carriers within a HEMT channel by providing a second heterojunction below the channel—a so-called Double Heterostructure HEMT or DH-HEMT. However, in general, the amount of confinement due to the heterobarrier (which is a function of the difference in electron affinity between a wide-bandgap layer and the narrower-bandgap channel) may not be sufficiently large to result in effective confinement. Moreover, in a highly polarized material such as c-plane GaN, the polarization charges present in the material may reduce the confinement effect of the heterobarrier. Thus, in nitride-based transistor devices, the mere presence of a heterojunction alone below the channel may not be sufficient to effectively prevent carriers from migrating away from the 2DEG region into the buffer region where they can become trapped. Moreover, the structure of a DH-HEMT provides no additional barrier against surface trapping effects.
Another problem associated with the transit of carriers away from the channel region is linearity. When carriers are not confined to the channel, the ability to control their action via the applied gate voltage may be reduced, resulting in undesirable nonlinear transconductance characteristics.
The problems associated with free carrier trapping may also affect the performance of other types of nitride field effect transistors, such as GaN-based MESFETs.
According to some embodiments of the present invention, a heterojunction transistor may include a channel layer comprising a Group III nitride, a barrier layer comprising a Group III nitride on the channel layer, and an energy barrier comprising a layer of a Group III nitride including indium on the channel layer. The barrier layer may have a bandgap greater than a bandgap of the channel layer, and the channel layer may be between the barrier layer and the energy barrier. In addition, a concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer.
More particularly, the channel layer and the barrier layer may cooperatively induce a two-dimensional electron gas at an interface between the channel layer and the barrier layer. For example, the energy barrier may include a layer of InxGa1-xN (0<x#1), and more particularly, a layer of InxGa1-xN (0<x<1). A mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier may be at least about 1%. For example, a mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier may be in the range of about 1% to about 50%, and more particularly in the range of about 4% to about 16%.
The energy barrier may oppose movement of carriers away from the channel layer, and/or the energy barrier may include a quantum well. Moreover, the energy barrier may have a thickness in the range of about 1 Angstrom to about 200 Angstroms, and more particularly, in the range of about 1 Angstrom to about 100 Angstroms.
The heterojunction transistor may also include source, drain, and gate contacts on the barrier layer such that the barrier layer is between the channel layer and the source, drain, and gate contacts, and a substrate on the energy barrier such that the energy barrier is between the substrate and the channel layer. The barrier layer may have a thickness in the range of about 0.1 nm to about 10 nm. The barrier layer and the energy barrier may be separated by a distance in the range of about 5 nm to about 30 nm, and more particularly in the range of about 5 nm to about 20 nm. In addition, the channel layer may include a layer of AlyGa1-yN (0#y<1), the barrier layer may include a layer of AlzGa1-zN (0<z#1), and y and z may be different.
Moreover, the heterojunction transistor may include a cap layer including a Group III nitride on the barrier layer such that the barrier layer is between the cap layer and the channel layer. A concentration of Ga in the cap layer may be greater than a concentration of Ga in the barrier layer. A concentration of Al in the barrier layer may be greater than a concentration of Al in the channel layer.
According to some additional embodiments of the present invention, a method of forming a heterojunction transistor may include forming an energy barrier comprising a layer of a Group III nitride including indium, forming a channel layer comprising a Group III nitride on the energy barrier, and forming a barrier layer comprising a Group III nitride on the channel layer so that the channel layer is between barrier layer and the energy barrier. A concentration of indium (In) in the energy barrier may be greater than a concentration of indium (In) in the channel layer, and the barrier layer may have a bandgap greater than a bandgap of the channel layer.
The channel layer and the barrier layer may cooperatively induce a two-dimensional electron gas at an interface between the channel layer and the barrier layer. For example, the energy barrier may include a layer of InxGa1-xN (0<x#1), and more particularly, a layer of InxGa1-xN (0<x<1). A mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier may be at least about 1%. More particularly, a mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier may be in the range of about 1% to about 50%, and more particularly, in the range of about 4% to about 16%. The energy barrier may oppose movement of carriers away from the channel layer, and/or the energy barrier may include a quantum well. Moreover, the energy barrier may have a thickness in the range of about 1 Angstrom to about 200 Angstrom, and more particularly, in the range of about 1 Angstrom to about 100 Angstroms.
Forming the energy barrier may include forming the energy barrier on a substrate. In addition, source, drain, and gate contacts may be fanned on the barrier layer after &liming the barrier layer. For example, the channel layer may include a layer of AlyGa1-yN (0≦y<1), the barrier layer include a layer of AlzGa1-zN (0<z≦1), and y and z may be different. After forming the barrier layer, a cap layer comprising a Group III nitride may be formed on the barrier layer, and a concentration of Ga in the cap layer may be greater than a concentration of Ga in the barrier layer. Moreover, a concentration of Al in the barrier layer may be greater than a concentration of Al in the channel layer.
Forming the channel layer may include forming a first portion of the channel layer on the energy barrier at a first temperature. After forming the first portion of the channel layer, a second portion of the channel layer may be formed at a second temperature on the first portion of the channel layer wherein the first temperature is less than the second temperature. The first temperature, for example, may be at least about 100 degrees C. less than the second temperature. In addition, the first and second portions of the channel layer may each comprise GaN.
According to some more embodiments of the present invention, a heterojunction transistor may include a channel layer, a barrier layer on the channel layer, and an energy barrier on the channel layer such that the channel layer is between the barrier layer and the energy barrier. The barrier layer and the channel layer may cooperatively induce a two-dimensional electron gas at an interface between the channel layer and the barrier layer, and the energy barrier may oppose movement of carriers away from the channel layer.
The energy barrier may include a quantum well. The channel layer may include a first layer of a Group III nitride, the barrier layer may include a second layer of a Group III nitride, and the energy barrier may include a third layer of a Group III nitride. The energy barrier, for example, may include a layer of InxGa1-xN (0<x≦1), and more particularly, the energy barrier may include a layer of InxGa1-xN (0<x<1). A mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier may be at least about 1%, and more particularly, in the range of about 1% to about 50%, and more particularly, in the range of about 4% to about 16%. Moreover, the energy barrier may have a thickness in the range of about 1 Angstrom to about 200 Angstroms, and more particularly, in the range of about 1 Angstrom to about 100 Angstroms.
The heterojunction transistor may also include source, drain, and gate contacts on the barrier layer such that the barrier layer is between the channel layer and the source, drain, and gate contacts, and the heterojunction transistor may also include a substrate on the energy barrier such that the energy barrier is between the substrate and the channel layer. The channel layer may include a Group III nitride, the barrier layer may include a Group III nitride, and the barrier layer may have a bandgap greater than a bandgap of the channel layer. The channel layer may include a layer of AlyGa1-yN (0≦y<1), the barrier layer may include a layer of AlzGa1-zN (0<z≦1), and y and z may be different.
In addition, a cap layer including a Group III nitride may be provided on the barrier layer such that the barrier layer is between the cap layer and the channel layer, and a concentration of Ga in the cap layer may be greater than a concentration of Ga in the barrier layer. Moreover, the barrier layer may include a Group III nitride and the channel layer may include a Group III nitride, and a concentration of Al in the barrier layer may be greater than a concentration of Al in the channel layer.
a is a table providing parameters for HEMT structures (Sample1-5 corresponding to Sample1-5 of
b-c are graphs illustrating back-confinement values Vbc and device resistances Dr, respectively, as functions of a percentage of Indium in the InGaN layer in the structures of
a-b include graphs illustrating gain, power out, and power added efficiency for control HEMT structures and for HEMT structures according to embodiments of the present invention.
a-b include graphs illustrating drain currents for control HEMT structures and for HEMT structures according to embodiments of the present invention.
The present invention will now be described more fully with reference to the accompanying drawings in which some embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
Furthermore, the various layers and regions illustrated in the figures are illustrated schematically. Accordingly, the present invention is not limited to the relative size and spacing illustrated in the accompanying figures. As will also be appreciated by those of skill in the art, references herein to a layer formed “on” a substrate or other layer may refer to the layer formed directly on the substrate or other layer or on an intervening layer or layers formed on the substrate or other layer. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that although the terms first, second, etc. may be used herein to describe various regions, layers, and/or sections, these regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer, or section from another region, layer, or section. Thus, a first region, layer, or section discussed below could be termed a second region, layer, or section, and similarly, a second without departing from the teachings of the present invention.
As discussed above, confinement of carriers in the channel is an important concern in the design of a nitride-based field effect transistor. Embodiments of the present invention may provide enhanced confinement of carriers through the inclusion of a high-field region on one or both sides of a channel. The electric field in the high field region may be generated by the transfer of charge between an electron source region and a hole source region. The electric field in the high field region is directed away from the channel. Thus, the electric field opposes the movement of negatively charged electrons away from the channel. (In general, the direction of an electric field is defined by the direction of electric force acting on a positively charged particle.)
As used herein, the term “Group III nitride” refers to those semiconducting compounds formed between nitrogen and the elements in Group III of the periodic table, usually aluminum (Al), gallium (Ga), and/or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. As is well understood by those in this art, the Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN) compounds. These compounds all have empirical formulas in which one mole of nitrogen is combined with a total of one mole of the Group III elements. Accordingly, formulas such as AlxGa1-xN where 0≦x≦1 are often used to describe them. For brevity, when the term AlInGaN is used herein without specification of relative percentages for the Group III elements (Al, In and Ga), it will be understood to refer to a compound of the general formula InxAlyGazN where x+y+z=1, 0≦x≦1, 0≦y≦1, and 0≦z≦1. Thus, as used herein, the term InAlGaN may refer to GaN, InN, AlN, AlGaN, AlInN, InGaN and/or AlInGaN unless otherwise specified or limited. Accordingly, the terms “InAlGaN”, “Group III-nitride material” and “nitride-based material” are used interchangeably throughout this specification.
Embodiments of the present invention are schematically illustrated as a high electron mobility transistor (HEMT) 10 in the cross-sectional view of
A buffer layer 13 on the substrate 12 provides an appropriate crystalline transition between the substrate 12 and the remainder of the device. Buffer layer 13 may include one or more layers of InAlGaN. In particular embodiments, buffer layer 13 may include AlN or AlGaN. Silicon carbide has a much closer crystal lattice match to Group III nitrides than does sapphire (Al2O3), which is a very common substrate material for Group III nitride devices. The closer lattice match may result in Group III nitride films of higher quality than those generally available on sapphire. Silicon carbide also has a very high thermal conductivity so that the total output power of Group III nitride devices on silicon carbide is, typically, not as limited by thermal dissipation of the substrate as in the case of the same devices formed on sapphire. Also, the availability of semi-insulating silicon carbide substrates may provide for device isolation and reduced parasitic capacitance.
Although silicon carbide is the preferred substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, GaAs, LGO, ZnO, LAO, InP and the like. In some embodiments, an appropriate buffer layer also may be formed.
Suitable SiC substrates are manufactured by, for example, Cree, Inc., of Durham, N.C., the assignee of the present invention, and the methods for producing are described, for example, U.S. Pat. Nos. Re. 34,861; 4,946,547; 5,200,022; and 6,218,680, the contents of which are incorporated herein by reference in their entirety. Similarly, techniques for epitaxial growth of Group III nitrides have been described in, for example, U.S. Pat. Nos. 5,210,051; 5,393,993; 5,523,589; and 5,592,501, the contents of which are also incorporated herein by reference in their entirety.
Particular structures for GaN-based HEMTs are described, for example, in commonly assigned U.S. Pat. No. 6,316,793 and U.S. application Ser. No. 09/904,333 filed Jul. 12, 2001 for “ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME,” U.S. provisional application Ser. No. 60/290,195 filed May 11, 2001 for “GROUP III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER,” U.S. patent application Ser. No. 10/102,272, to Smorchkova et al., entitled “GROUP-III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER” and U.S. patent application Ser. No. 10/199,786, to Saxler, entitled “STRAIN BALANCED NITRIDE HETEROJUNCTION TRANSISTORS AND METHODS OF FABRICATING STRAIN BALANCED NITRIDE HETEROJUNCTION TRANSISTORS” the disclosures of which are hereby incorporated herein by reference in their entirety. Embodiments of the present invention may be incorporated into such structures and, therefore, should not be construed as limited to the particular structures described in detail herein.
Returning again to
A barrier layer 16 is provided on the channel layer 14. The barrier layer 16 may be a Group III-nitride having a bandgap larger than that of the channel layer 14. Accordingly, the barrier layer 16 may be AlGaN, AlInGaN, AlInN and/or AlN. The barrier layer 16 may be at least about 10 nm thick, but is not so thick as to cause cracking or defect formation therein. Moreover, the barrier layer 16 should be thin enough that it is completely depleted under equilibrium conditions.
Preferably, the barrier layer 16 is undoped or doped with activated donor atoms at a concentration of less than about 1019 cm−3. In some embodiments, the barrier layer 16 may be delta-doped at a concentration of up to about 1013 cm−2 at a distance of about 100 Å (Angstroms) from the interface between barrier layer 16 and channel layer 14. In some embodiments of the invention, the barrier layer 16 includes AlxGa1-xN where 0<x≦1. In certain embodiments of the present invention, the barrier layer 16 includes AlGaN with an aluminum concentration of between about 5% and about 100%. In specific embodiments of the present invention, the aluminum concentration is greater than about 10%. The barrier layer 16 has a bandgap greater than that of the channel layer 14.
The barrier layer may also be provided with multiple layers as described in U.S. patent application Ser. No. 10/102,272, to Smorchkova et al., entitled “GROUP-III NITRIDE BASED HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH BARRIER/SPACER LAYER” and U.S. Pat. No. 6,316,793 entitled “Nitride Based Transistors on Semi-Insulating Silicon Carbide Substrates with Passivation Layer” issued Nov. 13, 2001, the disclosures of which are incorporated herein by reference as if set forth fully herein. Thus, embodiments of the present invention should not be construed as limiting the barrier layer to a single layer but may include, for example, barrier layers having combinations of InAlGaN layers having various material compositions. For example, a GaN/AlN structure may be utilized to reduce or prevent alloy scattering.
An optional InAlGaN contact layer or cap layer (not shown) may be provided on the barrier layer 16 to facilitate the formation of contacts of the transistor 10. An example of such a cap layer is disclosed in U.S. application Ser. No. 09/904,333 filed Jul. 12, 2001 for “ALUMINUM GALLIUM NITRIDE/GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTORS HAVING A GATE CONTACT ON A GALLIUM NITRIDE BASED CAP SEGMENT AND METHODS OF FABRICATING SAME,” which is referenced above. In addition, there may be a compositionally graded transition layer (not shown) between the barrier layer 16 and the contact or cap layer. The source contact 18, the drain contact 20 and the gate contact 22 may be fabricated as described in U.S. Pat. No. 6,316,793.
As discussed above, a 2DEG sheet charge region 15 is induced at the interface between channel layer 14 and barrier layer 16. In order to reduce the movement of carriers away from the channel layer 14, a region 32 having a high electric field is provided between the channel layer 14 and the buffer layer 13. In some embodiments, the high field is generated by charge transfer between an electron source layer 34 and a hole source layer 30 which are spaced apart by a distance “d” which defines the thickness of the high field region 32.
In some embodiments, including the embodiment illustrated in
Moreover, the buffer 13 may be doped with deep acceptors as described in S. Heikman et al., Growth of Fe-Doped Semi-insulating GaN by Metalorganic Chemical Vapor Deposition, Appl. Phys. Let. 81, pp. 439-441 (2002). Specific examples of co-doped layers are provided in U.S. patent application Ser. No. 10/752,970 entitled “Co-Doping for Fermi Level Control in Semi-Insulating Group III Nitrides”, filed Jan. 7, 2004 and assigned to the assignee of the present invention, the disclosure of which is incorporated herein by reference. The buffer could be doped with Fe or another deep acceptor.
This effect is illustrated in
Because the electron source layer is designed to be fully depleted, the layer is characterized by a fixed positive charge from the ionized donor atoms. In the illustration of
where KS is the relative dielectric constant of the semiconductor material and ∈0 is the permittivity of free space. Since the structure is in equilibrium, the net charge density is assumed to be zero within the immediate vicinity of the electron source layer and hole source layer but nonzero within those layers. The resulting electric field is shown in
V(x)=∫∞KE(x)dx
The electric potential in the structure is illustrated in
As an example of a design methodology, consider a pair of two oppositely doped layers which are very thin compared to their separation. Assume both are have an identical sheet charge that is depleted. Thus, the sheet charge density in each layer is given as Nsheet=Psheet (both given in units of cm−2).
The electric field between the two sheets of charge is then (q×Psheet)/∈ where q is the elementary charge (1.602*10−19C) and ∈ is the dielectric constant of the material (about 9*8.85*10−14F/cm for GaN). For GaN, the electric field would be about Psheet*(2×10−7 V-cm). Thus, for a sheet charge density of 1012 cm−2, the field would be about 2×105 V/cm.
The built in voltage is the product of the electric field with the separation distance d.
Vbi=d*(q*Psheet)/ε
This voltage is necessarily less than Eg−Ea−Ed where Eg is the energy gap, Ea is the acceptor ionization energy relative to the valence band and Ed is the donor ionization energy relative to the conduction band. To ensure full depletion, a voltage for the barrier should be chosen to be safely below Eg−Ea−Ed.
So, if Vbi<(Eg−Ea−Ed)/q
Then d×(q×Psheet)/∈<(Eg−Ea−Ed)/q
d×Psheet×(2×10−7 V-cm)<(Eg−Ea−Ed)/q
d×Psheet<5×106×(Eg−Ea−Ed)/q(V−1 cm−1)
If we assume relatively shallow acceptors and donors, a 2V barrier may be an appropriate goal.
d×Psheet<2×5×106/cm=107/cm
d×Psheet<107/cm×104 μm/cm
d×Psheet<1011 μm/cm2
If we choose a sheet charge density that is small compared to the channel charge, but large enough for a field that may improve confinement, for example 1012 cm−2 then
d<1011 μm/cm2/Psheet or
d<0.1 μm
In order to obtain a sheet density of 1012 cm−2 in the electron source layer 34 and the hole source layer 30, the semiconductor crystal may be delta doped. As is known in the art, delta doping refers to doping a semiconductor layer with a very high density of dopants in a very thin region. For example, to form hole source layer 30, the semiconductor crystal of AlxGa1-xN may be doped with an acceptor such as Mg or Zn at an activated concentration of about 1018 cm−3 for a depth of about 10 nm. Hole source layer 30 may be doped with deep level acceptor elements such as Fe or V. Alternatively, hole source layer 30 may be co-doped with deep level transition elements, such as Fe or V, along with shallow acceptor dopants, such as Zn and/or Mg. Using shallow acceptors with smaller activation energies Ea may yield a larger maximum built-in voltage VbiHowever, if the material is overdoped, free acceptors could be generated which would adversely impact device performance. Also, it is undesirable to form a “camel hump” in the conduction band Ec that could trap electrons. Thus, it may be preferable to keep Vbi fairly low and choose a dopant with a low memory effect in the growth system.
Similarly, the electron source layer may be doped with Si, Ge or O atoms. However, other forms of doping may be used in conjunction with thicker layers. For example, doping in the layers could be progressively graded or abrupt. Moreover, the electron source layer and the hole source layer may be thicker or thinner than 10 nm. In general, the electron source layer and hole source layer may each range in thickness from about 0.2 nm to about 100 nm. The electron source layer and the hole source layer do not have to have the same thickness or doping density.
Thus, for a 2V barrier, “d” may be less than about 0.1 μm. In general, depending on the desired barrier height and the doping levels used, the thickness “d” of the high field region 32 may range from about 10 nm to about 200 nm.
Depending on the desired barrier, different doping levels and spacings may be chosen. In some embodiments, the barrier may have a potential height of less than about 0.5V. In other embodiments, the barrier height may be about 1V or less. In still other embodiments, the barrier height may be about 2V or less. As discussed above, the limit on the barrier height is that it be less than (Eg−Ea−Ed).
In some embodiments, the electron source layer may include the 2DEG region induced at the interface of the barrier layer and the channel layer. In such embodiments, the 2DEG region should not be fully depleted by the hole source region. An example of such embodiments is shown in
The conductivity of this region is modulated by applying a voltage to the gate electrode 22. When a reverse voltage is applied, the conduction band in the vicinity of conduction layer 15 is elevated above the Fermi level, and a portion of the conduction layer 15 is depleted of carriers, thereby preventing the flow of current from the source 18 to the drain 20.
To oppose the movement of electrons away from the channel layer, an energy barrier is formed by inserting the electron source layer 34 and the hole source layer 30 between the channel layer 14 and the buffer layer 13. The electron source layer 34 and the hole source layer 30 are spaced apart by a distance “d” which defines a region 32 having a high electric field. The slope of the energy bands within the region 32 is directly related to the strength of the electric field in this region. As illustrated in
Other embodiments of the present invention are illustrated in
As with the embodiments described above, the transfer of carriers between the quasi-p-type region created at the interface between the first and second layers 38 and 36 and the electron source layer 34 creates a high field region 32 that serves as a barrier against electrons transiting away from the 2DEG region 15.
In some embodiments, the second layer 36 comprises InAlGaN. In particular embodiments, the second layer 36 may include AlxGa1-xN with 0.02≦x≦0.2. The second layer 36 may also have a graded composition for lattice matching or strain relief. The second layer 36 may be from 10 nm to 10 μm thick. Moreover, the second layer 36 may be omitted altogether if buffer layer 13 has a suitable aluminum composition such that an interface between buffer layer 13 and the first layer 38 forms a heterojunction capable of acting as a hole source layer.
An illustrative band diagram for the structure of
As discussed above, it may also be desirable to prevent as many carriers from the channel layer 14 from reaching the surface of a transistor device. Although the exposed surface of a transistor device is usually passivated, carrier trapping in interface states of a passivation layer may have a negative impact on the performance and/or lifetime of a microwave transistor.
Accordingly, in some embodiments of the invention, a potential barrier is formed in the structure to resist or oppose the movement of carriers away from the channel layer 14 towards the surface of the device.
In order to form effective source and drain ohmic contacts 18, 20 it may be desirable to recess the contacts, for example by etching through the hole source layer 40, the high field layer 42 and the electron source layer 44 to expose a surface of barrier layer 16 prior to metallization as illustrated in
An illustrative band diagram for the structure of
As with the embodiments illustrated in
An illustrative band diagram of the device 10C is shown in
The carrier confining potential barriers described with reference to
Other embodiments of the present invention are illustrated in
In certain of the embodiments illustrated in
An illustrative band diagram for the structure of
Embodiments of the present invention illustrated in
Method embodiments of the present invention are illustrated in
In some embodiments illustrated in
In particular embodiments illustrated in
In other embodiments, a channel layer is formed, an electron source layer is formed on the channel layer, a high field region is formed on the electron source layer and a hole source layer is formed on the high field region.
The steps of forming a channel layer, forming an electron source layer, forming a high field region and forming a hole source layer are described in detail above. In particular, the step of forming an electron source layer may include delta-doping a thin layer of a nitride-based crystal with donor (n-type) impurities. For example, as discussed above, an electron source layer may be formed by doping a semiconductor crystal with a concentration of dopant atoms of about 1018 cm−3 for a thickness of about 10 nm. Similarly, the step of forming a hole source layer may include delta-doping a thin layer of a nitride-based crystal with acceptor (p-type) impurities. As discussed above, the electron and hole source layers may be formed thicker or thinner than 10 nm. Moreover, the electron and hole source layers do not have to have the same thickness and/or doping levels.
Instead of forming an intentionally doped layer, the step of forming an electron source layer may be accomplished simultaneously with the formation of a 2DEG at a GaN/AlGaN interface. That is, the 2DEG region may act as the electron source layer for purposes of certain embodiments. Similarly, the step of forming a hole source layer may be accomplished by the formation of a heterointerface that acts as an acceptor-doped region due to piezoelectric effects as discussed above.
Additional embodiments of the present invention are illustrated in
The charge induced by an InN/GaN interface may be expected to be very high (>2×1014 cm−2), so no more than ˜2 monolayers may be desired for a large barrier. The interfaces 30A and 34A are the hole and electron source regions, respectively, and each may possess this very large charge density. Therefore, a very thin layer 38 (energy barrier or back barrier) may be capable of producing a large barrier as previously described. Also, the InxGa1-xN (0<x≦1) layer 38 may be kept thin enough so that there may be no allowed energy levels fowled within the quantum well that may act as electron or hole traps. Accordingly, for a GaN/InN/GaN structure, the InN may be kept below ˜2 monolayers for this reason. For a GaN/InGaN/GaN (or AlGaN/GaN/AlGaN or other InAlGaN/InAlGaN/InAlGaN) structure with a given barrier layer, a thickness of the layer 38 may be increased approximately linearly as the band offset is decreased to reduce and/or prevent accumulation of electrons in the well. A maximum allowable thickness for forbidding quantum levels within the well may scale only approximately as the square root of the thickness of the layer 38. Therefore, a large discontinuity in band gap may be desirable. Interface regions 30A and 34A may each be either abrupt or graded.
In certain of the embodiments illustrated in
By providing the layer 38 (energy barrier or back barrier) as a layer of InxGa1-xN (0<x<1), as opposed to a layer of InN, manufacturability of the device may be increased. According to some embodiments of the present invention, a mole fraction of InN in an alloy of InN/GaN making up the layer 38 (energy barrier or back barrier) may be at least about 1% (percent), and more particularly, in the range of about 2% (percent) to about 20% (percent). Moreover, a concentration of indium in the layer 38 may vary in directions parallel and/or perpendicular with respect to a surface of the substrate, and/or the layer 38 may include InN and/or GaN dots (inclusions) therein.
Embodiments of the present invention illustrated in
According to some embodiments of the present invention, the substrate 12 may be a semi-insulating silicon carbide (SiC) of the 4H polytype, the buffer layer 13 (nucleation layer) may be a layer of AlN, the layer 36 may be a layer of GaN, the layer 38 (energy barrier or back barrier) may be a layer of InxGa1-xN (0<x≦1), the low temperature protective layer 55 may be a layer of GaN, the channel layer 14 may be a layer of GaN, the barrier layer 16 may be a layer of AlN, and the cap layer 17 may be a layer of AlnGa1-nN (0≦n≦1). Moreover, ohmic implants may be provided to improve contact with one or more of the source contact 18 and/or the drain contact 20, and/or the passivation layer 52 may be a layer of silicon nitride such as a High Purity Nitride (HPN).
As shown in
Particular structures according to embodiments of the present invention are illustrated in the table of
The layer 38 (energy barrier or back barrier) has a thickness of about 5 nm (nanometers) for Samples1-11, and the layer 38 is omitted (i.e., a thickness of 0) from Control1-2. The layer 38 has a mole fraction of InN in an InN/GaN alloy of: about 4% for Sample1 and Sample4; about 6% for Sample5; about 8% for Sample2-3, Sample6, and Sample9-11; about 12% for Sample7; and about 16% for Sample8. The layer 38 was formed at a temperature of: about 699 degrees C. for Sample8; about 739 degrees C. for Sample7; about 779 degrees C. for Sample6 and Sample9; about 784 degrees C. for Sample2-3; about 804 degrees C. for Sample5; about 819 degrees C. for Sample10-11; and about 824 degrees C. for Sample1 and Sample4. Moreover, layer 38 of Sample9-10 was doped with silicon on the order of 5×1017 per cm3, and layer 38 of Sample11 was doped with silicon on the order of 2×1018 per cm3. Layer 36 in each of Sample1-11 and Control1-2 has a thickness of about 2000 nm (nanometers).
By providing a InxGa1-xN (0<x≦1) layer 38 on the channel layer 14 opposite the barrier layer 16 (as in each of Sample1-11), a resulting polarization may improve charge confinement of the 2DEG at the interface of the channel and barrier layers 14 and 16. More particularly, the InxGa1-xN (0<x≦1) layer 38 may form a charge dipole raising a conduction-band potential in the GaN layer 36. The InxGa1-xN (0<x≦1) layer 38 is not required to be an active current carrying layer so that a quality InxGa1-xN (0<x≦1) layer 38 may be relatively low. A concentration of indium in the InxGa1-xN (0<x<1) layer 38 may thus vary in directions perpendicular and/or parallel with respect to a surface of the substrate 12, and/or the layer 38 may include InN and/or GaN dots (inclusions) therein. Moreover, the InxGa1-xN (0<x≦1) layer 38 of each of Sample1-11 may provide a barrier in the range of about 0.2 eV to about 0.4 eV. In addition, a structure of each of Sample1-11 may be provided as a 0.5 μm (micrometer) stepper based HEMT.
According to some embodiments of the present invention, the barrier layer 16 may have a thickness in the range of about 0.1 nm to about 10 nm, and more particularly, in the range of about 0.7 nm to about 0.8 nm, and/or the barrier layer 16 may be separated from the energy barrier 38 by a distance in the range of about 5 nm to about 30 nm, and more particularly, in the range of about 5 nm to about 20 nm, and still more particularly in the range of about 10 nm to about 15 nm. According to some embodiments of the present invention, the channel layer 14 may have a thickness in the range of about 1 nm to about 20 nm, and more particularly in the range of about 8 nm to about 10 nm, and/or the GaN protective layer 55 may have a thickness of about 15 nm or less, and more particularly, of about 7 nm or less. According to some embodiments of the present invention, the energy barrier 38 may have a thickness in the range of about 0.1 nm (1 Angstrom) to about 10 nm (100 Angstrom), and more particularly, in the range of about 1 nm (10 Angstrom) to about 5 nm (50 Angstrom). According to some embodiments of the present invention, a mole fraction of InN (indium nitride) in an InN/GaN alloy of the energy barrier may be in the range of about 1% to about 50%, and more particularly, in the range of about 4% to about 16%.
The band diagrams of
Without the InxGa1-xN (0<x≦1) layer 38, the electron distribution (dashed line) may extend well into a buffer region as shown in
Drain-source output resistances Rds (measured in ohms) are provided in
As shown in
Confinement may be improved with improved quality of the InxGa1-xN (0<x≦1) layer 38, and a relatively thin InxGa1-xN (0<x≦1) layer 38 with a relatively high In (indium) mole fraction may provide a relatively high dipole and improved confinement. A high indium (In) content InxGa1-xN (0<x≦1) layer 38, however, may be difficult to grow with high crystal quality. An effective InxGa1-xN (0<x≦1) layer 38 (energy barrier or back barrier) may be provided with a relatively low In content (for example, having a mole fraction of InN in an InN/GaN alloy of about 5%) and a thickness in the range of about 10 Å (Angstroms) to about 50 Å (Angstroms).
Heterojunction transistors (such as HEMTs) according to embodiments of the present invention may be formed by forming an epitaxial nucleation layer 13 (such as an MN nucleation layer) on a single crystal substrate (such as a 4H—SiC substrate). An epitaxial Group III nitride layer 36 (such as a layer of GaN may be formed on the nucleation layer 13, and an epitaxial Group III nitride energy barrier layer 38 (such as a layer of InxGa1-xN where 0<x≦1 or where 0<x<1) may be formed on the layer 36.
An epitaxial Group III nitride low temperature protective layer 55 (such as a layer of InAlGaN) may be formed on the energy barrier layer 38, and an epitaxial Group III nitride channel layer 14 (such as a layer of InAlGaN) may be formed on the low temperature protective layer 55. More particularly, the low temperature protective layer 55 may be formed at a temperature at least 100 degrees C. less than a temperature at which the channel layer 14 is formed. For example, the low temperature protective layer 55 may be formed at a temperature in the range of about 600 degrees C. to about 800 degrees C., and the channel layer 14 may be formed at a temperature of at least about 1000 degrees C. The low temperature protective layer 55 may thus protect the energy barrier layer 38 during the subsequent step of forming the channel layer 14, and the low temperature protective layer 55 may be considered a part of the channel layer 14. After forming the channel layer 14, an epitaxial Group III nitride barrier layer 16 (such as a layer of InAlGaN) may be formed on the channel layer 14, and an epitaxial Group III nitride cap layer 17 (such as a layer of InAlGaN) may be formed on the barrier layer 16. After forming the cap layer 17, source, gate, and drain contacts 18, 22, and 20 and passivation layer 52 may be fowled.
More particularly, Group III nitride compositions of the energy barrier layer 38, the channel layer 14, the barrier layer 16, and the cap layer 17 may vary. For example, a concentration of gallium in the cap layer 17 may be greater than a concentration of gallium in the barrier layer 16. A concentration of aluminum in the barrier layer 16 may exceed a concentration of aluminum in the channel layer 14 and/or the low temperature protective layer 55. Moreover, a concentration of indium in the energy barrier layer 38 may exceed a concentration of indium in the channel layer 14 and/or the low temperature protective layer 55. For example, the energy barrier layer 38 may comprise a layer of InxGa1-xN (0<x≦1), the channel layer 14 may comprise a layer of AlyGa1-yN (0≦y<1), and the barrier layer 16 may comprise a layer of AlzGa1-zN (0<z≦1), and x, y, and/or z may be different. More particularly, the energy barrier layer 38 may comprise a layer of InxGa1-xN (0<x<1), the channel layer 14 may comprise a layer of GaN, the barrier layer 16 may comprise a layer of AlN, and the cap layer 17 may comprise a layer of AlnGa1-nN (0<n<1).
HEMT structures according to embodiments of the present invention may provide improved power performance, for example, for mm-wave amplifiers for satellite communication, mm-wave WLAN (Wireless Local-Area Network), Digital Radio, solid-state amplifiers for vacuum tube replacement, and/or high frequency amplifiers for test and measurement applications. Power levels of 5 to 10 times that currently available using gallium-arsenide (GaAs) and/or indium-phosphorus (InP) transistors may be provided by HEMT structures according to embodiments of the present invention with relatively high efficiency and/or high power mm-wave amplifier operation.
By including the InxGa1-xN (0<x≦1) layer 38 in HEMT structures according to embodiments of the present invention, output characteristics may be improved by providing confinement from the backside of the GaN HEMT channel layer 14. Performance may be improved for HEMT structures operating at radio frequency (RF) and/or microwave frequencies, and even more significant improvements may be provided for HEMT structures operating at higher frequencies. As gate lengths are scaled down for higher frequency operations, device output conductance may be reduced linearly. Although on-resistance may also decrease due to dimensional shrinkage, the reduction may be at a much lower rate so that power gain may be compromised, and improvement of extrinsic cut-off frequency fmax with respect to ft may be less than desired. Moreover, a sub-threshold leakage may increase when the gate length is below 0.25 μm (micrometers) so that Power Added Efficiency (PAE) is reduced.
In alternatives, an energy barrier (or back barrier) may be provided using AlGaN based buffer layers. AlGaN layers, however, may tend to be unintentionally doped, and dopant compensation may cause deep traps. Moreover, a crystal quality of bulk AlGaN may generally be less than a crystal quality of currently available GaN, because the crystal formation process for AlGaN may be more complicated and may be subjected to alloy disorder. A layer of AlGaN may be provided between the 2-DEG and a relatively high quality GaN buffer, but a buried sub-channel may form at the first AlGaN/GaN interface. Grading the AlGaN from the GaN buffer may reduce the sub-channel while generating bulk polarization charges, possibly reducing confinement.
Exemplary embodiments described herein having heterostructures as a hole or electron source are illustrated with respect to Ga-polar epitaxial layers. For exemplary embodiments relying on doping to provide a hole and/or source layer, such structures would be the same for non-polar or partially Ga polar. However, typically, non-polar structures would not be able to take advantage of heterointerface polarization doping. Embodiments of the present invention employing N-polar structures would look different in terms of the heterostructure layers, although the same principles apply, just reversed.
The table of
The gate contacts 22 of the devices represented in the tables of
The gate length Lg is the distance from one side of the gate contact 22 adjacent the drain contact 18 to the other side of the gate contact 22 adjacent the source contact 20 shown in
A back-confinement value Vbc may define a confinement of the two dimensional electron gas at a particular frequency Ft, and the InGaN layer 55 according to embodiments of the present invention may provide improved back-confinement values. More particularly, back-confinement values may be calculated as shown below:
Vbc=Rds*Ft*d.
The back-confinement value Vbc as calculated above may also represent a confinement potential per unit area of sheet-charge density (V/Ns*q) where V is the confinement potential, Ns is the sheet charge, and q is the unit electron charge.
In the structures of
Vbc(Sample3)=(287.8 ohm mm)(27.7*10−6 mm)(44 GHz)=0.35 ohm mm2 GHz
Of the device of
Vbc(Sample4)=(197.8 ohm mm)(27.7*10−6 mm)(39 GHz)=0.21 ohm mm2 GHz
Of the devices (Control1 and Control2) of
Vbc(Control1)=(163.3 ohm mm)(27.7*10−6 mm)(44 GHz)=0.20 ohm mm2 GHz
Vbc(Control2)=(137.3 ohm mm)(27.7*10−6 mm)(41 GHz)=0.16 ohm mm2 GHz
According to embodiments of the present invention a heterojunction transistor may include a channel layer 14 of a Group III nitride, a barrier layer 16 of a Group III nitride on the channel layer 14 wherein the barrier layer 16 has a bandgap greater than a bandgap of the channel layer 14, a gate contact 22 on the barrier layer 16 so that the barrier layer 16 is between the gate contact 22 and the channel layer 14, and source and drain contacts 18 and 20 on opposite sides of the gate contact 22. In addition, an energy barrier 38 of InGaN may be provided on the channel layer 14 so that the channel layer 14 is between the energy barrier 38 and the barrier layer 16, and the energy barrier 38 may be configured to provide a back confinement value Vbc of at least about 0.21 ohm mm2 GHz, and more particularly, a back confinement value Vbc of at least about 0.3 ohm mm2 GHz. Moreover, the energy barrier 38 may be configured to provide back confinement values Vbc of at least approximately 0.21 ohm mm2 GHz for unity gain frequencies Ft of at least about 35 GHz.
In addition, a device resistance Dr may be defined as a function of drain-source output resistance Rds, gate length Lg, and the separation d between the gate contact 22 and the two dimensional electron gas (2DEG). More particularly, device resistance Dr may be calculated as shown below:
Dr=Rds*d/Lg.
In the structures of
Dr(Sample3)=(287.8 ohm mm)(27.7 nm)/(550 nm)=14.5 ohm mm
Of the device of
Dr(Sample4)=(197.8 ohm mm)(27.7 nm)/(550 nm)=10 ohm mm
Of the devices (Control1 and Control2) of
Dr(Control1)=(163.3 ohm mm)(27.7 nm)/(550 nm)=8.2 ohm mm
Dr(Control2)=(137.3 ohm mm)(27.7 nm)/(550 nm)=6.9 ohm mm
According to embodiments of the present invention a heterojunction transistor may include a channel layer 14 of a Group III nitride, a barrier layer 16 of a Group III nitride on the channel layer 14 wherein the barrier layer 16 has a bandgap greater than a bandgap of the channel layer 14. A gate contact 22 may be provided on the barrier layer 16 so that the barrier layer 16 is between the gate contact 22 and the channel layer 14, and source and drain contacts 18 and 20 may be provided on opposite sides of the gate contact 22. In addition, an energy barrier 38 of InGaN may be provided on the channel layer 14 so that the channel layer 14 is between the energy barrier 38 and the barrier layer 16, and the energy barrier 38 may be configured to provide a device resistance Rd of at least about 9 ohm mm, and more particularly, a device resistance Rd of at least about 14 ohm mm.
As shown in the table of
The graphs of
The graphs of
As shown in the graphs of
The graphs of
The graph of
The graphs of
The HEMT structure according to embodiments of the present invention used to provide the information of
In the drawings and specification, there have been disclosed typical embodiments of the invention, and, although specific terms have been employed, they have been used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.
The present application claims the benefit of priority as a divisional application of U.S. patent application Ser. No. 11/357,752 filed Feb. 17, 2006 now U.S. Pat. No. 7,612,390, which claims the benefit of priority as a continuation-in-part application of U.S. patent application Ser. No. 10/772,882 filed Feb. 5, 2004 now U.S. Pat. No. 7,170,111. The disclosures of both of the above referenced applications are hereby incorporated herein in their entirety by reference.
This invention was made with Government support under Contract Nos. N00014-02-C-0306 and FA8650-04-C-7146 awarded by the Office Of Naval Research (ONR) and the Air Force Research Laboratory (AFRL). The Government has certain rights in this invention.
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| WO 03049193 | Jun 2003 | WO |
| WO 2004008495 | Jan 2004 | WO |
| WO 2005024909 | Mar 2005 | WO |
| WO 2005083793 | Sep 2005 | WO |
| Entry |
|---|
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| Number | Date | Country | |
|---|---|---|---|
| 20100187570 A1 | Jul 2010 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11357752 | Feb 2006 | US |
| Child | 12566973 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10772882 | Feb 2004 | US |
| Child | 11357752 | US |
