Patent Application
20150372096
The present invention is related to transistor devices and circuits for power switching and microwave amplification. More specifically, it is related to high mobility transistors and microwave integrated circuits with improved critical dimension uniformity, increased lithographic yield and reduced defects in the active components.
In addition to devices based on a metal-oxide-semiconductor (MOS) structure, an insulated gate bipolar transistor (IGBT) structure and a lightly doped drain metal-oxide-semiconductor (LDMOS) structure which are commonly used for power switching and signal amplification, a new class of semiconductors based on III-nitrides are being developed. This is due to the needs to enhance the circuit performance by having higher power handling capability and to reduce the unwanted power loss, beyond what the present silicon-based devices can provide. There is also a need to provide devices which can perform at high frequencies, preferably in the millimetre wave regions, higher than 10 GHz or even higher than 100 GHz.
The new class of III-nitride semiconductors include the ones where III represents Al, Ga and In. Examples of the new class of semiconductors include AlN, GaN, InN, AlGaN, InGaN and their alloys. Some of these new III-nitrides have exceptional electronic properties suitable for devices having reduced unwanted power losses and increased power handling capability over a wide range of frequencies up to millimetre waves. Such performance characteristics are made possible due to the inherent properties including short energy relaxation time, τ, large energy bandgaps and high electron mobility as compared to silicon and gallium arsenide. Due to the short relaxation time and large energy bandgaps, devices fabricated using these III-nitride semiconductors and their alloys have breakdown electric fields substantially greater than the silicon or gallium arsenide counter parts. For example, the breakdown electric field for AlGaN is 3.0×106 V/cm which is about 10 times of that for Si and GaAs and devices made of AlGaN can sustain larger voltages with the same device dimensions or thicknesses during the operation. As a result, the critical temperatures of some of the III-nitrides for stable operation are substantially higher than GaAs and Si. For example, the critical junction temperature for stable operation is 250° C. for silicon devices, 400° C. for GaAs devices and 600° C. for devices based on III-nitrides. Combining the high critical breakdown electric field, high mobility and high critical operation temperature, it is evident that III-nitrides devices and circuits are idea for high power switching and high frequency millimetre wave circuit applications and it is possible for the III-nitrides to replace some of the high frequency applications currently provided by GaAs technology.
Currently, the III-nitride layers are often deposited on sapphire (Al2O3), silicon carbide (SiC) and silicon (Si) substrates. Due to the difference between the III-nitrides materials and the substrates (sapphire, SiC or Si) used, there is often a mismatch in lattice constants and a difference in thermal expansion coefficients between the substrates and the III-nitride layers. These thermal expansion coefficient difference and lattice mismatch will induce strain or stresses in the epitaxial III-nitride thin films during cooling or heating period. They also lead to strain and stresses in the sapphire, SiC and Si substrates and create a deformation of the substrates, which might cause critical dimension uniformity to deteriorate and induce defects such as microcracks in the III-nitride epitaxial layers.
In
Conventional manufacturing method for devices or circuits based on the III-nitride layers on a wafer involves several photolithography processes. Each requires one photomask. A typical photolithography process includes (1) applying photoresist and soft baking, (2) exposing to transfer the patterns on the photomask to a selected region or field in the photoresist on the wafer then step and repeat or step and scan over the entire wafer, (3) developing the transferred patterns in each field in a developer, (4) rinsing and drying and (5) examine patterns and determining critical dimensions of features in the patterns. After the photolithography process, either etching of epitaxial layers in the exposed regions not covered by the photoresist or deposition of metal layers in exposed regions will be performed. After the etching or deposition, the remaining photoresist will be removed and the wafer cleaned for subsequent photolithography process. One of the key steps in photolithography is (2) transferring of patterns on the photomask onto a field in the photoresist, which is made either using a stepper or a scanner. As seen in
In an imaging system, the minimum feature in a printed photoresist patterns is given by: FS=k1 λ/NA, here k1 is a constant of about 0.3-0.4, λ is the wavelength of the light source and NA is numerical aperture of the lens (220). As values of k1 and NA are substantially constant for a given stepper or scanner, a light source with a short wavelength is used to achieve a small FS. A stepper using i-line of Hg lamp has a wavelength λ=365 nm whereas a scanner using an ArF laser has a wavelength λ=193 nm. Another important parameter in a stepper or a scanner is the depth of focus (DOF) (280) which is a parameter defining the imaging performance of the photoresist. It is the depth range of the wafer over which the feature sizes are within the specifications. Value of DOF is typically defined as the wafer plane height variation that leads to a ±10% variation of the critical dimension (CD) or width of the smallest features printable in the stepper or scanner.
In Table 1 the wavelength, NA and DOF are listed for steppers and scanners using different light sources. It is noted that the values of DOF are quite small and can pose difficulties when such systems are used to project images of patterns on a photomask onto photoresist applied on a wafer with a large bow or deformation, considering the need of uniform critical dimension (CD) over a single field. As the value of bow exceeds the DOF of the stepper or scanner, the critical dimension (CD) or the width of the smallest features in the projected and developed photoresist patterns will have width variation from one location to the others in the field. This variation in the smallest feature dimension will degrade the electronic performance of devices or circuits. In order to ensure the success in the photolithography imaging, a wafer with a bow is held in position against a wafer chuck by an attracting force. Such attracting force often induces additional strain or stresses superimposing on the original strain or stresses already induced during the deposition of composite epitaxial layers. The additional strain or stresses will have further effects on the performance of the devices or circuits fabricated.
The present invention provides high mobility transistors and microwave integrated circuits based on III-nitride epitaxial layers or III-arsenide epitaxial layers with improved critical dimension uniformity and reduced defects in active components.
a is a cross-section of a wafer or substrate for III-nitride layers deposition with a diameter (100D) and a thickness (100T).
a shows a portion of a concave substrate with a deformation bow (330) substantially smaller than the depth of focus (280) of the stepper or scanner.
a shows microcracks (410, 420 and 430) induced in the composite epitaxial layers (402).
a is a schematic cross-sectional view of a wafer (510) with composite epitaxial layers (520) and a first photoresist layer (540) on top, showing a concave deformation with a bow (530):
a is a schematic cross-sectional view of a field (600) having a substrate (610) with composite epitaxial layers (620) and a first photoresist layer (640), showing a concave deformation with a bow (630).
a shows sample (700) having a substrate (710) with composite epitaxial layers (720).
a is a schematic top view of a HEMT, showing four dicing lane edges (911, 912, 913, 914) and four composite epitaxial HEMT region edges (921, 922, 923, 924). The values of the four distances (921D, 922D, 923D, 924D) between adjacent dicing lane edges and composite epitaxial HEMT region edges are kept to be greater than 100 μm and more preferably more than 150 μm according to this invention in order to avoid the effects due to the presence of dicing lanes and the associated reduction in strain and stresses in said composite epitaxial layer region on said HEMT.
a shows a portion of a wafer or a substrate (310), with a photoresist layer (320) applied on it and the width of the substrate portion (310W) is substantially the same as the field image width (270W) shown in
When the deformation of a concave substrate portion (310) is severe, the bow (330′) is substantially greater than DOF (280) of the imaging system, as shown in
When the deformation of a convex substrate portion (310) is severe, the bow (330″) is substantially greater than DOF (280) of the imaging system, as shown in
During exposing, a substrate must be flat within the entire field width. This is often achieved by applying an attracting force to the wafer against a chuck either by an electrostatic force or by vacuum. Such a force deforms the wafer and the composite epitaxial layers on it and induces more strain or stresses on top of the existing strain or stresses induced in the composite epitaxial films during deposition, hence increases strain or stresses to an even more severe level. These strain or stresses lead to creation of unwanted microcracks (410, 420, 430,
These unwanted microcracks can have detrimental effects to active devices such as HEMTs in a switching circuit of MMIC when these microcracks are within or close to the active channel. In
Refer now to
In the conductive channel layer (442C), there are charge carriers or electrons (455) shown as circles with a density controlled during the epitaxial deposition of the composite (InGaN—AlGaN—GaN) epitaxial layer so that appropriate stresses will allow a sheet resistance of the conductive channel layer to be in the order of 100 to 200 ohm per square or less. In the ON state, for a HEMT with a ratio of channel width (446W) to channel length (446L) of 100, the resistance of the channel region between said source and drain is equal to 1 ohm or 2 ohm which can be neglected for certain switching applications. When a voltage is applied between said gate (445, 445P) and said source (443) so that majority of the charge carriers or electrons are expelled from the conductive channel layer (442C) immediately below the gate (445). The expelling of charge carriers or electrons is due to electric fields created in the Schottky barrier layer (442S) immediately below said gate, by the voltage applied between the gate and the source. The expelling lead to depletion of charge carriers or electrons in the conductive channel layer (442C) immediately below gate (445) and increases its resistivity by several orders of magnitude. The HEMT is now in an OFF state where resistance between the drain (444) and the source (443) increases by several orders of magnitude from the original ON resistance value of 1 ohm. The HEMT in the above description is an ideal device without been affected by the unwanted presence of microcracks and acts as an electronic switch.
When intermediate voltages are applied between said gate and source, intermediate amounts of charge carriers or electrons will remain so that the resistance between the drain and the source will have intermediate values. When a voltage is applied between the drain and the source, intermediate currents will be allowed to flow from drain to source. With the above behaviour, the HEMT acts as an electronic amplifier for alternating currents or signals, which may vary at microwave or millimetre wave frequencies. In order to obtain good device performance for both switching and signal amplification, the conductive channel in ON state must have continuous distribution of charge carriers or electrons.
As indicated before, the above description of operations of the HEMT (440) in
According to one embodiment of this invention, before fabricating devices and circuits on a wafer (510) with composite epitaxial layers (520) and having a substantial initial bow (530) as shown in
In order to carry out this grooving process, a first photoresist layer (540) is applied on the surface of the composite epitaxial layers (520) coated wafer (510) for a first photolithography process and a first etching process. Exposing and developing said first photoresist layer using a first photomask to remove photoresist and to expose the composite epitaxial layers (520) in the X-axis field lanes (550-1, 550-2, 550-3, 550-4, 550-5, 550-6, 550-7, 550-8, see
The first photolithography process for the first grooving may be implemented using a first mask with 1 to 1 projection or proximity printing. This is because the resolution of field lanes is often large in the order of 50 μm or 100 μm. Alternately, the first photolithography may well be achieved using a stepper due to the large field lanes dimensions and due to the fact that the field lanes are located in four periphery regions. With the complete removal or partial removal of the composite epitaxial channel layers in the field lanes, the strain or stresses in the substrate wafer is partially removed so that the final bow (590) will have a value substantially less than the initial bow (530) before the etching of the materials in the field lanes. After applying a second photoresist (585) on the released wafer, the localized region bow (590′,
To improve the thermal stability of the present HEMT, there is a need to deposit a layer of passivation material such silicon nitride and silicon oxide nitride, silicon oxide nitride, magnesium oxide, hafnium oxide, aluminum oxide and the mixtures. As the technology of passivation for transistor devices is not the scope of this invention, more description will not be given.
The substrate may be silicon, silicon carbide, sapphire and GaAs as long as their crystalline quality is suitable for epitaxial growth of the III-nitride layers. Materials for the III-nitride layers may include AlN, GaN, InN, AlGaN, InGaN, AlInN and their alloys. Materials for drain contact and source contact can be selected from a combination of metals such as Ti, W, Pt, Al, Au, Cu as long as the first metal contacting the composite epitaxial layers can make a low contact resistance. Whereas materials for said gate can be selected from a material group of Ni, Ta, W, Pt, Al, Ti as long as the first metal contacting the channel gate region can make a rectifying Schottky contact.
The most important photolithography process in device or circuit fabrication is for creation of the smallest features. For high electron mobility transistor (HEMT), this will be the one for the creation of gate and more specifically for the creation of the stem portion of said gate. For a HEMT or circuit for microwave and millimetre wave applications, the length of said gate stem portion (or CD) will be as small as 100 nm or even less than 50 nm. To achieve such a small length for said gate stem portion, a scanner with a light source of short wavelength must be used. The wavelength for the scanners for this purpose is 193 nm and the associated DOF is small: 500 nm. Therefore, the complete removal or partial removal of materials from the field lanes alone may not be sufficient to achieve the required wafer surface flatness to obtain the required CD uniformity over the entire fields.
According to another embodiment of this invention, before the fabrication of devices and circuits, a second grooving process is carried out to remove composite epitaxial layers (620) in the dicing lanes as shown in
In order to carry out second grooving process to further improve uniformity of the smallest features, a first photoresist layer (640,
The first photolithography process for the second grooving may be implemented using a first mask with 1 to 1 projection or proximity printing. This is because the resolution or width of dicing lanes is often large. Alternately, the first photolithography may well be achieved using a stepper due to the large chip dimensions. With the removal or partial removal of composite epitaxial channel layers in said dicing lanes, the strain or stresses in the substrate is partially removed so that the final bow (690) is reduced from the initial bow (630) before the etching of the materials in the scribing or dicing lanes. After applying a second photoresist (695) on the released substrate, the localized region bow (690′,
To improve the thermal stability of the present HEMT, a layer of passivation material such silicon nitride and silicon oxide, silicon oxide nitride, magnesium oxide, hafnium oxide, aluminum oxide and their mixtures is deposited on the top surface of the HEMT. As the technology of passivation for transistor devices is not the scope of this invention, more description will not be given.
The substrate may be silicon, silicon carbide, sapphire and GaAs as long as their crystalline quality is suitable for epitaxial growth of the III-nitride layers. Materials for the III-nitride layers may include AlN, GaN, InN, AlGaN, InGaN, AlInN and their alloys. Materials for the drain contact and the source contact can be selected from a combination of metals such as Ti, W, Pt, Al, Au, Cu as long as the first metal contacting the composite epitaxial layers can make a low contact resistance. Materials for the gate can be selected from a metal group including Ni, Ta, W, Pt, Al, Ti and Au as long as the first metal contacting the channel gate region can make a rectifying Schottky contact.
Although the second grooving process is used as an example in the following descriptions, it should be noted that this etching process can be used for both the second grooving process and for the first grooving process. Etching of materials in composite epitaxial layers may be achieved using conventional photolithography and dry etching. As shown in FIG. 7a, sample (700) comprises a substrate (710) with composite epitaxial layers (720) deposited on the top surface. The composite epitaxial layers comprise a first buffer layer (721) with a first buffer layer thickness (721T), a conductive channel layer (722) with a conductive layer thickness (722T), a Schottky barrier layer (723) with a Schottky barrier layer thickness (723T), a ledge layer (724) with a ledge layer thickness (724T), a doped ohmic contact layer (725) with a doped ohmic contact layer thickness (725T). On top of the composite epitaxial layers a first photoresist layer (730L, 730R,
According to another embodiment of the present invention, above-described etching may be continued so that the buffer layer in the exposed region (721C′) is etched down to a thickness (721T′,
According to this invention, the composite epitaxial layers are III-nitride layers selected from a material group of AlN, GaN, InN, AlGaN, InGaN, AlInN and their alloys where as substrate is selected from a material group of sapphire, SiC and Si.
When fabricating a high electron mobility transistor based MMIC on composite epitaxial layers coated substrate with substantial deformation from stain or stresses, the uniformity of the width of the smallest features can be improved further and the unwanted formation of microcracks during processing can be further reduced according to yet another embodiment of this invention. As shown in
For those skilled in the art, it is understandable that MMIC according to this invention may include additional HEMTs beyond the second stage HEMT. Hence, there could be a third stage HEMT or even a fourth stage HEMT to achieve desired performance of the MMICs. According to yet another embodiment of this invention, after the etching of composite epitaxial layer, the substrate area outside the first composite epitaxial layer HEMT region (841) and outside the second composite epitaxial layer HEMT region (851) is covered by a layer of insulator such as silicon nitride, silicon oxide, silicon oxide nitride, magnesium oxide, hafnium oxide, aluminum oxide and their mixtures. It is preferred for such insulator layers to have a large breakdown electric field and low stresses so as not to cause further deformation of the substrate.
After the first and the second grooving processes, stress and strain in the substrate and in the composite epitaxial layers are reduced and the uniformity of the critical dimension is improved. However, the etching of epitaxial layers in the field lanes and in the dicing lanes will also change the strain and stress between individual layers of the composite layers. As described before, appropriate stresses is necessary for the operation of the high electron mobility transistors After the etching of the composite epitaxial layers in the field lanes and in the dicing lanes, the strain and stress in the Schottky layer (442S) become smaller. This will cause reduction of induced positive charge carriers in the Schottky layer and induced negative charge carriers in the channel layer (442C), which will affect the properties of the high electron mobility transistors and the MMIC based on them.
A high electron mobility transistor (900), which represents either 840 or 850 in
According to yet another embodiment of this invention, values of the dicing lane edge to composite epitaxial layers HEMT region edge distance (921D, 922D, 923D, 924D) are kept to be substantially greater than 100 μm and more preferably greater than 150 μm, in order to minimize effects of changes in strain and stresses in said composite epitaxial layers HEMT region due to the removal of materials of composite epitaxial layers in the dicing lanes on the electronic performance of the high electron mobility transistor. It should be pointed out that the diagram of
The above-mentioned concept of keeping values of the dicing lane edge to composite epitaxial layers HEMT region edge distances (921D, 922D, 923D, 924D) to be substantially greater than 100 μm may well be adopted to the fabrication of a single high electron mobility transistor, or switching circuits and millimetre wave circuit in order to minimize effects of changes in strain and stresses in the composite epitaxial layers HEMT regions due to dicing or due to the removal of materials of composite epitaxial layers in the dicing lanes on the electronic performance of the high electron mobility transistor.
