Patent Grant
11142844
This disclosure generally relates to the production of single crystal silicon ingots and wafers, the ingots and wafers having low oxygen concentration, high resistivity, and improved mechanical strength.
Single crystal silicon is the starting material in many processes for fabricating semiconductor electronic components and solar materials. For example, semiconductor wafers produced from silicon ingots are commonly used in the production of integrated circuit chips. In the solar industry, single crystal silicon may be used instead of multicrystalline silicon due to the absence of grain boundaries and dislocations. Single crystal silicon ingots are machined into a desired shape, such as a silicon wafer, from which the semiconductor or solar wafers can be produced
Existing methods to produce high-purity single crystal silicon ingot include a float zone method and a magnetic field applied Czochralski (MCZ) process. The float zone method includes melting a narrow region of a rod of ultrapure polycrystalline silicon and slowly translating the molten region along the rod to produce a single crystal silicon ingot of high purity. The MCZ process produces single crystal silicon ingots by melting polycrystalline silicon in a crucible, dipping a seed crystal into the molten silicon, and withdrawing the seed crystal in a manner sufficient to achieve the diameter desired for the ingot. A horizontal and/or vertical magnetic field may be applied to the molten silicon to inhibit the incorporation of impurities, such as oxygen, into the growing single crystal silicon ingot. Although float zone silicon ingots typically contain relatively low concentrations of impurities, such as oxygen, the diameter of ingots grown using the float zone method are typically no larger than about 200 mm due to limitations imposed by surface tension. MCZ silicon ingots may be produced at higher ingot diameters compared to float zone ingots, but MCZ silicon ingots typically contain higher concentrations of impurities.
During the process of producing single crystal silicon ingots using the MCZ method, oxygen is introduced into silicon crystal ingots through a melt-solid or melt crystal interface. The oxygen may cause various defects in wafers produced from the ingots, reducing the yield of semiconductor devices fabricated using the ingots. For example, insulated-gate bipolar transistors (IGBTs), high quality radio-frequency (RF), high resistivity silicon on insulator (HR-SOI), charge trap layer SOI (CTL-SOI), and substrate for GaN epitaxial applications typically require a low oxygen concentration (Oi) in order to achieve high resistivity.
At least some known semiconductor devices are fabricated using float zone silicon materials to achieve a low Oi and high resistivity. However, float zone materials are relatively expensive and are limited to use in producing ingots having a diameter less than approximately 200 mm. Accordingly, float zone silicon materials are expensive and unable to produce higher diameter silicon crystal ingots with a relatively low oxygen concentration.
High quality radio-frequency (RF) devices built on high resistivity silicon on insulator (HR-SOI) require very high resistivity for good second order harmonic performance (HD2). To maintain the high resistivity of the wafer during device fabrication and packaging, a very low Oi is required in order to minimize the thermal donor impact of Oi and to avoid formation of PN junctions. However, the mechanical strength of the low Oi wafer is severely degraded, and these wafers are prone to slip during high temperature process steps in SOI line, EPI reactor, and device fabrication steps. This causes a high yield loss both for SOI wafer manufacturers as well device manufacturer.
This Background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In one embodiments, the present invention is directed to a single crystal silicon wafer comprising: two major, parallel surfaces, one of which is a front surface of the single crystal silicon wafer and the other of which is a back surface of the single crystal silicon wafer, a circumferential edge joining the front and back surfaces of the single crystal silicon wafer, a bulk region between the front and back surfaces, and a central plane of the single crystal silicon wafer between the front and back surfaces of the single crystal silicon wafer, wherein by the bulk region comprises an impurity comprising nitrogen at a concentration of at least about 1×1014 atoms/cm3, germanium at a concentration of at least about 1×1019 atoms/cm3, or a combination nitrogen at a concentration of at least about 1×1014 atoms/cm3 and germanium at a concentration of at least about 1×1019 atoms/cm3, and interstitial oxygen at a concentration of less than about 6 ppma (New ASTM: ASTM F 121, 1980-1983; DIN 50438/1, 1978), and further wherein the main body of the single crystal silicon ingot has a resistivity of at least about 1000 ohm cm.
In one embodiment, the present invention is further directed to a method of growing a single crystal silicon ingot. The method comprises preparing a silicon melt, wherein the silicon melt is prepared by melting polycrystalline silicon in a quartz lined crucible and adding a source of an impurity to the quartz lined crucible, the impurity comprising germanium, nitrogen, or a combination of germanium and nitrogen; and pulling the single crystal silicon ingot from the silicon melt, the single crystal silicon ingot comprising a central axis, a crown, an end opposite the crown, and a main body between the crown and the opposite end, the main body having a lateral surface and a radius, R, extending from the central axis to the lateral surface, wherein the main body of the single crystal silicon ingot comprises nitrogen at a concentration of at least about 1×1014 atoms/cm3, germanium at a concentration of at least about 1×1019 atoms/cm3, or a combination of nitrogen at a concentration of at least about 1×1014 atoms/cm3 and germanium at a concentration of at least about 1×1019 atoms/cm3, further wherein the pulling conditions are sufficient to yield a concentration of interstitial oxygen in the main body of the single crystal silicon ingot of less than about 6 ppma (New ASTM: ASTM F 121, 1980-1983; DIN 50438/1, 1978), and further wherein the main body of the single crystal silicon ingot has a resistivity of at least about 1000 ohm cm.
In one embodiment, the present invention is further directed to a single crystal silicon ingot comprising: a central axis, a crown, an end opposite the crown, and a main body between the crown and the opposite end, the main body having a lateral surface and a radius, R, extending from the central axis to the lateral surface, wherein the main body of the single crystal silicon ingot comprises an impurity comprising nitrogen at a concentration of at least about 1×1014 atoms/cm3, germanium at a concentration of at least about 1×1019 atoms/cm3, or a combination nitrogen at a concentration of at least about 1×1014 atoms/cm3 and germanium at a concentration of at least about 1×1019 atoms/cm3, and interstitial oxygen at a concentration of less than about 6 ppma (New ASTM: ASTM F 121, 1980-1983; DIN 50438/1, 1978), and further wherein the main body of the single crystal silicon ingot has a resistivity of at least about 1000 ohm cm.
Various refinements exist of the features noted in relation to the above-mentioned aspect. Further features may also be incorporated in the above-mentioned aspect as well. These refinements and additional features may exist individually or in any combination. For instance, various features discussed below in relation to any of the illustrated embodiments may be incorporated into the above-described aspect, alone or in any combination.
Like reference symbols in the various drawings indicate like elements.
The method of the present invention is directed to the growth of single crystal silicon ingots under conditions sufficient to product ingots having low oxygen concentration, high resistivity, and improved mechanical strength. The present invention is further directed to single crystal silicon ingots produced by the method, and is still further directed to single crystal silicon wafers sliced from single crystal silicon ingots, the wafers having low oxygen concentration, high resistivity, and improved mechanical strength.
According to some embodiments of the present invention, the crystal growth conditions are sufficient to prepare a single crystal silicon ingot by the Czochralski method, the ingots comprising germanium (Ge) dopant at a concentration of at least about 1×1019 atoms/cm3 and having interstitial oxygen (Oi) at a concentration of less than about 6.0 ppma. According to some embodiments of the present invention, the crystal growth conditions are sufficient to prepare a single crystal silicon ingot by the Czochralski method, the ingots comprising nitrogen (N) dopant at a concentration of at least about 1×1014 atoms/cm3 and having interstitial oxygen (Oi) at a concentration of less than about 6.0 ppma. According to some embodiments of the present invention, the crystal growth conditions are sufficient to prepare a single crystal silicon ingot by the Czochralski method, the ingots comprising nitrogen (N) dopant at a concentration of at least about 1×1014 atoms/cm3 and germanium (Ge) dopant at a concentration of at least about 1×1019 atoms/cm3 and having interstitial oxygen (Oi) at a concentration of less than about 6.0 ppma. Further, the single crystal silicon ingots, and wafers sliced therefrom, have a resistivity of at least about 1000 ohm cm. In preferred embodiments, the ingots are pulled according to the Czochralski (Cz) batch crystal pulling process. Doping a single crystal silicon ingot with germanium advantageously improves the mechanical strength of the ingot, while also not impacting the resistivity of the Si. In some embodiments, nitrogen can be co-doped with Ge to improve mechanical strength without much impact on resistivity. The concentration of Ge and/or N dopant is low enough that the wafer is characterized by low or no thermal donor generation during a thermal process. Additionally, Ge doping does not degrade the second order harmonic performance, which can be degraded by other dopants, such as nitrogen, boron, or metals.
In some embodiments, resistivity may be controlled by selecting high purity polycrystalline silicon with >1000 ohm·cm resistivity and by preparing the melt in a high purity synthetic quartz lined crucible. In some embodiments, a compensating P/N type small quantity dilute dopant may be added to compensate for electrically active impurity to achieve desired resistivity of the crystal. Accordingly, the crystal pulling conditions and materials may be selected to provide a single crystal silicon ingot wherein the main body of the single crystal silicon ingot has a resistivity of at least about 1000 ohm cm, at least about 3000 ohm cm, at least about 4000 ohm cm, at least about 5000 ohm cm, at least about 10000 ohm cm, at least about 15000 ohm cm, or even at least about 20000 ohm cm.
In some embodiments, the interstitial oxygen, Oi, may be controlled to within a required range by puller process optimization. The methodology for manufacturing very low Oi single crystal silicon ingots may include combinations of three key process mechanisms. The three key mechanisms include 1) optimization of crucible inner wall temperature and crucible dissolution, 2) transport of Oi from crucible wall to the growing crystal, and 3) evaporation of SiO from the melt surface to gas phase. The three mechanisms stated above depend strongly on the melt flow conditions established and influenced heavily by the applied magnetic field. In some embodiments, the pulling conditions are sufficient to yield a concentration of interstitial oxygen in the main body of the single crystal silicon ingot of less than about 6 ppma, such as less than about 5 ppma, less than about 4 ppma, or even less than about 3 ppma. These concentrations are according to the New ASTM: ASTM F 121, 1980-1983; DIN 50438/1, 1978.
In some embodiments, germanium may be incorporated into the single crystal silicon ingot by adding a source of germanium, e.g., elemental germanium and/or silicon germanium, to the melt during meltdown process. Germanium is thereby incorporated in the single crystal silicon ingot based on segregation principle. Accordingly, in some embodiments, sufficient germanium, e.g., elemental germanium and/or silicon germanium, may be added to the silicon melt to thereby pull a single crystal silicon ingot wherein the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 1×1019 atoms/cm3, such as at least about 3×1019 atoms/cm3, or at least about 5×1019 atoms/cm3. The main body of the single crystal silicon ingot may comprise germanium at a concentration of less than about 1×1022 atoms/cm3, such as less than about 1×1021 atoms/cm3, or less than about 1×1020 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 1×1019 atoms/cm3 and less than about 1×1022 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 3×1019 atoms/cm3 and less than about 1×1022 atoms/cm3, such as between about 5×1019 atoms/cm3 and less than about 1×1021 atoms/cm3, or between about 5×1019 atoms/cm3 and less than about 1×1020 atoms/cm3.
In some embodiments, nitrogen may be incorporated into the single crystal silicon ingot by adding a source of nitrogen, e.g., silicon nitrogen or nitrogen gas, to the melt during meltdown process. Nitrogen is thereby incorporated in the single crystal silicon ingot based on segregation principle. In some embodiments, the main body of the single crystal silicon ingot comprises nitrogen at a concentration of at least about 1×1014 atoms/cm3, such as at least about 2×1014 atoms/cm3, or at least about 5×1014 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises nitrogen at a concentration of at least about 1×1014 atoms/cm3 and less than about 1×1016 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises nitrogen at a concentration between about 2×1014 atoms/cm3 and less than about 2×1015 atoms/cm3, such as at least about 5×1014 atoms/cm3 and less than about 1×1016 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises nitrogen at a concentration of at least about 1×1015 atoms/cm3 and less than about 1×1016 atoms/cm3.
In some embodiments, germanium may be incorporated into the single crystal silicon ingot by adding a source of germanium, e.g., elemental germanium and/or silicon germanium, and nitrogen may be incorporated into the single crystal silicon ingot by adding a source of nitrogen, e.g., silicon nitrogen or nitrogen gas, to the melt during meltdown process. Accordingly, in some embodiments, sufficient germanium, e.g., elemental germanium and/or silicon germanium, may be added to the silicon melt to thereby pull a single crystal silicon ingot wherein the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 1×1019 atoms/cm3, such as at least about 3×1019 atoms/cm3, or at least about 5×1019 atoms/cm3, and the main body of the single crystal silicon ingot comprises nitrogen at a concentration of at least about 1×1014 atoms/cm3, such as at least about 2×1014 atoms/cm3, or at least about 5×1014 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 1×1019 atoms/cm3 and less than about 1×1022 atoms/cm3 and nitrogen at a concentration of at least about 1×1014 atoms/cm3 and less than about 1×1016 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 3×1019 atoms/cm3 and less than about 1×1022 atoms/cm3 and nitrogen at a concentration of at least about 2×1014 atoms/cm3 and less than about 1×1015 atoms/cm3.
With reference to
With Reference to
Referring again to
Crucible 10 and single crystal 27 have a common axis of symmetry 38. Crucible drive unit 107 can raise crucible 10 along axis 38 as the melt 25 is depleted to maintain melt level 36 at a desired height. A crystal drive unit 121 similarly rotates pull shaft or cable 117 in a direction 110 opposite the direction in which crucible drive unit 107 rotates crucible 10 (e.g., counter-rotation). In embodiments using iso-rotation, crystal drive unit 121 may rotate pull shaft or cable 117 in the same direction in which crucible drive unit 107 rotates crucible 10 (e.g., in the clockwise direction). Iso-rotation may also be referred to as a co-rotation. In addition, crystal drive unit 121 raises and lowers crystal 27 relative to melt level 36 as desired during the growth process.
According to the Czochralski single crystal growth process, a quantity of polycrystalline silicon, or polysilicon, is charged to crucible 10. Additionally, the polycrystalline silicon charge comprises a source of germanium, which may be elemental germanium or silicon germanium, a source of nitrogen, which may be nitrogen gas or silicon nitride, or both a source of germanium and a source of nitrogen in order to dope the single crystal silicon ingot pulled from the melt. Suitable sources of germanium include elemental germanium and silicon germanium. In some embodiments, elemental, pure germanium is purified by a float zone process. The float zone purified Germanium is crushed into small chips/chunks and then used to dope the silicon melt. Silicon germanium may comprise germanium content in a molar ratio generally from about 0.1 to about 0.9. Accordingly, in some embodiments, sufficient Germanium, e.g., elemental germanium and/or silicon germanium, may be added to the silicon melt to thereby pull a single crystal silicon ingot wherein the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 1×1019 atoms/cm3, such as at least about 3×1019 atoms/cm3, or at least about 5×1019 atoms/cm3. The main body of the single crystal silicon ingot may comprise germanium at a concentration of less than about 1×1022 atoms/cm3, such as less than about 1×1021 atoms/cm3, or less than about 1×1020 atoms/cm3. Sufficient germanium is added to the silicon melt so that the resultant main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 1×1019 atoms/cm3 and less than about 1×1022 atoms/cm3, such as at least about 3×1019 atoms/cm3, or between about 5×1019 atoms/cm3 and less than about 1×1021 atoms/cm3, or between about 5×1019 atoms/cm3 and less than about 1×1020 atoms/cm3.
In some embodiments, the polycrystalline silicon charge comprises a source of nitrogen, e.g., silicon nitride and/or nitrogen gas. In some embodiments, sufficient nitrogen may be added so that the main body of the single crystal silicon ingot comprises nitrogen at a concentration of at least about 1×1014 atoms/cm3 and less than about 1×1016 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises nitrogen at a concentration between about 2×1014 atoms/cm3 and less than about 2×1015 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises nitrogen at a concentration of at least about 5×1014 atoms/cm3 and less than about 1×1016 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises nitrogen at a concentration of at least about 1×1015 atoms/cm3 and less than about 1×1016 atoms/cm3.
In some embodiments, the polycrystalline silicon charge comprises a source of germanium and a source of nitrogen. Accordingly, in some embodiments, sufficient germanium, e.g., elemental germanium and/or silicon germanium, may be added to the silicon melt to thereby pull a single crystal silicon ingot wherein the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 1×1019 atoms/cm3, such as at least about 3×1019 atoms/cm3, or at least about 5×1019 atoms/cm3, and sufficient nitrogen may be added to the silicon melt to thereby pull a single crystal silicon ingot comprising nitrogen at a concentration of at least about 1×1014 atoms/cm3, such as at least about 2×1014 atoms/cm3, or at least about 5×1014 atoms/cm3.
A heater power supply 123 energizes resistance heaters 105 and 106, and insulation 125 lines the inner wall of vacuum chamber 101. A gas supply 127 (e.g., a bottle) feeds argon gas to vacuum chamber 101 via a gas flow controller 129 as a vacuum pump 131 removes gas from vacuum chamber 101. An outer chamber 133, which is fed with cooling water from a reservoir 135, surrounds vacuum chamber 101.
The cooling water is then drained to a cooling water return manifold 137. Typically, a temperature sensor such as a photocell 139 (or pyrometer) measures the temperature of melt 25 at its surface, and a diameter transducer 141 measures a diameter of single crystal 27. In this embodiment, system 100 does not include an upper heater. The presence of an upper heater, or lack of an upper heater, alters cooling characteristics of crystal 27.
An upper magnet, such as solenoid coil 31, and a lower magnet, such as solenoid coil 33, are located above and below, respectively, melt level 36 in this embodiment. The coils 31 and 33, shown in cross-section, surround vacuum chamber (not shown) and share axes with axis of symmetry 38. In one embodiment, the upper and lower coils 31 and 33 have separate power supplies, including, but not limited to, an upper coil power supply 149 and a lower coil power supply 151, each of which is connected to and controlled by control unit 143.
In this embodiment, current flows in opposite directions in the two solenoid coils 31 and 33 to produce a magnetic field (as shown in
A control unit 143 is used to regulate the plurality of process parameters including, but not limited to, at least one of crystal rotation rate, crucible rotation rate, and magnetic field strength. In various embodiments, the control unit 143 may include a processor 144 that processes the signals received from various sensors of the system 100 including, but not limited to, photocell 139 and diameter transducer 141, as well as to control one or more devices of system 100 including, but not limited to: crucible drive unit 107, crystal drive unit 121, heater power supply 123, vacuum pump 131, gas flow controller 129 (e.g., an argon flow controller), upper coil power supply 149, lower coil power supply 151, and any combination thereof.
In the example embodiment, system 100 produces single crystal silicon ingots suitable for use in device manufacturing. The single crystal silicon ingot is generally cylindrical and, due to pulling conditions, is capped with a conical crown and a conical end opposite the crown. Accordingly, a single crystal silicon ingot pulled according to the method of the present invention comprises a central axis, a crown, an end opposite the crown, and a main body between the crown and the opposite end, the main body having a lateral surface and a radius, R, extending from the central axis to the lateral surface. Advantageously, system 100 may be used to produce single crystal silicon ingot 27, a substantial portion or all of which is substantially free of agglomerated intrinsic point defects. Furthermore, system 100 may be used to produce single crystal silicon ingot 27 having substantially no agglomerated defects that are larger than approximately one hundred twenty nanometers (nm) in diameter, or more particularly, approximately ninety nm in diameter. The shape of the melt-solid or melt-crystal interface and the pull speed is controlled during crystal growth to limit and/or suppress the formation of agglomerated intrinsic point defects.
During production, oxygen is introduced into single crystal silicon ingots through the melt-solid or melt crystal interface. However, oxygen may cause various defects in wafers produced from the ingots, reducing the yield of semiconductor devices. Accordingly, it is desirable to produce silicon crystal ingots with a low oxygen concentration. Using the methods described herein, single crystal silicon ingots are produced having an oxygen concentration less than approximately 6 ppma, or less than approximately 5 ppma, or less than approximately 4 ppma less than approximately 3 ppma. These concentrations are according to the New ASTM: ASTM F 121, 1980-1983; DIN 50438/1, 1978.
Without being limited to any particular theory, oxygen is introduced into the growing silicon crystal ingot emerging from the melt by an interacting series of events, each of which is influenced by at least one process parameter as described herein below. SiO is introduced into the melt via dissolution at the crucible wall. The SiO introduced at the crucible wall may be moved elsewhere in the melt via flow induced by buoyancy forces created by localized heating of the melt neat the crucible wall. The SiO may be further moved by additional flow induced by the rotation rate of the crystal at the melt-crystal interface as well as rotation rate of the crucible itself. The concentration of SiO in the melt may be reduced via evaporation from the melt at the exposed surface of the melt. The interaction of any combination of dissolution, convection, and evaporation of SiO within the melt influences the concentration of SiO in the melt situated near the crystal-melt interface that is formed into the silicon crystal ingot. In various aspects, any one or more process parameters are simultaneously regulated to reduce the concentration of SiO situated near the melt-crystal interface, and consequently reduce the oxygen concentration within the silicon crystal ingot formed according to the method.
In various embodiments, various process parameters are regulated simultaneously to facilitate producing silicon crystal ingots with a low oxygen concentration. In one embodiment, the various process parameters are regulated in at least two stages that include an intermediate body growth stage corresponding to growth of the silicon crystal ingot up to an intermediate ingot lengths of approximately 800 mm, and a late body growth stage corresponding to growth of the silicon crystal ingot from an intermediate ingot length of approximately 800 mm up to the total ingot length. In this embodiment, the regulation of the various process parameters in at least two different stages accounts for changes in the nature of the interaction of dissolution, convection, evaporation of SiO within the melt, depth of the melt in the crucible, and the flow cells within the melt in the crucible as the silicon crystal ingot grows in length.
In particular, the role of convection is modified over the formation of the entire silicon crystal ingot due to a decrease in the depth of the melt within the crucible associated with growth of the silicon crystal ingot, as described in detail below. As a result, at the late body growth stage, the regulation of at least one process parameter is modified differently relative to the regulation of these same parameters at the intermediate body growth stage. In some embodiments, at the late body growth stage, the regulation of at least three process parameters is modified differently relative to the regulation of these same parameters at the intermediate body growth stage. As described herein below, the regulation of the process parameters modulate various factors related to the convection of SiO within the melt at the late body growth stage. In one embodiment, the process parameters with modified regulation during the late body growth stage include, but are not limited to: seed rotation rate, crucible rotation rate, and magnetic field strength.
Referring again to
As described herein, the transition from an intermediate to a late body growth stage is a soft transition. The transition may vary depending on various parameters of the process, such as crucible size, shape, depth of melt, modeling parameters, and the like. Generally, at the intermediate body growth stage, parameters are such that there are limited or no interactions between fluid motion induced by crystal flow cell 18 and buoyancy flow cell 17; the crystal flow cell 18 and buoyancy flow cell 17 are effectively decoupled. At the late body growth stage, parameters are such that there are interactions between fluid motion induced by crystal flow cell 18 and buoyancy flow cell 17; the crystal flow cell 18 and buoyancy flow cell 17 are effectively coupled. By way of non-limiting example, late body growth stage occurs when less than about 37% of the initial mass of melt 25 is left in crucible 10 in an embodiment that includes an initial melt mass between 180 kg to 450 kg in a crucible 10 with an inner diameter of about 36 inches. In various embodiments, depth 200 of melt 25 within crucible 10 is monitored to identify the transition from the intermediate to a late body growth stage. In other examples, the late body growth stage occurs when less than about 35%, less than about 40%, less than about 45%, or less than about 50% of the initial mass of melt 25 is left in crucible 10. In some embodiments, the transition from intermediate to late body growth stage is determined based on the depth of melt 25, or any other suitable parameter.
In various embodiments, the method includes regulating the seed rotation rate in at least two stages including, but not limited to, the intermediate body growth stage and the late body growth stage. In one embodiment, the method includes rotating crystal 27 during the intermediate body growth stage at a seed rotation rate ranging from approximately 8 to 14 rpm, and more specifically 12 rpm. In this embodiment, the method further includes reducing the seed rotation rate at the late body growth stage to a seed rotation rate ranging from approximately 6 rpm to 8 rpm, and more specifically 8 rpm.
In another embodiment, the seed rotation rate may be reduced according to the intermediate ingot length. By way of non-limiting example, the seed rotation rate may be regulated to approximately 12 rpm for intermediate ingot lengths up to approximately 850 mm, and may be further regulated to linearly decrease to approximately 8 rpm at an intermediate ingot length of approximately 950 mm, and then regulate seed rotation rate at approximately 8 rpm up to the total ingot length, as illustrated in
Crucible rotation rate may further influence the oxygen concentrations within crystals 27 formed according to embodiments of the method. Crucible rotation rate refers to the rate at which crucible 10 is rotated about axis 38 using crucible drive unit 107. Crucible rotation rate impacts the flow of SiO from crucible 10 to crystal 27 and an amount of SiO evaporating from melt 25. A high crucible rotation rate reduces both a boundary layer thickness between crucible 10 and melt 25, and a boundary layer thickness between melt line 36 and the gas above melt 25. However, to minimize the oxygen concentration in crystal 27, a thicker boundary layer between crucible 10 and melt 25 is desired to reduce the SiO transport rate, while a thinner boundary layer between melt line 36 and the gas above melt 25 is desired to increase the SiO evaporation rate. Accordingly, the crucible rotation rate is selected to balance the competing interests of a high boundary layer thickness between crucible 10 and melt 25 resulting from slower crucible rotation rates and a low boundary layer thickness between melt line 36 and the gas above melt 25 resulting from higher crucible rotation rates.
Changes in depth 200 of melt 10 between intermediate body growth stage and late body growth stage described herein above influence the impact of modulation of crucible rotation rate on oxygen concentration in a manner similar to the influence of seed rotation rate described herein previously. In various embodiments, the method includes regulating the crucible rotation rate in at least two stages including, but not limited to, the intermediate body growth stage and the late body growth stage. In one embodiment, the method includes rotating crucible 10 at the intermediate body growth stage at a crucible rotation rate ranging from approximately 1.3 rpm to approximately 2.2, and more specifically 1.7 rpm. In this embodiment, the method further includes reducing the crucible rotation rate at the late body growth stage to a crucible rotation rate ranging from approximately 0.5 rpm to approximately 1.0 rpm, and more specifically 1 rpm.
The method may further include regulating magnet strength in at least two stages including, but not limited to, the intermediate body growth stage and the late body growth stage. Magnet strength refers to the strength of the cusped magnetic field within the vacuum chamber. More specifically, magnet strength is characterized by a current through coils 31 and 33 that is controlled to regulate magnetic strength. Magnetic strength impacts the flow of SiO from crucible 10 to crystal 27. That is, a high magnetic strength minimizes the flow of SiO from crucible 10 to crystal 27 by suppressing a buoyancy force within melt 25. As the magnetic field suppresses the buoyancy flow, it decreases the dissolution rate of the quartz crucible, thus lowering the interstitial oxygen incorporated into the crystal. However, if the magnetic field strength increases beyond a certain level, further retardation in the buoyancy flow may result in decreasing the evaporation rate at the melt free surface, thus raising the interstitial oxygen levels. Due to differences in the relative contribution of buoyancy flow to the oxygen content of the crystal at the late body formation stage relative to the intermediate body formation stage as described previously herein, an adjustment to the magnet strength at the late body formation stage enables appropriate modulation of buoyancy flow to reduce oxygen within the crystal formed at the late body formation stage.
In various embodiments, the method includes regulating the magnetic field strength in at least two stages including, but not limited to, the intermediate body growth stage and the late body growth stage. In one embodiment, the method includes regulating the magnetic field strength at the intermediate body growth stage such that the magnetic field strength is approximately 0.02 to 0.05 Tesla (T) at an edge of crystal 27 at the melt-solid interface and approximately 0.05 to 0.12 T at the wall of crucible 10. In another aspect, the method includes regulating the magnetic field strength at the late body growth stage such that the magnetic field strength is approximately 150% of the magnetic field strength used during the intermediate body growth stage, corresponding to approximately 0.03 to 0.075 Tesla (T) at an edge of crystal 27 at the melt-solid interface and approximately 0.075 to 0.18 Tat the wall of crucible 10.
One or more additional process parameters may be regulated to facilitate producing silicon crystal ingots with a low oxygen concentration. However, the effects of these additional process parameters are not sensitive to the changes in the depth 200 of melt 25 within crucible 10 during growth of crystal 27. Consequently, the regulation of the additional process parameters described herein remains essentially the same between different stages of crystal growth, as described in additional detail below.
One additional process parameter that is controlled, at least in some embodiments, is wall temperature of crucible 10. The wall temperature of crucible 10 corresponds to a dissolution rate of crucible 10. Specifically, the higher the wall temperature of crucible 10, the faster that portions of crucible 10 will react with and dissolve into melt 25, generating SiO into the melt and potentially increasing an oxygen concentration of crystal 27 via the melt-crystal interface. Accordingly, reducing the wall temperature of crucible 10, as used herein, equates to reducing the dissolution rate of crucible 10. By reducing the wall temperature of crucible 10 (i.e., reducing the dissolution rate of crucible 10), the oxygen concentration of crystal 27 can be reduced. Wall temperature may be regulated by controlling one or more additional process parameters including, but not limited to heater power and melt to reflector gap.
Heater power is another process parameter that may be controlled in some embodiments to regulate the wall temperature of crucible 10. Heater power refers to the power of side and bottom heaters 105 and 106. Specifically, relative to typical heating configurations, by increasing a power of side heater 105 and reducing a power of bottom heater 106, a hot spot on the wall of crucible 10 is raised close to the melt line 36. As the wall temperature of crucible 10 at or below melt line 36 is lower, the amount of SiO generated by melt 25 reacting with crucible 10 is also lower. The heater power configuration also impacts melt flow by reducing the flow (i.e., transport) of SiO from crucible 10 to single crystal 27. In this embodiment, a power of bottom heater 106 is approximately 0 to 5 kilowatts, and more specifically approximately 0 kilowatts, and a power of side heater 105 is in a range from approximately 100 to 125 kilowatts. Variations in the power of side heater 105 may be due to, for example, variation in a hot zone age from puller to puller.
In some embodiments, melt to reflector gap is an additional process parameter that is controlled to regulate the wall temperature of crucible 10. Melt to reflector gap refers to a gap between melt line 36 and a heat reflector (not shown). Melt to reflector gap impacts the wall temperature of crucible 10. Specifically, a larger melt to reflector gap reduces the wall temperature of crucible 10. In this embodiment, the melt to reflector gap is between approximately 60 mm and 80 mm, and more specifically 70 mm.
Seed lift is an additional process parameter that is controlled to regulate the flow of SiO from crucible 10 to crystal 27. Seed lift refers to the rate at which pull shaft or cable 117 lifts seed crystal 115 out of melt 25. In one embodiment, seed crystal 115 is lifted at a rate between about 0.4 mm/min and about 0.7 mm/min, for example, in a range of approximately 0.42 to 0.55 millimeters per minute (mm/min), and more specifically 0.46 mm/min for 300 mm product. This pull rate is slower than pull rates typically used for smaller diameter (e.g., 200 mm) crystals. For example, the seed lift for 200 mm product may between about 0.55 mm/min and about 0.95 mm/min, such as in a range of approximately 0.55 to 0.85 mm/min, and more specifically 0.7 mm/min.
Pull speed is an additional process parameter that may be regulated to control the defect quality of the crystal. For example, using SP2 laser light scattering, the detected agglomerated point defects generated by the process described herein may be less than 400 counts for defects less than 60 nm, less than 100 counts for defects between 60 and 90 nm, and less than 100 counts for less defects between 90 and 120 nm.
In some embodiments, inert gas flow is an additional process parameter that is controlled to regulate the SiO evaporation from melt 25. Inert gas flow, as described herein, refers to the rate at which argon gas flows through vacuum chamber 101. Increasing the argon gas flow rate sweeps more SiO gas above melt line 36 away from crystal 27, minimizing a SiO gas partial pressure, and in turn increasing SiO evaporation. In this embodiment, the argon gas flow rate is in a range from approximately 100 slpm to 150 slpm.
Inert gas pressure is an additional process parameter also controlled to regulate the SiO evaporation from melt 27 in some embodiments. Inert gas pressure, as described herein, refers to the pressure of the argon gas flowing through vacuum chamber 101. Decreasing the argon gas pressure increases SiO evaporation and hence decreases SiO concentration in melt 25. In this embodiment, the argon gas pressure ranges from approximately 10 torr to 30 torr.
In suitable embodiments, cusp position is an additional process parameter that is controlled to regulate the wall temperature of crucible 10 and the flow of SiO from crucible 10 to crystal 27. Cusp position, as described herein, refers to the position of the cusp of the magnetic field generated by coils 31 and 33. Maintaining the cusp position below melt line 36 facilitates reducing the oxygen concentration. In this embodiment, the cusp position is set in a range from approximately 10 mm to 40 mm below melt line 36, more specifically, in a range of approximately 25 mm to 35 mm below melt line 36, and even more specifically, at approximately 30 mm.
By controlling process parameters (i.e., heater power, crucible rotation rate, magnet strength, seed lift, melt to reflector gap, inert gas flow, inert gas pressure, seed rotation rate, and cusp position) as described above, a plurality of process parameters (i.e., a wall temperature of a crucible, a flow of SiO from the crucible to a single crystal, and an evaporation of SiO from a melt) are regulated to produce single crystal silicon ingots having a low oxygen concentration. In one embodiment, the methods described herein facilitate producing a silicon ingot with an ingot diameter greater than approximately 150 millimeters (mm), a total ingot length of at least approximately 900 mm, and an oxygen concentration less than 6 ppma, such as less than about 5 ppma, less than about 4 ppma, or even less than about 3 ppma. In another embodiment, the methods described herein facilitate producing a silicon ingot with an ingot diameter ranging from approximately 150 mm to 460 mm, specifically approximately 300 mm, and an oxygen concentration less than 6 ppma, such as less than about 5 ppma, less than about 4 ppma, or even less than about 3 ppma. In another additional embodiment, the methods described herein facilitate producing a silicon ingot with a total ingot length ranging from approximately 900 mm to 1200 mm, and an oxygen concentration less than 6 ppma, such as less than about 5 ppma, less than about 4 ppma, or even less than about 3 ppma. These concentrations are according to the New ASTM: ASTM F 121, 1980-1983; DIN 50438/1, 1978.
A single crystal silicon wafer may be sliced according to conventional techniques from a single crystal silicon ingot or slug prepared according to the method of the present invention. In general, a single crystal silicon wafer comprises two major, parallel surfaces, one of which is a front surface of the single crystal silicon wafer and the other of which is a back surface of the single crystal silicon wafer, a circumferential edge joining the front and back surfaces of the single crystal silicon wafer, a bulk region between the front and back surfaces, and a central plane of the single crystal silicon wafer between the front and back surfaces of the single crystal silicon wafer. Wafers then undergo conventional processing. Accordingly, any sharp, fragile edges are rounded or “profiled” to provide strength and stability to the wafer. This will ultimately prevent chipping or breakage in subsequent processing. Next, each wafer is laser-marked with very small alphanumeric or bar code characters. This laser-mark ID gives full trace-ability to the specific date, machine, and facility where the wafers were manufactured. The wafers are then loaded into a precision “lapping” machine that uses pressure from rotating plates and an abrasive slurry to ensure a more uniform, simultaneous removal of saw damage present on both front and backside surfaces. This step also provides stock removal and promotes flatness uniformity. Now the wafers must go through an “etching” cycle. Chemical etching is necessary for the removal of residual surface damage caused by lapping; it also provides some stock removal. During the etching cycle, wafers progress down another series of chemical baths and rinse tanks with precise fluid dynamics. These chemical solutions produce a flatter, stronger wafer with a glossy finish. All wafers are then sampled for mechanical parameters and for process feedback.
Single crystal silicon wafers having low oxygen concentration (i.e., less than about 6 ppma, less than about 5 ppma, less than about 4 ppma, or even less than about 3 ppma) using the systems and methods described herein may be advantageous in a variety of applications. For example, insulated-gate bipolar transistors (IGBTs), high quality radio-frequency (RF), high resistivity silicon on insulator (HR-SOI), charge trap layer SOI (CTL-SOI), and substrate for GaN EPI applications may benefit from the low oxygen concentration because they achieve high resistivity and do not have p-n junctions. In some embodiments, the resistivity of a single crystal silicon wafer is at least about 3000 ohm cm, such as at least about 4000 ohm cm, at least about 5000 ohm cm, at least about 10000 ohm cm, such as at least about 15000 ohm cm, or even at least about 20000 ohm cm. Wafers produced for IGBT applications using the methods described herein may, for example, have 30 to 300 ohm-centimeter (ohm-cm) N-type resistivity or greater than 750 ohm-cm N/P-type resistivity. Further, wafers produced for radiofrequency (RF), high resistivity silicon on insulator (HR-SOI), charge trapping layer SOI (CTL-SOI). and/or GaN EPI applications using the methods described herein may have, for example, greater than 750 ohm-cm P-type wafers, or at least about 3000 ohm cm, such as at least about 4000 ohm cm, at least about 5000 ohm cm, at least about 10000 ohm cm, such as at least about 15000 ohm cm, or even at least about 20000 ohm cm. Wafers produced by the described systems and methods may also be used as handle wafers. For P-type wafers produced using the methods described herein, boron, aluminum, gallium, and/or indium may be suitably used has a majority carrier, and red phosphorus, phosphorus, arsenic, and/or antimony may be used as a minority carrier. For N-type wafers produced using the methods described herein, red phosphorus, phosphorus, arsenic, and/or antimony may be used as the majority carrier, and boron, aluminum, gallium, and/or indium may be used as the minority carrier.
To improve mechanical strength and slip performance, wafers produced using the methods described are co-doped (e.g., by doping the single crystal that forms the ingot) with germanium and/or nitrogen. Germanium may be incorporated into the single crystal silicon ingot by adding a source of germanium, e.g., elemental germanium and/or silicon germanium, to the melt during meltdown process. Germanium is thereby incorporated in the solid crystal form based on segregation principle. Accordingly, in some embodiments, single crystal silicon wafers sliced from ingots pulled according to the method of the present invention comprise germanium at a concentration of at least about 1×1019 atoms/cm3, such as at least about 3×1019 atoms/cm3, or at least about 5×1019 atoms/cm3. The single crystal silicon wafers sliced from ingots pulled according to the method of the present invention may comprise germanium at a concentration of less than about 1×1022 atoms/cm3, such as less than about 1×1021 atoms/cm3, or less than about 1×1020 atoms/cm3. In some embodiments, the single crystal silicon wafers comprise germanium at a concentration of at least about 1×1019 atoms/cm3 and less than about 1×1022 atoms/cm3. In some embodiments, the single crystal silicon wafers comprise germanium at a concentration of at least about 5×1019 atoms/cm3 and less than about 1×1022 atoms/cm3. Single crystal silicon wafers sliced from the main body portion of the single crystal silicon ingots comprises germanium within these concentration ranges.
In some embodiments, nitrogen may be incorporated into the single crystal silicon ingot by adding a source of nitrogen, e.g., silicon nitrogen or nitrogen gas, to the melt during meltdown process. In addition to improving mechanical strength, nitrogen dopant may interact with Oi in order to partially alter the electrical property of the wafers by forming thermal donors. This electrical property may be a function of temperature, as the generation and killing temperature of such species are different for each individual species. The thermal donor generated by O—O, N—O, Ge—O have different thermal stability. For example, N—O thermal donor is found to be generated around 600° C. and may be stable up <900° C. Thus to dissociate the N—O thermal donor, a >900° C. thermal donor kill (TDK) step may be required to control the resistivity of the wafers. Alternatively, in absence of such TDK process step, the doping of the crystal may be adjusted to compensate for the resistivity shift by TD, to achieve target resistivity. In some embodiments, the single crystal silicon ingot is co-doped with germanium and nitrogen. In some embodiments, the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 1×1019 atoms/cm3, at least about 3×1019 atoms/cm3, such as at least about 5×1019 atoms/cm3 and nitrogen at a concentration of at least about 1×1014 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 1×1019 atoms/cm3 and less than about 1×1022 atoms/cm3 and nitrogen at a concentration of at least about 1×1014 atoms/cm3 and less than about 1×1016 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises nitrogen at a concentration of at least about 5×1014 atoms/cm3 and less than about 1×1016 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises nitrogen at a concentration of at least about 2×1014 atoms/cm3 and less than about 1×1015 atoms/cm3. In some embodiments, the main body of the single crystal silicon ingot comprises germanium at a concentration of at least about 3×1019 atoms/cm3 and less than about 1×1022 atoms/cm3 and nitrogen at a concentration of at least about 1×1015 atoms/cm3 and less than about 1×1016 atoms/cm3. Single crystal silicon wafers sliced from the main body portion of the single crystal silicon ingots comprise germanium and nitrogen within these concentration ranges.
Example systems and methods of producing single crystal silicon ingots with relatively low oxygen concentration from a melt formed from polycrystalline silicon are described herein. These methods take advantage of changes in the structure of flow cells in the melt between a first and second stage of production of the ingot to produce relatively low oxygen silicon. During the first stage, the silicon ingot is relatively small and the depth of the melt is relatively deep. The second stage is characterized by a depleted melt depth within the crucible due to formation of the silicon ingot. In this second stage, a flow cell induced by rotation of the silicon ingot within the melt may contact the bottom of the crucible, causing unwanted inclusion of silicon oxide formed at the crucible bottom into the growing crystal ingot. The methods and systems described herein control production of the ingot to limit the including of the unwanted silicon oxide. Generally, at least one process parameter is changed during the second stage relative to its value during the first stage. Non-limiting examples of changes in process parameters from the first stage to the second stage include: reduced crystal rotation rate, reduced crucible rotation rate, increased magnetic field strength, and any combination thereof. For example, in some embodiments, the silicon ingot is rotated more slowly during the second stage to reduce contact of the rotation induced flow cell with the bottom of the crucible, and thereby reduce the amount oxygen included in the silicon ingot.
The systems and methods described herein enable the formation of single crystal silicon ingots with low oxygen concentration maintained over a longer ingot length than was achieved using previous methods. A detailed description of the effects of these changes in process parameters on the structure of flow cells within the crucible and the oxygen content of the silicon ingots formed using the method on various embodiments, are described in further detail herein.
Embodiments of the methods described herein achieve superior results compared to prior methods and systems. For example, the methods described herein facilitate producing silicon ingots with a lower oxygen concentration than at least some known methods. Further, unlike at least some known methods, the methods described herein may be used for the production of ingots having a diameter greater than 150 mm, such as about 300 mm.
Additionally, incorporation of germanium impurity and/or nitrogen impurity, into the low oxygen content, high resistivity wafers improves mechanical strength in wafers normally suffering from degraded mechanical strength and susceptible to wafer slip during high temperature operations. The fracture strength of germanium doped low oxygen wafers may be improved both as grown and post anneal. Another advantage of germanium doping is lowered thermal donor formation, thereby reducing the free carrier concentration and enabling higher resistivity wafers. Still further, germanium doping in single crystal silicon ingots and wafers can effectively suppress void defects. The Germanium dopant atoms combine with vacancies, thereby suppressing vacancy aggregation necessary to form voids. An additional effect of vacancy combination is strain relaxation originating from the mismatch of Ge atoms in silicon crystal lattice. The reduction of free vacancies leads to suppression of grown-in voids and decreases the formation temperature and thus the size of voids, leading to poorer thermal stability of voids. In addition, germanium doping in single crystal silicon ingots and wafers improves the formation of denuded zone (DZ, i.e. a region of low or no oxygen precipitation) in the near surface region can be achieved under one-step high temperature annealing, as a result of germanium enhancing oxygen precipitation in the bulk region and the out-diffusion of oxygen in the near surface region.
In addition, both N and Ge doping in Si crystals can effectively suppress void defects and reduce the concentration of free vacancies significantly (J. Cry. Growth 243 (2002) 371-374). Thus during crystal growth, it can be pulled faster for the same defect concentration compared to conventional processes, thus improving throughput of the process. This is particularly helpful for a charge trap layer SOI application (CTL-SOI), where, a poly-silicon based charge trap layer is added between high resistivity low oxygen handle and P type donor wafer. Due to the presence of poly-silicon layer, high density of crystal defect (COP) may be allowed on the handle wafers without disruption of the process flow during device manufacturing (in particular during LLS inspection).
Wafers sliced from ingots prepared according to the method of the present invention are suitable for use as a handle wafer and/or a donor wafer in the manufacture of silicon on insulator structures. Semiconductor wafers (e.g., silicon wafers) may be utilized in the preparation of composite layer structures. A composite layer structure (e.g., a semiconductor-on-insulator, and more specifically, a silicon-on-insulator (SOI) structure) generally comprises a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Generally, the device layer is between 0.01 and 20 micrometers thick, such as between 0.05 and 20 micrometers thick. Thick film device layers may have a device layer thickness between about 1.5 micrometers and about 20 micrometers. Thin film device layers may have a thickness between about 0.01 micrometer and about 0.20 micrometer. In general, composite layer structures, such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz, are produced by placing two wafers in intimate contact, thereby initiating bonding by van der Waal's forces, followed by a thermal treatment to strengthen the bond. The anneal may convert the terminal silanol groups to siloxane bonds between the two interfaces, thereby strengthening the bond.
After thermal anneal, the bonded structure undergoes further processing to remove a substantial portion of the donor wafer to achieve layer transfer. For example, wafer thinning techniques, e.g., etching or grinding, may be used, often referred to as back etch SOI (i.e., BESOI), wherein a silicon wafer is bound to the handle wafer and then slowly etched away until only a thin layer of silicon on the handle wafer remains. See, e.g., U.S. Pat. No. 5,189,500, the disclosure of which is incorporated herein by reference as if set forth in its entirety. This method is time-consuming and costly, wastes one of the substrates and generally does not have suitable thickness uniformity for layers thinner than a few microns.
Another common method of achieving layer transfer utilizes a hydrogen implant followed by thermally induced layer splitting. Particles (atoms or ionized atoms, e.g., hydrogen atoms or a combination of hydrogen and helium atoms) are implanted at a specified depth beneath the front surface of the donor wafer. The implanted particles form a cleave plane in the donor wafer at the specified depth at which they were implanted. The surface of the donor wafer is cleaned to remove organic compounds or other contaminants, such as boron compounds, deposited on the wafer during the implantation process.
The front surface of the donor wafer is then bonded to a handle wafer to form a bonded wafer through a hydrophilic bonding process. Prior to bonding, the donor wafer and/or handle wafer are activated by exposing the surfaces of the wafers to plasma containing, for example, oxygen or nitrogen. Exposure to the plasma modifies the structure of the surfaces in a process often referred to as surface activation, which activation process renders the surfaces of one or both of the donor water and handle wafer hydrophilic. The surfaces of the wafers can be additionally chemically activated by a wet treatment, such as an SC1 clean or hydrofluoric acid. The wet treatment and the plasma activation may occur in either order, or the wafers may be subjected to only one treatment. The wafers are then pressed together, and a bond is formed there between. This bond is relatively weak, due to van der Waal's forces, and must be strengthened before further processing can occur.
In some processes, the hydrophilic bond between the donor wafer and handle wafer (i.e., a bonded wafer) is strengthened by heating or annealing the bonded wafer pair. In some processes, wafer bonding may occur at low temperatures, such as between approximately 300° C. and 500° C. In some processes, wafer bonding may occur at high temperatures, such as between approximately 800° C. and 1100° C. The elevated temperatures cause the formation of covalent bonds between the adjoining surfaces of the donor wafer and the handle wafer, thus solidifying the bond between the donor wafer and the handle wafer. Concurrently with the heating or annealing of the bonded wafer, the particles earlier implanted in the donor wafer weaken the cleave plane.
A portion of the donor wafer is then separated (i.e., cleaved) along the cleave plane from the bonded wafer to form the SOI wafer. Cleaving may be carried out by placing the bonded wafer in a fixture in which mechanical force is applied perpendicular to the opposing sides of the bonded wafer in order to pull a portion of the donor wafer apart from the bonded wafer. According to some methods, suction cups are utilized to apply the mechanical force. The separation of the portion of the donor wafer is initiated by applying a mechanical wedge at the edge of the bonded wafer at the cleave plane in order to initiate propagation of a crack along the cleave plane. The mechanical force applied by the suction cups then pulls the portion of the donor wafer from the bonded wafer, thus forming an SOI wafer. The donor can recycled for multiple uses as SOI donor wafer.
According to other methods, the bonded pair may instead be subjected to an elevated temperature over a period of time to separate the portion of the donor wafer from the bonded wafer. Exposure to the elevated temperature causes initiation and propagation of cracks along the cleave plane, thus separating a portion of the donor wafer. The crack forms due to the formation of voids from the implanted ions, which grow by Ostwald ripening. The voids are filled with hydrogen and helium. The voids become platelets. The pressurized gases in the platelets propagate micro-cavities and micro-cracks, which weaken the silicon on the implant plane. If the anneal is stopped at the proper time, the weakened bonded wafer may be cleaved by a mechanical process. However, if the thermal treatment is continued for a longer duration and/or at a higher temperature, the micro-crack propagation reaches the level where all cracks merge along the cleave plane, thus separating a portion of the donor wafer. This method allows recycle of the donor wafer, but typically requires heating the implanted and bonded pair to temperatures approaching 500° C.
The use of high resistivity semiconductor-on-insulator (e.g., silicon-on-insulator) wafers for RF related devices such as antenna switches offers benefits over traditional substrates in terms of cost and integration. To reduce parasitic power loss and minimize harmonic distortion inherent when using conductive substrates for high frequency applications it is necessary, but not sufficient, to use substrate wafers with a high resistivity. Accordingly, the resistivity of the handle wafer for an RF device is generally greater than about 500 Ohm-cm. As a handle wafer, wafers prepared according to the method of the present invention are particularly suitable for high resistivity SOI structures for use in RF devices. An HR-SOI structure may comprise a high resistivity handle wafer having a low oxygen concentration, high resistivity, and be doped with germanium for improved mechanical strength. Accordingly, some embodiments of the present invention are directed to an HR-SOI structure comprising a Ge-doped handle wafer, a dielectric layer (generally, a buried silicon oxide layer or BOX), and a device layer.
Such a substrate is prone to formation of high conductivity charge inversion or accumulation layers at the BOX/handle interface causing generation of free carriers (electrons or holes), which reduce the effective resistivity of the substrate and give rise to parasitic power losses and device nonlinearity when the devices are operated at RF frequencies. These inversion/accumulation layers can be due to BOX fixed charge, oxide trapped charge, interface trapped charge, and even DC bias applied to the devices themselves.
A method is required therefore to trap the charge in any induced inversion or accumulation layers so that the high resistivity of the substrate is maintained even in the very near surface region. It is known that charge trapping layers (CTL) between the high resistivity handle substrates and the buried oxide (BOX) may improve the performance of RF devices fabricated using SOI wafers. A number of methods have been suggested to form these high interface trap layers. For example, one of the method of creating a semiconductor-on-insulator (e.g., a silicon-on-insulator, or SOI) with a CTL for RF device applications is based on depositing an undoped polycrystalline silicon film on a silicon substrate having high resistivity and then forming a stack of oxide and top silicon layer on it. A polycrystalline silicon layer acts as a high defectivity layer between the silicon substrate and the buried oxide layer. An alternative method is the implantation of heavy ions to create a near surface damage layer. Devices, such as radiofrequency devices, are built in the top silicon layer.
It has been shown in academic studies that the polycrystalline silicon layer in between of the oxide and substrate improves the device isolation, decreases transmission line losses and reduces harmonic distortions. See, for example: H. S. Gamble, et al. “Low-loss CPW lines on surface stabilized high resistivity silicon,” Microwave Guided Wave Lett., 9(10), pp. 395-397, 1999; D. Lederer, R. Lobet and J.-P. Raskin, “Enhanced high resistivity SOI wafers for RF applications,” IEEE Intl. SOI Conf., pp. 46-47, 2004; D. Lederer and J.-P. Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increased substrate resistivity,” IEEE Electron Device Letters, vol. 26, no. 11, pp. 805-807, 2005; D. Lederer, B. Aspar, C. Laghaé and J.-P. Raskin, “Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate,” IEEE International SOI Conference, pp. 29-30, 2006; and Daniel C. Kerr et al. “Identification of RF harmonic distortion on Si substrates and its reduction using a trap-rich layer”, Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008 (IEEE Topical Meeting), pp. 151-154, 2008.
In some embodiments, the high resistivity, low oxygen, germanium doped wafers are suitable substrates for epitaxial deposition. The epitaxial deposition preferably is carried out by chemical vapor deposition. Generally speaking, chemical vapor deposition involves exposing the surface of the wafer to an atmosphere comprising silicon in an epitaxial deposition reactor, e.g., a Centura reactor available from Applied Materials. Preferably, the surface of the wafer is exposed to an atmosphere comprising a volatile gas comprising silicon (e.g., SiCl4, SiHCl3, SiH2Cl2, SiH3Cl, or SiH4). The atmosphere also preferably contains a carrier gas (preferably H2). For example, the source of silicon during the epitaxial deposition may be SiH2Cl2 or SiH4. If SiH2Cl2 is used, the reactor vacuum pressure during deposition preferably is from about 500 to about 760 Torr. If, on the other hand, SiH4 is used, the reactor pressure preferably is about 100 Torr. Most preferably, the source of silicon during the deposition is SiHCl3. This tends to be much cheaper than other sources. In addition, an epitaxial deposition using SiHCl3 may be conducted at atmospheric pressure. This is advantageous because no vacuum pump is required and the reactor chamber does not have to be as robust to prevent collapse. Moreover, fewer safety hazards are presented and the chance of air or other gases leaking into the reactor chamber is lessened.
During the epitaxial deposition, the temperature of the wafer surface preferably is ramped to and maintained at a temperature sufficient to prevent the atmosphere comprising silicon from depositing polycrystalline silicon on the surface. Generally, the temperature of the surface during this period preferably is at least about 900° C. More preferably, the temperature of the surface is maintained in the range of between about 1050 and about 1150° C. Most preferably, the temperature of the surface is maintained at the silicon oxide removal temperature.
The rate of growth of the epitaxial deposition preferably is from about 0.5 to about 7.0 μm/min. A rate of about 3.5 to about 4.0 μm/min may be achieved, for example, by using an atmosphere consisting essentially of about 2.5 mole % SiHCl3 and about 97.5 mole % H2 at a temperature of about 1150° C. and an absolute pressure of up to about 1 atm.
In some applications, the wafers comprise an epitaxial layer which imparts electrical properties. In some embodiments, the epitaxial layer is lightly doped with phosphorous. Therefore, the ambient for epitaxial deposition comprises phosphorous present as a volatile compound, such as, for example, phosphine, PH3. In some embodiments, the epitaxial layer can contain boron. Such a layer may be prepared by, for example, including B2H6 in the atmosphere during the deposition.
A deposited epitaxial layer may comprise substantially the same electrical characteristics as the underlying wafer. Alternatively, the epitaxial layer may comprise different electrical characteristics as the underlying wafer. An epitaxial layer may comprise a material selected from the group consisting of silicon, silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Depending upon the desired properties of the final integrated circuit device, the epitaxial layer may comprise a dopant selected from the group consisting of boron, arsenic, and phosphorus. The resistivity of the epitaxial layer may range from 1 to 50 Ohm-cm, typically, from 5 to 25 Ohm-cm. In some embodiments, the epitaxial layer may have a thickness between about 20 nanometers and about 3 micrometers, such as between about 20 nanometers and about 2 micrometers, such as between about 20 nanometers and about 1.5 micrometers or between about 1.5 micrometers and about 3 micrometers.
In some embodiments, the high resistivity, low oxygen, germanium doped wafers are suitable substrates for gallium nitride epitaxial deposition, such as by molecular beam epitaxy. GaN molecular beam epitaxy (MBE) growth is a non-equilibrium process where a Ga vapor beam from an effusion cell and an activated nitrogen beam from a plasma source are directed toward a heated substrate. Under suitable conditions, layer-by-layer deposition of Ga and N atomic planes is possible. The MBE procedure is performed in an ultra-high vacuum chamber, minimizing film contamination.
The following non-limiting Examples are provided to further illustrate the present invention.
A germanium doped single crystal silicon short ingot (crystal ID #1) and a germanium doped single crystal silicon full length ingot (crystal ID #2) were produced in a 200 mm FF furnace (SunEdison, S. Korea). Polycrystalline silicon and germanium were charged to a high purity quartz lined synthetic crucible (Toshiba). The charge for preparing the germanium doped single crystal silicon full length ingot (crystal ID #2) comprised 1.3 kg of 5N grade germanium and 180 kg of high resistivity polycrystalline silicon (>1000 Ohm·Cm). Additionally, 0.024 grams of phosphorus was added to the melt to provide a phosphorus dopant concentration of about 1.1×106 ppba. The charge was melted and a crystal was pulled according to the techniques disclosed herein. The single crystal silicon ingot was targeted for >16,000 Ohm·Cm resistivity by adjusting the dopant concentration in the melt before starting the crystal growth process. This was based on resistivity of the melt calculated by growing a short crystal with <200 mm diameter and <15 kg wt. The single crystal silicon ingot comprises <5.0 ppma Oi.
The germanium doped single crystal silicon full length ingot (crystal ID #2) prepared according to Example 1 was subjected to a thermal anneal procedure. Prior to anneal the pulled ingot, the pulled ingot was cropped by removing the seed and end cones. For analysis, the ingot was sliced at different positions, thereby preparing multiple slugs having a thickness of about 1350 micrometers. Each cropped slug was edge ground and subjected to a mixed acid etch to a final thickness of about 1180 micrometers, which was followed by lapped wafer cleaning to a final thickness of 1150 micrometers and pre-RTA clean. The slug was subjected to a thermal donor kill in a rapid thermal anneal at 750° C. at a temperature ramp of 360° C./minute. After lapping and anneal, the annealed slugs were cooled and held for four hours before four point probe measurement. The annealed slug was subjected to a four point probe measurement technique for resistivity and additional characteristics, as provided in Table 2.
The mechanical strength of a single crystal silicon wafer sliced from the ingot prepared according to Example 1 is compared with non-germanium-doped silicon wafer (ID #0) also having low Oi using an EPI reactor slip generation test by a temperature ramp. According to this test, the lower the number of slip generated, the greater the mechanical strength. Thereby, a lower yield loss is expected. Further, the larger the no-slip temperature window by this test, the larger the process window during the SOI wafer and device manufacturing. As depicted by the graphs of
The mechanical strength of a single crystal silicon wafer sliced from the ingot prepared according to Example 1 is compared with non-germanium-doped silicon wafer (ID #0) also having low Oi using an EPI reactor slip generation test by a temperature ramp. According to this test, the lower the number of slip generated, the greater the mechanical strength. Thereby, a lower yield loss is expected. Further, the larger the no-slip temperature window by this test, the larger the process window during the SOI wafer and device manufacturing. As depicted by the graph of
A nitrogen doped single crystal silicon ingot was produced in 200 mm FF furnace at SunEdison Semiconductor facility at S. Korea. Seed end N-concentration was targeted for ˜1.4×1014 nitrogen atoms/cm3 in the wafer by adding equivalent amount of silicon nitride during meltdown process (crystal ID #3). Similarly, another crystal was grown by targeting ˜5×1014 nitrogen atoms/cm3 concentration at seed end (crystal ID #4). Resistivity of the crystal was targeted for >3000 Ohm·Cm at seed end by adjusting the dopant concentration in the melt before starting the crystal growth process (based on resistivity of the melt calculated by growing a short crystal with <200 mm diameter and <15 kg wt). The process is optimized to get desired <6.0 ppma Oi.
A germanium doped single crystal silicon ingot (crystal ID #2) was produced in a 200 mm FF furnace at SunEdison facility at S. Korea. 1.3 kg on 5N grade Ge is co-melted with 180 kg of high resistivity Si (>1000 Ohm·Cm) in a high purity quartz lined synthetic crucible. Crystal was targeted for >16,000 Ohm·Cm resistivity by adjusting the dopant concentration in the melt.
The mechanical strength of the wafers are compared with non-germanium-doped silicon wafer (high resistivity, >1000 Ohm·Cm; and low Oi, <6.0 ppma) and different concentration of nitrogen and Ge doped low Oi using an EPI reactor slip generation test by a temperature ramp. The lower the number of slip generated by this test, the greater the mechanical strength, and lower yield loss is expected. Further, larger the no-slip temperature window, larger the process window during SOI wafer and device manufacturing. Based on this test, these is a significant improvement of slip count is observed. The non-germanium-doped silicon wafer has ˜3° C. temperature offset window at 1100° C., 250 s process condition, while the low concentration nitrogen doping (˜1.4×1014 nitrogen atoms/cm3) has 9° C. and high concentration N doping (˜5×1014 nitrogen atoms/cm3) has >20° C. temperature offset. See Table 3. Ge doped wafer has ˜6° C. temperature offset window under similar condition. This improvement is significant enough to improve slip free processing of high resistivity low Oi wafer under much severe process condition.
When introducing elements of the present invention or the embodiment(s) thereof, the articles “a”, “an”, “the” and “said” are intended to mean that there are one or more of the elements. The terms “comprising”, “including” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” “approximately,” and “substantially,” is not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged; such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise.
As various changes could be made in the above without departing from the scope of the invention, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.
This application is a U.S. national stage application of International Application No. PCT/US2017/036061, filed Jun. 6, 2017, the disclosure of which is incorporated by reference as if set forth in its entirety. International Application No. PCT/US2017/036061 disclosure claims the benefit of U.S. provisional application Ser. No. 62/347,143, filed on 8 Jun. 2016 and the benefit of U.S. provisional application Ser. No. 62/347,145, filed on 8 Jun. 2016. The disclosures of both priority documents are hereby incorporated by reference as if set forth in their entirety.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2017/036061 | 6/6/2017 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2017/214084 | 12/14/2017 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 4501060 | Frye et al. | Feb 1985 | A |
| 4755865 | Wilson et al. | Jul 1988 | A |
| 4968384 | Asano | Nov 1990 | A |
| 5189500 | Kusunoki | Feb 1993 | A |
| 6043138 | Ibok | Mar 2000 | A |
| 6204205 | Yu et al. | Mar 2001 | B1 |
| 6373113 | Gardner et al. | Apr 2002 | B1 |
| 6479166 | Heuer et al. | Nov 2002 | B1 |
| 6562127 | Kud et al. | May 2003 | B1 |
| 6624047 | Sakaguchi et al. | Sep 2003 | B1 |
| 7629054 | Umeno | Dec 2009 | B2 |
| 7868419 | Kerr et al. | Jan 2011 | B1 |
| 7879699 | Schulze et al. | Feb 2011 | B2 |
| 7915716 | Pisigan et al. | Mar 2011 | B2 |
| 8058137 | Or-Bach et al. | Nov 2011 | B1 |
| 8076750 | Kerr et al. | Dec 2011 | B1 |
| 8466036 | Brindle et al. | Jun 2013 | B2 |
| 8481405 | Arriagada et al. | Jul 2013 | B2 |
| 8796116 | Grabbe et al. | Aug 2014 | B2 |
| 8846493 | Libbert et al. | Sep 2014 | B2 |
| 8859393 | Ries et al. | Oct 2014 | B2 |
| 9202711 | Liu et al. | Dec 2015 | B2 |
| 9458554 | Mueller et al. | Oct 2016 | B2 |
| 20020090758 | Henley et al. | Jul 2002 | A1 |
| 20040003769 | Tamatasuka et al. | Jan 2004 | A1 |
| 20040005740 | Lochtefeld et al. | Jan 2004 | A1 |
| 20040031979 | Lochtefeld et al. | Feb 2004 | A1 |
| 20040108537 | Tiwari | Jun 2004 | A1 |
| 20040213907 | Todd et al. | Oct 2004 | A1 |
| 20050026432 | Atwater, Jr. et al. | Feb 2005 | A1 |
| 20050153524 | Maa et al. | Jul 2005 | A1 |
| 20050167002 | Ghyselen et al. | Aug 2005 | A1 |
| 20050253224 | Ho | Nov 2005 | A1 |
| 20060030124 | Maa et al. | Feb 2006 | A1 |
| 20060033110 | Alam et al. | Feb 2006 | A1 |
| 20060046431 | Blietz et al. | Mar 2006 | A1 |
| 20060226482 | Suvorov | Oct 2006 | A1 |
| 20070032040 | Lederer | Feb 2007 | A1 |
| 20070054466 | Hebras | Mar 2007 | A1 |
| 20070066033 | Kurita | Mar 2007 | A1 |
| 20070200144 | Aspar et al. | Aug 2007 | A1 |
| 20080171443 | Hebras | Jul 2008 | A1 |
| 20080299744 | Yamazaki et al. | Dec 2008 | A1 |
| 20090004833 | Suzuki et al. | Jan 2009 | A1 |
| 20090014828 | Mizushima et al. | Jan 2009 | A1 |
| 20090092810 | Lee et al. | Apr 2009 | A1 |
| 20090117716 | Shimomura et al. | May 2009 | A1 |
| 20090278233 | Pinnington et al. | Nov 2009 | A1 |
| 20090321829 | Nguyen et al. | Dec 2009 | A1 |
| 20100224968 | Kurita | Sep 2010 | A1 |
| 20110174362 | Tanner et al. | Jul 2011 | A1 |
| 20110298083 | Yoneda | Dec 2011 | A1 |
| 20120091587 | Or-Bach et al. | Apr 2012 | A1 |
| 20120161310 | Brindle et al. | Jun 2012 | A1 |
| 20120238070 | Libbert et al. | Sep 2012 | A1 |
| 20120267681 | Nemoto et al. | Oct 2012 | A1 |
| 20130120951 | Zuo et al. | May 2013 | A1 |
| 20130122672 | Or-Bach et al. | May 2013 | A1 |
| 20130168835 | Botula et al. | Jul 2013 | A1 |
| 20130193445 | Dennard et al. | Aug 2013 | A1 |
| 20130294038 | Landru et al. | Nov 2013 | A1 |
| 20130323153 | Hoshi et al. | Dec 2013 | A1 |
| 20130344680 | Arriagada et al. | Dec 2013 | A1 |
| 20140042598 | Kitada et al. | Feb 2014 | A1 |
| 20140070215 | Bedell et al. | Mar 2014 | A1 |
| 20140084290 | Allibert et al. | Mar 2014 | A1 |
| 20140120654 | Fujii et al. | May 2014 | A1 |
| 20140124902 | Botula et al. | May 2014 | A1 |
| 20140273405 | Liu et al. | Sep 2014 | A1 |
| 20150004778 | Botula et al. | Jan 2015 | A1 |
| 20150112308 | Ishida | Apr 2015 | A1 |
| 20150115480 | Peidous et al. | Apr 2015 | A1 |
| 20160108551 | Basak et al. | Apr 2016 | A1 |
| 20170033002 | Meguro et al. | Feb 2017 | A1 |
| 20170345663 | Ishizuka et al. | Nov 2017 | A1 |
| Number | Date | Country |
|---|---|---|
| 101165224 | Apr 2008 | CN |
| 102312292 | Jan 2012 | CN |
| 103429798 | Dec 2013 | CN |
| 103578976 | Feb 2014 | CN |
| 0939430 | Jan 1999 | EP |
| 1087041 | Mar 2001 | EP |
| 1865551 | Dec 2007 | EP |
| 2426701 | Jul 2012 | EP |
| 2503592 | Sep 2012 | EP |
| 2579303 | Oct 2013 | EP |
| H01315144 | Dec 1989 | JP |
| 2005306653 | Nov 2005 | JP |
| 2007191350 | Aug 2007 | JP |
| 2012253364 | Dec 2012 | JP |
| 2014019600 | Feb 2014 | JP |
| 2016088822 | May 2016 | JP |
| 10-2009-0082001 | Jul 2009 | KR |
| 1020090079419 | Jul 2009 | KR |
| 2005010243 | Feb 2005 | WO |
| 2009120407 | Oct 2009 | WO |
| 2012127006 | Sep 2012 | WO |
| 2015112308 | Jul 2015 | WO |
| 2015119742 | Aug 2015 | WO |
| Entry |
|---|
| Fukuda, Tetsuo et al., Mechanical strength of silicon crystals with oxygen and/or germanium impurities, Applied Physics Letter, 1992, pp. 1184-1186, vol. 60. |
| Chiou, H-D et al., Effects of Oxyygen and Nitrogen on Slip in CZ Silicon Wafers, 1046B Extended Abstracts, 1984, Abstract No. 36, pp. 51-52, Pennington, New York. |
| Gamble, H.S. et al., Low-loss CPW Lines on Surface Stabilized High-Resistivity Silicon, IEEE Microwave and Guided Wave Letters, Oct. 1999, pp. 395-397, vol. 9, No. 10. |
| Lederer, D. et al., Enhanced High resistivity SOI wafers for RF Applications, 2004, IEEE International SOI Conference, Oct. 2004, pp. 46-47. |
| Lederer D. et al., New Substrate Passivation Method Dedicated to HR SOI Wafer Fabrication With Increased Substrate Resistivity, IEEE Electron Device Letters, Nov. 2005, pp. 805-807, vol. 26, No. 11. |
| Lederer, D. et al., Performance of SOI devices transferred onto passivated HR SOI substrates using a layer transfer technique, 2006, IEEE International SOI Conference Proceedings, 2006, pp. 29-30. |
| Kerr, Daniel C., Identification of RF harmonic distortion of Si substrates and its reduction using a trap-rich layer, IEEE (IEEE Topical Meeting), 2008, pp. 151-154. |
| Blicher, Adolph, Field-Effect and Bipolar Power Transistor Physics, Book, 1981, pp. 61-64, Academic Press, Inc. |
| Morkc, Hadis, Nanoheteroepitaxy and nano-ELO; Handbook of Nitride Semiconductors and Devices, Materials Properties, Physics, and Growth, 2009, Wiley, pp. 564-569, vol. 1, Chapter 3.5.5.3. |
| Zamir, S. et al., Reduction of cracks in GaN films on Si-on-insulator by lateral confined epitaxy, Journal of Crystal Growth, Elsevier Amsterdam, NL, Sep. 2002, pp. 375-380, vol. 243, No. 3-4. |
| Gao, Min, et al., A transmission electron microscopy study of microstructural defects in proton implanted silicon, Journal of Applied Physics, Oct. 15, 1996 American Institute of Physcis, pp. 4767-4769, vol. 70, No. 8. |
| Gao, Min, et al., Two-dimensional network of dislocations and nanocavities in hydrogen-implanted and two-step annealed silicon, Applied Physcis Letters, American Institute of Physics May 18, 1998, pp. 2544-2546, vol. 72, No. 20. |
| Lu, Hongqiang et al., Characterization of methyl-doped silicon oxide film deposited using Flowfil(TM) chemical vapor deposition technology, Journal of Vacuum Science and Technology, Part B, May 2002, pp. 828-833, vol. 20, No. 3, Melville, New York. |
| Tong, Q. Y. et al., Semiconductor wafer bonding: recent developments, Materials Chemistry and Physics, Mar. 1994, pp. 101/127, vol. 37, No. 2, Elsevier Sequoia. |
| Porrini, M. et al., Growth of Large Diameter High purity Silicon Single Crystals With The MCZ Method for Power Devices Applications, MADEP, Symposium on Materials and Devices for Powerelectronics, EPE Europen Conference on Power Electronics and Applications, Sep. 2, 1991, pp. 90-93. |
| International Search Report and Written Opinion prepared by the International Searching Authority regarding PCT/US2017/036061 dated Sep. 14, 2017; pp. 1-11. |
| Number | Date | Country | |
|---|---|---|---|
| 20200216975 A1 | Jul 2020 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62347143 | Jun 2016 | US | |
| 62347145 | Jun 2016 | US |
