Patent Application
20060220170
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a metal oxide semiconductor field effect transistor (MOSFET).
2. Description of the Related Art
To integrate control circuits and high-voltage transistors has become a development trend for present power integrated circuit (Power IC). Therefore, if high-voltage transistor devices can be fabricated using standard process, it would be a preferable way for integrating a monolithic IC. However, the high-voltage transistor fabricated in current standard process does not have an isolation structure, and the transistor current without isolation structure may flow in the substrate and cause disturbance to the control circuit. Also, the transistor current may produce ground bounce to affect the control signal of the control circuit. Accordingly, the transistor without the isolation structure is not suitable for the integrated technology. In a conventional technology, a thin epitaxial layer and an N-type buried layer are used to provide the transistor an isolation structure and high breakdown voltage, but the complicated manufacturing process increases the fabricating cost and reduces the yield.
Accordingly, to overcome the above disadvantages, the present invention provides a field effect transistor device having higher breakdown voltage, lower conductive resistance and an isolation structure for integrating a monolithic IC.
The present invention provides a high-voltage MOSFET having an isolation structure, and the field effect transistor device includes an N-type MOSFET and a P-type MOSFET disposed in a P-type substrate.
The N-type MOSFET comprises a first N-type diffusion region having N-type conductive ions to form a first deep N-type well in a P-type substrate; a first P-type diffusion region having P-type conductive ions to form a P-type region in the first deep N-type well; a first drain diffusion region having N+-type conductive ions to form a first drain region in the first N-type diffusion region; a first source diffusion region having N+-type conductive ions to form a first source region; and a first contact diffusion region having P+-type conductive ions to form a first contact region, wherein the first P-type diffusion region encloses the first source region and the first contact region.
The P-type MOSFET comprises a second N-type diffusion region having N-type conductive ions to form a second deep N-type well in the P-type substrate; a second P-type diffusion region having P-type conductive ions to form a second P-type region in the second deep N-type well; a second drain diffusion region having P+-type conductive ions to form a second drain region in the second N-type diffusion region; a second source diffusion region having P+-type conductive ions to form a second source region; and a second contact diffusion region having N+-type conductive ions to form a second contact region, wherein the second N-type diffusion region encloses the second source region and the second contact region.
A plurality of separation P-type diffusion regions having P-type conductive ions form a plurality of separated P-type regions in the P-type substrate to provide further isolation between MOSFETs. The first P-type region located in the first N-type diffusion region, the second P-type region located in the second N-type diffusion region, the plurality of separated P-type regions, the first deep N-type well and the second deep N-type well form the depletion regions.
A first channel is formed between the first source region and the first drain region. A second channel is formed between the second source region and the second drain region. A first polysilicon gate is located on a first thin gate oxidation layer and a first thick field oxidation layer to control a first current flow in the first channel. A second polysilicon gate is located on a second thin gate oxidation layer and a second thick field oxidation layer to control a second current flow in the second channel.
Furthermore, the first deep N-type well and the second deep N-type well respectively formed by the first N-type diffusion region and the second diffusion region provide a low-resistance path which limits the transistor current between the drain region and the source region.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The P-type MOSFET 50 also includes the P-type substrate 100, a second N-type diffusion region 41 to form a second deep N-type well 410 in the P-type substrate 100. A second P-type diffusion region 42 having P-type conductive ions forms a second P-type region 420 in the second deep N-type well 410. A second drain diffusion region 43 having P+-type conductive ions forms a second drain region 430 in the second P-type diffusion region 42. A second source diffusion region 44 having P+-type conductive ions forms a second source region 440. A second-channel is formed between the second source region 440 and the second drain region 430. A second contact diffusion region 45 having N+-type conductive ions forms a second contact region 450, wherein the second N-type diffusion region 41 encloses the second source region 440 and the second contact region 450. The P-type MOSFET 50 further includes the plurality of separated P-type diffusion regions 160, and the separated P-type region 260 formed in the P-type substrate 100 to provide isolation between MOSFETs.
The fabricating process of the first P-type region 220 and the second P-type region 420 may be a P-type well process or a P-type body process. A first thin gate oxidation layer 510 and a second thin gate oxidation layer 520, a first thick field oxidation layer 530, a second thick field oxidation layer 540, a third thick field oxidation layer 531 and a fourth thick field oxidation layer 541 are formed on the P-type substrate 100. The first polysilicon gate 550 is located on the first thin gate oxidation layer 510 and the first field oxidation layer 530 to control the current flow of the first channel of the N-type MOSFET 10. A second polysilicon gate 560 is located on the second thin gate oxidation layer 520 and the second field oxidation layer 540 to control the current flow of the second channel of the P-type MOSFET 50. A silicon oxidation isolation layer 600 covers the polysilicon gates 550 and 560 and thick field oxidation layers 530, 531, 540 and 541. A first drain metal contact 710 and a second drain metal contact 720 having metal electrodes connect with the first drain diffusion region 23 and the second drain diffusion region 43, respectively. A first source metal contact 750 having a metal electrode connects with the first source diffusion region 24 and the first contact diffusion region 25. A second source metal contact 760 having another metal electrode connects with the second source diffusion region 44 and the second contact diffusion region 45.
A first gap 810 is used to maintain a space between the first thick field oxidation layer 530 and the first P-type region 220 to increase the breakdown voltage of the N-type MOSFET 10. A second gap 820 is used to maintain another space between the second thick field oxidation layer 540 and the second deep N-type well 410 to increase the breakdown voltage of the P-type MOSFET 50. The first P-type region 220, the second P-type region 420, the separated P-type region 260, the first deep N-type well 210 and the second deep N-type well 410 form a depletion region to provide isolation between MOSFETs. The first P-type region 220 and the first deep N-type well 210 form a depletion region, and the second P-type region 420 and the second deep N-type well 410 form another depletion region. Along with the P-type region 260, the isolation effect between transistors is more preferable.
Only through a simplified process, the high-voltage transistor device of the present invention, such as the N-type MOSFET 10 and the P-type MOSFET 50, has increased breakdown voltage, lower conductive resistance, and isolation structure. In addition, the conventional high-voltage transistor isolation structure uses the N-type epitaxial layer 660 to enclose the first drain region 230 and the first P-type region 220 of the N-type MOSFET 10, and uses the N-type epitaxial layer 680 to enclose the second source region 440, the second contact region 450 and the second P-type region 420 of the P-type MOSFET 50. The present invention applies the first deep N-type well 210 and the second deep N-type well 410 to do the same. Therefore, the present invention does not require additional masks for fabricating epitaxial layers, such as the N-type epitaxial layers 660 and 680, in the conventional process. The present invention only uses a standard well structure to fabricate the transistor structure with lower cost, high yield and isolation structure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
