Patent Application
20160276428
1. Field of the Invention
Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to transistor devices allowing for a high-voltage operation.
2. Description of the Related Art
Integrated circuits formed on semiconductor wafers typically include a large number of circuit elements, which form an electric circuit. In addition to active devices such as, for example, field effect transistors and/or bipolar transistors, integrated circuits can include passive devices such as resistors, inductors and/or capacitors. In particular, during the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer.
A MOS transistor, for example, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors.
For rectifying and/or switching applications, high-voltage transistors are needed. The development of single chip processes for integrating power switches with control circuitry is a major trend in the field of power IC development. The LDMOS (lateral double diffusion MOS) process in particular is currently being applied to manufacture monolithic ICs. For example, LDMOS FETs are key components of RF power amplifiers used in base stations for personal communication systems (for example, GSM, EDGE, etc.). High breakdown-voltages are most important advantages of LDMOS FETs.
As a device of MOSFET variety, an LDMOS FET uses an inversion channel at the silicon-oxide interface. The inversion channel is induced under the gate by positive gate potential. Under practically relevant conditions, the inversion layer only exists over the laterally diffused P-well, which is sometimes called depletion stopper. As the electrons leave the region over the stopper, they are picked up by the electric field due to positive drain bias and abandon the inversion channel going deeper into the bulk. The effective gate length defines the lateral extension of the stopper layer. It may be, therefore, shorter than the physical length of the gate electrode. The LDMOS process, typically, involves performing planar diffusion on the surface of a semiconductor substrate to form a main current path oriented in the lateral direction. Since the lateral MOSFET is manufactured using a typical IC process, the control circuit and the lateral power MOSFET can be integrated onto a monolithic power IC. An LDMOS process using a reduced surface electric field (RESURF) technique with a low thickness EPI or N-well can achieve a high voltage with low on-resistance. A variety of LDMOS designs have been proposed for integrating control circuitry with power switches.
However, LDMOS FETs as the one described with reference to
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
Generally the subject matter disclosed herein relates to semiconductor devices and methods for fabricating the same, wherein enhanced transistor performance may be obtained for N-channel transistors and P-channel transistors on the basis of silicon-on-insulator (SOI) techniques.
One illustrative semiconductor device disclosed herein includes a substrate, a buried oxide layer formed over the substrate, a semiconductor layer formed over the buried oxide layer and a transistor device. The transistor device includes a gate electrode, a gate insulation layer and a channel region. The gate insulation layer (gate dielectric) comprises a part of the buried oxide layer. The transistor device may be an N-channel or a P-channel TFT.
One illustrative method of forming a semiconductor device disclosed herein includes providing a silicon-on-insulator (SOI) wafer comprising a substrate, a buried oxide layer and a semiconductor layer and forming a transistor device in and on the wafer. The formation of the transistor device includes forming a gate electrode in the substrate by doping the substrate and forming a gate insulation layer from the buried oxide layer.
According to another example, a method of forming a semiconductor device is provided included providing a silicon-on-insulator (SOI) wafer comprising a substrate, a buried oxide layer and a semiconductor layer, and forming a transistor device in and on the wafer. The formation of the transistor device includes forming a gate electrode in the semiconductor layer and forming a gate insulation layer from the buried oxide layer.
The thus manufactured or provided transistor may be used as a switching device in high-frequency applications. Thus, a method of driving a transistor device as a switch is also provided, wherein the transistor device is formed in and on an SOI wafer and comprises a gate electrode and a part of a buried oxide layer of the SOI wafer as a gate dielectric, comprising applying an electrical voltage of more than 5 V, for example, more than 8 V, to the gate electrode.
The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:
While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.
Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.
The present disclosure will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details which are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary or customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition shall be expressively set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.
The following embodiments are described in sufficient detail to enable those skilled in the art to make use of the invention. It is to be understood that other embodiments would be evident, based on the present disclosure, and that system, structure, process or mechanical changes may be made without departing from the scope of the present disclosure. In the following description, numeral-specific details are given to provide a thorough understanding of the disclosure. However, it would be apparent that the embodiments of the disclosure may be practiced without the specific details. In order to avoid obscuring the present disclosure, some well-known circuits, system configurations, structure configurations and process steps are not disclosed in detail.
Generally, it is described how to manufacture a semiconductor device with a transistor device allowing for applying relatively high voltages, for example, voltages of some 5 to 10 V, to the gate electrode of the transistor device. With reference to
As shown in
The BOX layer 20 may comprise silicon (di)oxide or a borosilicate glass or a borophosphosilicate glass (BPSG). The BOX layer may be composed of different layers and one of the different layers may comprise BPSG or an SiO2 compound comprising boron or phosphorus. The substrate 10 may be a semiconductor substrate, for example, a silicon substrate, in particular, a single crystal silicon substrate. Other materials may be used to form the semiconductor substrate 10 such as, for example, germanium, silicon germanium, gallium phosphate, gallium arsenide, etc. The thickness of the semiconductor layer 30 may lie in the range of 5-30 nm, in particular, 5-15 nm, and the thickness of the BOX layer 20 may lie in the range of 10-50 nm, in particular, 10-30 nm and, more particularly, 15-25 nm.
From the wafer shown in
The device shown in
The transistor device formed in accordance with
Another example of the manufacture of a semiconductor device comprising a transistor device according to the present invention is illustrated in
Again, the BOX layer 200 may comprise silicon (di)oxide. The substrate 100 may be a semiconductor substrate, for example, a silicon substrate, in particular, a single crystal silicon substrate. Other materials may be used to form the semiconductor substrate 100 such as, for example, germanium, silicon germanium, gallium phosphate, gallium arsenide, etc. The thickness of the semiconductor layer 300 may lie in the range of 5-30 nm, in particular, 5-15 nm, and the thickness of the BOX layer 20 may lie in the range of 10-50 nm, in particular, 10-30 nm and, more particularly, 15-25 nm.
From the wafer shown in
In the substrate 100, some appropriate well implant may be performed. Moreover, as shown in
Different from the example shown in
The gate electrode 400 may be formed by appropriately doping the semiconductor layer 300 or it may be formed as a fully silicided gate electrode, for instance, a fully silicided polysilicon gate electrode. The gate electrode 400 may comprise a metal-containing layer formed on the dielectric layer. The metal-containing layer may comprise at least one of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), tungsten (W), for example. The metal-containing layer may be relatively thin with a thickness below 50 nm, in particular, below 20 nm. The gate electrode material may comprise a semiconductor layer, for example, comprising silicon, above the metal-containing layer. The semiconductor layer of the gate electrode material may comprise un-doped polycrystalline silicon.
The source 500, drain 500′ and gate 400 are electrically contacted by contacts 710, 720 and 730, respectively. It is noted that N+ contact regions for contacting the source/drain and gate electrodes may be formed. The formation of these N+ contact regions may comprise implantation and/or epitaxial growth. The configuration shown in
If considered appropriate, sidewall spacers 800 may be employed for the doping processes used to form the drain and source regions 500 and 500′. Formation of the sidewall spacers 800 after performing the etching process based on an etching mask, for example, an NO mask, used for etching the wafer of
It should be noted that both the semiconductor device of the example illustrated in
According to the disclosure, the BOX layer of an SOI wafer is used as a gate dielectric of a transistor device. Therefore, it is necessary that the quality of the SOI wafer, in particular, the quality of the BOX layer, is rather high. A high-quality SOI wafer may be provided by means of the SMARTCUT® technique.
After bonding of the semiconductor wafer 900 and the handle wafer 930, an anneal treatment is performed to generate bubbles 940 in the weakened layer 920. The bubble formation facilitates breakage at the weakened layer 920. The separated part 950 of the semiconductor wafer can be re-used for the formation of another SOI wafer. The surface of the resulting semiconductor layer 960 may be treated by chemical mechanical polishing to provide the semiconductor layer 960 of an SOI wafer 1000. Eventually, the SOI wafer 1000 results by cutting the handle wafer 930 as illustrated at the bottom of
The process flow illustrated in
As a result, the present application provides a semiconductor device and manufacturing techniques for such a semiconductor device wherein the semiconductor device comprises a transistor with a gate insulation layer made of the BOX layer of an SOI wafer. Thereby, supply of relatively high voltages to the gate electrode of the transistor during operation is made possible without running the risk of damaging the transistor.
The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is, therefore, evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.
