Claims
- 1. A method for plating a homogenous copper tin alloy onto a semiconductor substrate, comprising:
providing a plating solution to a plating cell, wherein the plating solution contains an acid, a copper ion source, and a tin ion source, the copper ion source including between about 70% and about 98.5% of the metal ions and the tin ions including between about 1.5% and about 30% of the metal ions; providing a plating bias to a conductive layer formed on the semiconductor substrate while the conductive layer is in fluid contact with the plating solution, the plating bias being configured to overlap a plating potential range of both copper and tin; and simultaneously plating copper and tin ions onto the conductive layer from the plating solution to form a homogenous copper tin alloy layer on the conductive layer.
- 2. The method of claim 1, wherein the tin ion source comprises at least one of SnSO4 and SnCl2.
- 3. The method of claim 1, wherein the concentration of the copper ion source is between about 0.2M and about 0.9M.
- 4. The method of claim 1, wherein the concentration of the tin ion source is between about 0.1M and about 0.8M.
- 5. The method of claim 1, wherein the plating bias includes a current density of between about 5 mA/cm2 and about 60 mA/cm2.
- 6. The method of claim 1, further comprising rotating the substrate during the plating process.
- 7. The method of claim 1, wherein the plating bias is configured to plate a homogenous copper tin alloy during a first stage and a substantially tin free copper metal layer during a second stage, the second stage occurring after the first stage.
- 8. The method of claim 1, further comprising annealing the homogenous copper tin alloy at a temperature of between about 200° C. and about 400° C. for between about 5 minutes and about 1 hour.
- 8. The method of claim 1, further comprising calculating a change in reduction potential for copper and tin resulting from concentration variances from the following equation:
- 9. The method of claim 8, wherein the plating bias is calculated from the calculated concentration variances.
- 10. A method for plating a homogenous copper-tin alloy onto a semiconductor substrate, comprising:
providing a plating solution to an electrochemical plating cell, the plating solution comprising:
an acid comprising at least one of sulfuric acid and phosphoric acid.; a copper ion source at a concentration of between about 0.4M and about 0.9M; a tin ion source, the tin ion source including at least one of SnSO4 and SnCl2, the tin ion source being at a concentration of between about 0.1M and 0.4M; and at least one organic plating additive; exposing a deposition surface of the substrate having a seed layer formed thereon to the plating solution; supplying an electrical deposition bias to the seed layer, wherein the deposition bias generates a current density of between about 5 mA/cm2 and about 60 mA/cm2 across the surface of the seed layer; and simultaneously plating tin ions and copper ions on the substrate surface to form a homogenous copper-tin alloy.
- 11. The method of claim 10, further comprising annealing the copper-tin alloy at a temperature of between about 200° C. and about 400° C. for a duration of between about 5 minutes and about 60 minutes.
- 12. The method of claim 10, further comprising rotating the substrate during the plating process at a rotation rate of between about 5 RPM and about 40 RPM.
- 13. The method of claim 10, wherein the homogenous copper tin alloy includes less than about 1.5% of tin.
- 14. The method of claim 10, wherein the homogenous copper tin alloy includes up to about 98.5% copper.
- 15. The method of claim 10, wherein the deposition bias is configured to overlap a calculated plating potential range for the particular copper concentration and the particular tin concentration of the plating solution.
- 16. The method of claim 15, further comprising calculating a change in reduction potential for copper and tin resulting from concentration variances from the following equation:
- 17. The method of claim 10, further comprising maintaining the electrical deposition bias at a magnitude small enough to prevent an oxidation reaction of Sn2+ to Sn4+.
- 18. A method for plating a substantially homogenous copper tin alloy layer on a conductive seed layer formed onto a semiconductor substrate, comprising:
providing a plating solution having both copper ions and tin ions therein; exposing the conductive seed layer to the plating solution; and applying a plating bias to the conductive seed layer to plate the substantially homogenous copper tin alloy layer onto the conductive seed layer, wherein the plating solution includes between about 0.2M and about 0.5M of copper ion concentration and between about 0.4M and about 0.8M of tin ion concentration, and wherein the plating bias includes a current density of between about 5 mA/cm2 and about 60 mA/cm2.
- 19. The method of claim 18, wherein the plating bias is calculated to overlap a plating potential range of copper and tin.
- 20. The method of claim 18, further comprising annealing the substantially homogenous copper tin alloy layer after the plating step.
- 21. The method of claim 18, further comprising calculating a change in reduction potential for copper and tin resulting from concentration variances from the following equation:
- 22. The method of claim 21, wherein the calculated reduction potentials are used to determine an alloy plating bias that will overlap copper ions and tin ions in the plating solution.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims benefit of U.S. provisional patent application serial No. 60/370,512 filed Apr. 3, 2002, which is herein incorporated by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60370512 |
Apr 2002 |
US |