Patent Application
20240047493
This application claims priority to Korean Patent Application No. 10-2022-0095895, filed on Aug. 2, 2022 in the Korean Intellectual Property Office (KIPO), the contents of which is incorporated by reference herein in its entirety.
Example embodiments relate to an image sensor and a method of manufacturing the same.
As the electronic industry develops, the size of the image sensor has decreased, and thus various studies have been performed in order to satisfy the need for the high integration degree of the image sensor.
The high integration degree of the image sensor may increase the electric interference between circuit patterns, and thus a solution for decreasing the electric interference is needed.
One or more example embodiments provide an image sensor having improved characteristics and a method of manufacturing an image sensor having improved characteristics.
According to an aspect of an example embodiment, an image sensor includes: a first substrate comprising an analog block and a digital block; an isolation structure extending through the first substrate and dividing the analog block from the digital block; a first transistor on the digital block; a second transistor on the analog block; a wiring on and electrically connected to the second transistor; a second substrate on the wiring; a color filter array layer on the second substrate, the color filter array layer comprising color filters; a microlens on the color filter array layer; a light sensing element in the second substrate; a transfer gate extending through a lower portion of the second substrate, the transfer gate being adjacent to the light sensing element; and a floating diffusion region at a lower portion of the second substrate adjacent to the transfer gate, the floating diffusion region being electrically connected to the wiring.
According to an aspect of an example embodiment, an image sensor includes: a first substrate; an isolation structure comprising: a first isolation pattern extending through an upper portion of the first substrate; and a second isolation pattern structure extending through a lower portion of the first substrate and contacting the first isolation pattern, the second isolation pattern structure comprising a material different from a material of the first isolation pattern; a first transistor on the first substrate; a wiring on and electrically connected to the first transistor; a second substrate on the wiring; a color filter array layer on the second substrate, the color filter array layer comprising color filters; a microlens on the color filter array layer; a light sensing element in the second substrate; a transfer gate extending through a lower portion of the second substrate, the transfer gate being adjacent to the light sensing element; and a floating diffusion region at a lower portion of the second substrate adjacent to the transfer gate, the floating diffusion region being electrically connected to the wiring.
According to an aspect of an example embodiment, a method of manufacturing an image sensor includes: forming a first isolation pattern at least partially through a first substrate comprising first and second surfaces opposite to each other, the first isolation pattern extending through a portion of the first substrate adjacent to the second surface of the first substrate; forming circuit patterns on the second surface of the first substrate; forming a first insulating interlayer on the second surface of the first substrate on the circuit patterns; forming a light sensing element in a second substrate comprising first and second surfaces opposite to each other; forming a transfer gate through a portion of the second substrate adjacent to the second surface of the second substrate; forming a floating diffusion region at a portion of the second substrate adjacent to the transfer gate; forming a second insulating interlayer on the second surface of the second substrate, the transfer gate and the floating diffusion region; bonding the first substrate and the second substrate so that the second insulating interlayer on the second substrate and the first insulating interlayer on the first substrate face each other; and forming a second isolation pattern structure through a portion of the first substrate adjacent to the first surface of the first substrate to contact the first isolation pattern.
According to an aspect of an example embodiment, a method of manufacturing an image sensor includes: forming a first isolation pattern partially through a first substrate to divide the first substrate into an analog block and a digital block, the first substrate comprising first and second surfaces opposite to each other, and the first isolation pattern extending through a portion of the first substrate adjacent to the second surface of the first substrate; forming an analog circuit pattern in the analog block and a digital circuit pattern in the digital block; forming a first insulating interlayer on the second surface of the first substrate, the analog circuit pattern and the digital circuit pattern; forming a light sensing element in a second substrate comprising first and second surfaces opposite to each other; forming a transfer gate through a portion of the second substrate adjacent to the second surface of the second substrate; forming a floating diffusion region at a portion of the second substrate adjacent to the transfer gate; forming a second insulating interlayer on the second surface of the second substrate, the transfer gate and the floating diffusion region; bonding the first substrate and the second substrate so that the second insulating interlayer on the second substrate and the first insulating interlayer on the first substrate face each other; and forming a second isolation pattern structure through a portion of the first substrate adjacent to the first surface of the first substrate to contact the first isolation pattern, wherein the first isolation pattern and the second isolation pattern structure form an isolation structure extending through the first substrate and dividing the analog block from the digital block.
According to an aspect of an example embodiment, a method of manufacturing an image sensor includes: forming a logic circuit pattern on a first substrate; forming a first insulating interlayer on the first substrate and the logic circuit pattern; forming a first isolation pattern at least partially through a second substrate comprising first and second surfaces to divide the second substrate into an analog block and a digital block, the first isolation pattern extending through a portion of the second substrate adjacent to the second surface of the second substrate; forming an analog circuit pattern in the analog block and a digital circuit pattern in the digital block; forming a second insulating interlayer on the second surface of the second substrate, the analog circuit pattern and the digital circuit pattern; forming a light sensing element in a third substrate comprising first and second surfaces opposite to each other; forming a transfer gate through a portion of the third substrate adjacent to the second surface of the third substrate; forming a floating diffusion region at a portion of the third substrate adjacent to the transfer gate; forming a third insulating interlayer on the second surface of the third substrate, the transfer gate and the floating diffusion region; bonding the second and third substrates so that the third insulating interlayer on the third substrate and the second insulating interlayer on the second substrate face each other; forming a second isolation pattern structure through a portion of the second substrate adjacent to the first surface of the second substrate to contact the first isolation pattern; forming a fourth insulating interlayer on the first surface of the second substrate and the second isolation pattern structure; and bonding the first substrate and the second substrate so that the fourth insulating interlayer on the second substrate and the first insulating interlayer on the first substrate face each other.
The above and other aspects and features will be more apparent from the following description of example embodiments, taken in conjunction with the accompanying drawings, in which:
Example embodiments will be described more fully with reference to the accompanying drawings, in which example embodiments are shown. Embodiments described herein are provided as examples, and thus, the present disclosure is not limited thereto, and may be realized in various other forms. Each embodiment provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. By contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression, “at least one of a, b, and c,” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It will be understood that, although the terms “first,” “second,” and/or “third” may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second or third element, component, region, layer or section without departing from the teachings of example embodiments.
First, second and third regions I, II and III may refer to only an inside of a reference substrate, a first substrate, a second substrate and/or a third substrate. Alternatively, the first, second and third regions I, II and III may also refer to spaces over and under the reference substrate, the first substrate, the second substrate and/or the third substrate.
A direction substantially parallel to the reference substrate, the first substrate, the second substrate and/or the third substrate may be referred to as a horizontal direction, and a direction substantially perpendicular to the surface of the reference substrate, the first substrate, the second substrate and/or the third substrate may be referred to as a vertical direction. First and second directions D1 and D2 that cross each other may be referred to as the horizontal directions, and a third direction D3 is used as the vertical direction. First direction D1 and second direction D2 may be substantially perpendicular to one another and substantially perpendicular to the third direction D3.
In the specifications, up vs. down, on and over vs. beneath and under, upper surface vs. lower surface, and upper portion vs. lower portion are relative conceptions so as to describe opposite sides in the vertical direction, and each wording may have opposite meanings according to the specific parts to be explained with reference to example embodiments.
Referring to
In example embodiments, the first region I may be a pixel region in which pixels are formed, and the second region II may be a connection region in which connection wirings for transferring electrical signals in the vertical direction, that is, the third direction D3 are formed. In example embodiments, the second region II may be around and surround the first region I.
Hereinafter, drawings show only region X in the first and second regions I and II.
Referring to
Each of the first, second and third substrates 100, 200 and 400 may include silicon, germanium, silicon-germanium, or a III-V group compound semiconductor, such as GaP, GaAs, or GaSb. In some example embodiments, at least one of the first, second and third substrates 100, 200 and 400 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.
In example embodiments, the third substrate 400 may be a substrate on which elements for receiving light and converting the light into electronic signals are formed, the second substrate 200 may be a substrate on which elements for converting the electronic signals into voltage signals are formed, and the first substrate 100 may be a substrate on which logic circuit patterns for processing electrical signals, e.g., the electronic signals, the voltage signals, etc., are formed.
Thus, logic circuit patterns may be formed in the first, second and third regions I, II and III on the first substrate 100, and for example, a first transistor in the first region I of the first substrate 100 and two second transistors in the second region II of the first substrate 100 included as the logic circuit patterns are shown in
The first transistor may include a first gate electrode 112 on the first region I of the first substrate 100 and first impurity regions 102 at portions of the first substrate 100 adjacent to the first gate electrode 112, and the second transistor may include a second gate electrode 118 on the second region II of the first substrate 100 and second impurity regions 108 at portions of the first substrate 100 adjacent to the second gate electrode 118.
Contact plugs, wirings and vias electrically connected to the first and second transistors may be further formed on the first substrate 100.
For example, in addition to the first to sixth wirings 132, 152, 124, 154, 138 and 158 at first and second levels, upper wirings may be further formed at one or a plurality of levels higher than the second level.
A first insulating interlayer 160 may be formed on the first substrate 100, and may be provided on the first and second transistors, the first, second and third contact plugs 122, 124 and 128, the first to sixth wirings 132, 152, 134, 154, 138 and 158, and the first to fourth vias 142, 144, 148 and 178. In an example embodiment, first insulating interlayer 160 may be formed on the first substrate 100, and may cover the first and second transistors, the first, second and third contact plugs 122, 124 and 128, the first to sixth wirings 132, 152, 134, 154, 138 and 158, and the first to fourth vias 142, 144, 148 and 178.
In example embodiments, first and fourth adhesion layers 180 and 690 and a fourth insulating interlayer 670 may be stacked in the third direction D3. A first adhesion pad 198 extending through the first adhesion layer 180 to contact the fourth via 178, a sixth adhesion pad 708 extending through the fourth adhesion layer 690 to contact the first adhesion pad 198, and a fifteenth via 688 extending through the fourth insulating interlayer 670 to contact the sixth adhesion pad 708 may be formed.
The second substrate 200 may have first and second surfaces 201 and 203 that may be opposite to each other in the third direction D3.
Analog circuit patterns for forming elements that may convert electronic signals into voltage signals and digital circuit patterns for forming memory elements may be formed on the second surface 203 of the second substrate 200, which may be formed on the fourth and third regions IV and III, respectively, of the second substrate 200. That is, the third and fourth regions III and IV of the second substrate 200 may be a digital block region and an analog block region, respectively.
In example embodiments, the analog block and the digital block on the second substrate 200 may be divided by a first isolation structure 900 extending through the second substrate 200.
Referring to
Referring to
Additionally, the first isolation structure 900 may include second portions, each of which may extend in the first direction to be connected to the first portion, spaced apart from each other in the second direction D2, and thus the third region III of the second substrate 200 may be divided into a plurality of parts in the second direction D2. The first isolation structure 900 may have a ladder shape in the third region III and a boundary between the third and fourth regions III and IV, in a plan view.
The layout of the first isolation structure 900 is not be limited to those of
In example embodiments, the first isolation structure 900 may include a first isolation pattern 205 extending through a portion of the second substrate 200 adjacent to the second surface 203 and a second isolation pattern structure 642 extending through a portion of the second substrate 200 adjacent to the first surface 201 to contact the first isolation pattern 205.
The first isolation pattern 205 may include an oxide, e.g., silicon oxide.
In example embodiments, the second isolation pattern structure 642 may include a first conductive pattern 632 and a first insulation pattern 622 provided on a sidewall and an upper surface of the first conductive pattern 632. In an example embodiment, the second isolation pattern structure 642 may include a first conductive pattern 632 and a first insulation pattern 622 covering a sidewall and an upper surface of the first conductive pattern 632. The first conductive pattern 632 may include a metal, e.g., tungsten, copper, aluminum, etc., and the first insulation pattern 622 may include a metal oxide, e.g., aluminum oxide, hafnium oxide, etc., or silicon oxide, e.g., tetraethyl orthosilicate (TEOS).
In example embodiments, a first insulation layer 620 and a first conductive layer 630 may be stacked in the third direction D3 beneath the first surface 201 of the second substrate 200, which may include materials substantially the same as those of the first insulation pattern 622 and the first conductive pattern 632, respectively, so as to be merged thereto, respectively.
Third and fourth transistors may be formed on the second substrate 203 of the second substrate 200. In example embodiments, the third and fourth transistors may be formed on the third and fourth regions III and IV divided by the first isolation pattern 205 in the first region I of the second substrate 200. However, embodiments are not limited thereto, and one or a plurality of transistors may be formed in the third and fourth regions III and IV of the second substrate 200.
Particularly, the third transistor may include a third gate electrode 212 on the third region III of the second substrate 200 and third impurity regions 202 at upper portions of the second substrate 200 adjacent to the third gate electrode 212. Additionally, the fourth transistor may include a fourth gate electrode 216 on the fourth region IV of the second substrate 200 and fourth impurity regions 206 at upper portions of the second substrate 200 adjacent to the fourth gate electrode 216.
In example embodiments, the fourth transistor may be a source follower (SF) transistor. Additionally, a select transistor and a reset transistor may be further formed on the fourth region IV of the second substrate 200.
In example embodiments, the third transistor may be a transistor that may form a circuit in, e.g., an SRAM device or a DRAM device.
Contact plugs, wirings and vias electrically connected to the third and fourth transistors may be formed on the second substrate 200.
Additionally, a thirteenth wiring 238, an eighth via 248, a fourteenth wiring 258 and a tenth via 278 may be sequentially stacked on the second region II of the second substrate 200.
However, embodiments are not limited thereto, and in addition to the seventh to fourteenth wirings 232, 252, 234, 254, 236, 256, 238 and 258 at first and second levels, upper wirings may be further formed at one or a plurality levels higher than the second level.
A second insulating interlayer 260 may be formed on the second surface 203 of the second substrate 200, and may be provided on, and in an example embodiment cover, the third and fourth transistors, the fourth to sixth contact plugs 222, 224 and 226, the seventh to fourteenth wirings 232, 252, 234, 254, 236, 256, 238 and 258, and the fifth to tenth vias 242, 244, 246, 248, 276 and 278.
In example embodiments, a first through electrode structure 675 extending through the first conductive layer 630, the first insulation layer 620, the second region II of the second substrate 200 and a lower portion of the second insulating interlayer 260 to contact the thirteenth wiring 238 may be formed.
In example embodiments, the first through electrode structure 675 may include a second conductive pattern 665 and a second insulation pattern 655 provided on, and in an example embodiment covering, a sidewall of the second conductive pattern 665. The second conductive pattern 665 may include a metal, e.g., tungsten, copper, aluminum, etc., and the second insulation pattern 655 may include a metal oxide, e.g., aluminum oxide, hafnium oxide, etc., or silicon oxide, e.g., TEOS.
Second and third adhesion layers 280 and 520 may be stacked on the second insulating interlayer 260 and the ninth and tenth vias 276 and 278. Second and third adhesion pads 296 and 298 extending through the second adhesion layer 280 to contact the ninth and tenth vias 276 and 278, respectively, may be formed on the first and second regions I and II, respectively, of the second substrate 200. Additionally, fourth and fifth adhesion pads 536 and 538 extending through the third adhesion layer 520 to contact the second and third adhesion pads 296 and 298, respectively, may be formed.
A third insulating interlayer 500 may be formed on the third adhesion layer 520, and may contact a lower surface of the third substrate 400. The third substrate 400 may include first and second surfaces 401 and 403 opposite to each other in the third direction D3, and
In example embodiments, a pixel division structure 410 extending through the third substrate 400 in the third direction D3, a light sensing element 430 in each of unit pixel regions defined by the pixel division structure 410, a transfer gate (TG) 440 extending in the third direction D3 through a lower portion of the third substrate 400 to contact the light sensing element 430 and having a lower portion protruding from the second surface 403 of the third substrate 400 downwardly that may be, in an example embodiment, covered by the third insulating interlayer 500, and a floating diffusion (FD) region 450 at a lower portion of the third substrate 400 adjacent to the TG 440 may be formed in the first region I. In an example embodiment, the third insulating layer 500 may be provided on the lower portion protruding from the second surface 403 of the third substrate 400 downwardly.
In example embodiments, a p-type well including p-type impurities may be formed in the third substrate 400.
The pixel division structure 410 may extend in the third direction D3 from the second surface 403 to the first substrate 401 of the third substrate 400 in an inside of the first region I and at a boundary between the first and second regions I and II.
In example embodiments, the pixel division structure 410 may be arranged in a lattice pattern in a plan view, and unit pixel regions in which unit pixels are formed respectively may be defined by the pixel division structure 410. The unit pixel regions may be arranged in the first and second directions D1 and D2 in the first region I of the third substrate 400.
In example embodiments, the pixel division structure may include a core extending in the third direction D3 and a shell provided on, and in an example embodiment covering, a sidewall of the core. The core may include, e.g., polysilicon doped with impurities or undoped polysilicon, and the shell may include an insulating material, e.g., silicon oxide, silicon nitride, etc.
A fifth impurity region 420 including p-type impurities, e.g., boron may be formed at a portion of the third substrate 400 adjacent to the pixel division structure 410 in the first region I. An impurity concentration of the fifth impurity region 420 may be higher than that of the p-type well.
In example embodiments, the light sensing element 430 may be, for example, a photodiode (PD) or a portion of a photodiode (PD). The light sensing element 430 may be an impurity region doped with n-type impurities, e.g., phosphorus in the p-type well in the first region I of the third substrate 400, and thus the light sensing element 430 and the p-type well may form a PN junction diode. In example embodiments, the light sensing element 430 may be formed in each of the unit pixel regions defined by the pixel division structure 410.
The TG 440 may include a buried portion extending from the second surface 403 of the third substrate 400 in the third direction D3 upwardly and a protrusion portion under the buried portion and having a bottom surface lower than the second surface 403 of the third substrate 400. In example embodiments, the TG 440 may be formed in each of the unit pixel region defined by the pixel division structure 410.
The FD region 450 may be an impurity region doped with n-type impurities, e.g., phosphorus at a lower portion of the third substrate 400 adjacent to the TG 440.
Contact plugs, vias and wirings electrically connected to the TG 440 and the FD region 450 may be formed in the third insulating interlayer 500.
One or ones of the wirings, e.g., the eighteenth wiring 498 may extend from the first region I of the third substrate 400 to the second region II of the third substrate 400.
The third insulating interlayer 500 under the second surface 403 of the third substrate 400 may be provided on, and in an example embodiment cover, the TG 440, the FD region 450, the seventh and eighth contact plugs 466 and 468, the fifteenth to eighteenth wirings 476, 496, 478 and 498, and the eleventh to fourteenth vias 486, 488, 516 and 518.
The thirteenth and fourteenth vias 516 and 518 may contact the fourth and fifth adhesion pads 536 and 538, respectively, in the third adhesion layer 520. Thus, the FD region 450 on the third substrate 400 and electrically connected to the thirteenth via 516 may be electrically connected to the fourth transistor on the second substrate 200 through the second and fourth adhesion pads 296 and 536.
The first to fourth gate electrodes 112, 118, 212 and 216, the first to eighth contact plugs 122, 124, 128, 222, 224, 226, 466, 468, the first to fifteenth vias 142, 144, 148, 178, 242, 244, 246, 248, 276, 278, 486, 488, 516, 518, 688, and the first to eighteenth wirings 132, 152, 134, 154, 138, 158, 232, 252, 234, 254, 236, 256, 238, 258, 476, 496, 478, 498 may include a conductive material, e.g., a metal, a metal nitride, a metal silicide, etc., and the first to fourth insulating interlayers 160, 260, 500 and 670 may include an oxide, e.g., silicon oxide.
The first to fourth adhesion layers 180, 280, 520 and 690 may include an insulating nitride, e.g., silicon nitride, and the first to sixth adhesion pads 198, 296, 298, 536, 538 and 708 may include a metal, e.g., copper.
In example embodiments, a lower planarization layer 710 may be formed on the first surface 401 of the third substrate 400 and the pixel division structure 410, a color filter array layer including color filters 760, a microlens 775 and a transparent protection layer 780 may be stacked on the lower planarization layer 710 in the first region I, and a light blocking metal layer 740, an upper planarization layer 770 and the transparent protection layer 780 may be sequentially stacked on the lower planarization layer 710 in the second region II.
An interference blocking structure 745 between color filters 760 included in the color filter array layer, and a protection layer 750 provided on, and in an example embodiment covering, a surface of the interference blocking structure 745 on the lower planarization layer 710 may be formed in the first region I.
In an example embodiment, the lower planarization layer 710 may include first, second, third, fourth and fifth layers sequentially stacked in the third direction D3. The first, second, third, fourth and fifth layers may include, e.g., aluminum oxide, hafnium oxide, silicon oxide, silicon nitride, and hafnium oxide, respectively.
The interference blocking structure 745 may be formed on the lower planarization layer 710 to overlap the pixel division structure 410 in the third direction D3, and may have a lattice shape in a plan view. In example embodiments, the interference blocking structure 745 may include a first interference blocking pattern 725 and a second interference blocking pattern 735 stacked in the third direction D3. The first interference blocking pattern 725 may include a metal nitride, and the second interference blocking pattern 735 may include a metal. Alternatively, the second interference blocking pattern 735 may include a low refractive index material (LRIM).
The protection layer 750 may include a metal oxide, e.g., aluminum oxide.
The color filter array layer may be formed on the protection layer 750, and may include a plurality of color filters 760. A protection layer 750 may be provided on sidewalls and bottom surfaces of the color filters 760. In an embodiment, sidewalls and bottom surfaces of the color filters 760 may be covered by the protection layer 750. For example, the color filters 760 may include a green color filter G, a blue color filter B and a red color filter R, however, embodiments are not limited thereto.
In example embodiments, the light blocking metal layer 740 may include a barrier pattern 720 and a third conductive pattern 730 stacked in the third direction D3. The barrier pattern 720 may include, e.g., a metal nitride, and the third conductive pattern 730 may include, e.g., a metal.
In example embodiments, the microlens 775 and the upper planarization layer 770 may include substantially the same material, e.g., a photoresist material having a high transmittance. The transparent protection layer 780 may include, e.g., SiO, SiOC, SiC, SiCN, etc.
In the image sensor, the first region I of the second substrate 200 may be divided into the third and fourth regions III and IV by the first isolation structure 900 extending through the first region I of the second substrate 200, which may be the digital block and the analog block, respectively. Thus, electric interference between digital circuits and analog circuits in the digital block and the analog block, respectively, may decrease.
For example, impurities are doped into the second substrate 200 to form a well, and the third and fourth regions III and IV of the second substrate 200 may be divided by the formation of the well. However, if the second substrate 200 has a thin thickness, the formation of the well may not be easy. In example embodiments, even if the second substrate 200 has a thin thickness, the first region I of the second substrate 200 may be divided into the third and fourth regions III and IV by forming the first isolation pattern 205 and the second isolation pattern structure 642, as described below with
Referring to
The first transistor may be formed by forming a first gate electrode 112 on the first region I of the first substrate 100, and doping impurities into upper portions of the first substrate 100 adjacent to the first gate electrode 112 to form first impurity regions 102. Additionally, the second transistor may be formed by forming a second gate electrode 118 on the second region II of the first substrate 100, and doping impurities into upper portions of the first substrate 100 adjacent to the second gate electrode 118 to form second impurity regions 108.
Contact plugs, wirings and vias may be formed to be electrically connected to the first and second transistors.
A first insulating interlayer 160 may be formed on the first substrate 100 and be provided on the first and second transistors, the first, second and third contact plugs 122, 124 and 128, the first to sixth wirings 132, 152, 134, 154, 138 and 158, and the first, second and third vias 142, 144 and 148. In an example embodiment, the first insulating interlayer 160 may be formed on the first substrate 100 and cover on the first and second transistors, the first, second and third contact plugs 122, 124 and 128, the first to sixth wirings 132, 152, 134, 154, 138 and 158, and the first, second and third vias 142, 144 and 148.
Referring to
Referring to
Referring to
Third and fourth transistors may be formed on the first region I of the second substrate 200. In example embodiments, the third and fourth transistors may be formed on the third and fourth regions III and IV, respectively, divided by the first isolation pattern 205 in the first region I of the second substrate 200.
Particularly, the third transistor may be formed by forming a third gate electrode 212 on the third region III of the second substrate 200, and doping impurities into upper portions of the second substrate 200 adjacent to the third gate electrode 212 to form third impurity regions 202. Additionally, the fourth transistor may be formed by forming a fourth gate electrode 216 on the fourth region IV of the second substrate 200, and doping impurities into upper portions of the second substrate 200 adjacent to the fourth gate electrode 216 to form fourth impurity regions 206.
Contact plugs, wirings and vias may be formed to be electrically connected to the third and fourth transistors.
Additionally, a thirteenth wiring 238, an eighth via 248 and a fourteenth wiring 258 may be sequentially stacked on the second region II of the second substrate 200.
A second insulating interlayer 260 may be formed on the second surface 203 of the second substrate 200 and provided on the third and fourth transistors, the fourth to sixth contact plugs 222, 224 and 226, the seventh to fourteenth wirings 232, 252, 234, 254, 236, 256, 238 and 258, and the fifth to eighth vias 242, 244, 246 and 248. In an example embodiment, the second insulating interlayer 260 may be formed on the second surface 203 of the second substrate 200 and cover on the third and fourth transistors, the fourth to sixth contact plugs 222, 224 and 226, the seventh to fourteenth wirings 232, 252, 234, 254, 236, 256, 238 and 258, and the fifth to eighth vias 242, 244, 246 and 248.
Ninth and tenth vias 276 and 278 may be formed through an upper portion of the second insulating interlayer 260 to contact upper surfaces of the twelfth and fourteenth wirings 256 and 258, respectively, a second adhesion layer 280 may be formed on the second insulating interlayer 260 and the ninth and tenth vias 276 and 278, and second and third adhesion pads 296 and 298 may be formed through the second adhesion layer 280 to contact the ninth and tenth vias 276 and 278, respectively, on the first and second regions I and II, respectively, of the second substrate 200.
Referring to
In example embodiments, p-type well doped with p-type impurities, e.g., boron may be formed in the third substrate 400.
The pixel division structure 410 may extend in the third direction D3 toward the first surface 401 downwardly in an inside of the first region I and at a boundary between the first and second regions I and II, and the fifth impurity region 420 doped with p-type impurities, e.g., boron may be formed at a portion of the third substrate 400 adjacent to the pixel division structure 410. An impurity concentration of the fifth impurity region 420 may be higher than an impurity concentration of the p-type well.
In example embodiments, the pixel division structure 410 may have a shape of a polygon, e.g., a rectangle, in a plan view, and thus unit pixel regions in which unit pixels are formed, which may be surrounded by the pixel division structure 410, may be defined in the first region I of the third substrate 400.
The light sensing element 430 may be formed by doping n-type impurities, e.g., phosphorus into the p-type well in the first region I of the third substrate 400.
The TG 440 may be formed by forming a trench extending in the third direction D3 from the second surface 403 of the third substrate 400 downwardly, and filling a conductive material in the trench to protrude from the second surface 403 of the third substrate 400 upwardly.
N-type impurities, e.g., phosphorus may be doped into an upper portion of the third substrate 400 adjacent to the TG 440 to form an FD region 450.
Referring to
One or ones of the wirings, e.g., the eighteenth wiring 498 may extend from the first region I of the third substrate 400 to the second region II of the third substrate 400.
A third insulating interlayer 500 may be formed on the second surface 403 of the third substrate 400 and provided on, and in an example embodiment covering, the TG 440, the FD region 450, the seventh and eighth contact plugs 466 and 468, the fifteenth to eighteenth wirings 476, 496, 478 and 498, and the eleventh and twelfth vias 486 and 488.
Thirteenth and fourteenth vias 516 and 518 may be formed through an upper portion of the third insulating interlayer 500 to contact upper surfaces of the sixteenth and eighteenth wirings 496 and 498, respectively, a third adhesion layer 520 may be formed on the third insulating interlayer 500 and the thirteenth and fourteenth vias 516 and 518, and fourth and fifth adhesion pads 536 and 538 may be formed through the third adhesion layer 520 to contact the thirteenth and fourteenth vias 516 and 518, respectively, on the first and second regions I and II, respectively, of the third substrate 400.
Referring to
Referring to
A first insulation layer 620 may be formed on the upper surface of the first isolation pattern 205 exposed by the first opening 610, a sidewall of the first opening 610 and the first surface 201 of the second substrate 200, and a first conductive layer 630 may be formed on the first insulation layer 620 to fill the first opening 610.
Hereinafter, portions of the first insulation layer 620 and the first conductive layer 630 in the first opening 620 may be referred to as a first insulation pattern 622 and a first conductive pattern 632, respectively, which may form a second isolation pattern structure 642. Additionally, the first isolation pattern 205 and the second isolation pattern structure 642 stacked in the third direction D3 in the first region I of the second substrate 200 may form a first isolation structure 900.
The first region I of the second substrate 200 may be divided into third and fourth regions III and IV by the first isolation structure 900 in the first region I of the second substrate 200.
Referring to
A second insulation layer may be formed on the upper surface of the thirteenth wiring 238 exposed by the second opening 640, a sidewall of the second opening 640 and an upper surface of the first conductive layer 630, and may be partially removed by an anisotropic etching process. Thus, a second insulation pattern 655 may be formed on the sidewall of the second opening 640.
A second conductive layer may be formed on the thirteenth wiring 238, a sidewall and an upper surface of the second insulation pattern 655 to fill the second opening 640, and an upper portion of the second conductive layer may be planarized until the upper surface of the first conductive layer 630 is exposed. Thus, a second conductive pattern 665 may be formed in the second opening 640.
The second insulation pattern 655 and the second conductive pattern 665 may form a first through electrode structure 675.
Referring to
A fourth adhesion layer 690 may be formed on the fourth insulating interlayer 670 and the fifteenth via 688, and a sixth adhesion pad 708 may be formed through the fourth adhesion layer 690 to contact the fifteenth via 688.
The second and third substrates 200 and 400 bonded with each other may be overturned again, and the first and second substrates 100 and 200 may be bonded with each other so that the fourth adhesion layer 690 may contact the first adhesion layer 180, and during the bonding, the sixth adhesion pad 708 may contact the first adhesion pad 198.
Referring to
Thus, an upper surface of the pixel division structure 410 may be exposed, and as a result, the pixel division structure 410 may extend through the third substrate 400.
In example embodiments, the upper portion of the third substrate 400 may be performed by a polishing process, e.g., a grinding process, a chemical mechanical polishing (CMP) process, etc.
Referring to
A barrier layer and a third conductive layer may be sequentially formed on an upper surface of the lower planarization layer 710, and portions of the third conductive layer and the barrier layer in the first region I may be patterned to form a second interference blocking pattern 735 and a first interference blocking pattern 725, respectively, and portions of the barrier layer and the third conductive layer in the second region II may remain as a barrier pattern 720 and a third conductive pattern 730, respectively.
The barrier pattern 720 and the third conductive pattern 730 may form a light blocking metal layer 740, and the first and second interference blocking patterns 725 and 735 may form an interference blocking structure 745.
A protection layer 750 may be formed on the lower planarization layer 710 and the interference blocking structure 745 in the first region I.
Referring to
In example embodiments, the color filters 760 may be formed by depositing a color filter layer on the protection layer 750 and the light blocking metal layer 740 through, e.g., a spin coating process, and performing an exposure process and a developing process on the color filter layer. In an example embodiment, each of the color filters 760 may be formed on each of the unit pixel regions defined by the pixel division structure 410. Alternatively, each of the color filters 760 may be formed on neighboring ones of the unit pixel regions.
An upper planarization layer 770 may be formed on the color filter array layer, the protection layer 750 and the light blocking metal layer 740, and a patterning process and a reflow process may be performed on the upper planarization layer 770 in the first region I to form a microlens 775.
A transparent protection layer 780 may be formed on the microlens 775 and the upper planarization layer 770 to complete the fabrication of the image sensor.
As illustrated above, in the first region I of the second substrate 200, the portion of the second substrate 200 adjacent to the second surface 203 may be removed to form the recess, the first isolation pattern 205 may be formed to fill the recess, the portion of the second substrate 200 adjacent to the first surface 201 may be removed to form the first opening 610, and the second isolation pattern structure 642 may be formed to fill the first opening 610.
Thus, the first region I of the second substrate 200 may be divided into the third and fourth regions III and IV to be electrically insulated from each other by the first isolation structure 900 including the first isolation pattern 205 and the second isolation pattern structure 642 stacked in the third direction D3.
Referring to
In example embodiments, the second isolation structure 905 may further include a third insulation pattern 802 in the first opening 610 in addition to the first isolation pattern 205, and the third insulation pattern 802 may also be referred to as a third isolation pattern.
The third isolation pattern 802 may include a metal oxide, e.g., aluminum oxide, hafnium oxide, etc., or silicon oxide, e.g., TEOS. In example embodiments, the third isolation pattern 802 may include a material substantially the same as that of the second insulation pattern 655 included in the first through electrode structure 675.
Referring to
The second and third substrates 200 and 400 bonded with each other may be overturned, the portion of the first region I of the second substrate 200 adjacent to the first surface 201 may be removed to form the first opening 610 exposing the upper surface of the first isolation pattern 205, and the second opening 640 may be formed through the second region II of the second substrate 200 and an upper portion of the second insulating interlayer 260 to expose the upper surface of the thirteenth wiring 238.
A third insulation layer 800 may be formed on the upper surfaces of the first isolation pattern 205 and the thirteenth wiring 238, the sidewalls of the first and second openings 610 and 640, and the first surface 201 of the second substrate 200.
In example embodiments, the first opening 610 may have a width less than that of the second opening 640, and the third insulation layer 800 may entirely fill the first opening 610, but may be formed only on the sidewall of the second opening 640.
Referring to
Additionally, a portion of the third insulation layer 800 on the upper surface of the thirteenth wiring 238 may be removed to form a fourth insulation pattern 805 on the sidewall of the second opening 640.
A fourth conductive layer may be formed on the upper surface of the thirteenth wiring 238, a sidewall and an upper surface of the fourth insulation pattern 805, the first surface 201 of the second substrate 200 and an upper surface of the third insulation pattern 802 to fill the second opening 640, and the fourth conductive layer may be planarized until the first surface 201 of the second substrate 200 is exposed to form a fourth conductive pattern 815 in the second opening 640.
The fourth insulation pattern 805 and the fourth conductive pattern 815 may form a second through electrode structure 825.
Processes substantially the same as or similar to those illustrated with reference to
As illustrated above, the first and second openings 610 and 640 may be formed in the first and second regions I and II of the second substrate 200, the third insulation layer 800 may be formed to fill the first opening 610 and on the sidewall of the second opening 640, the third insulation layer 800 may be etched to form the fourth insulation pattern 805, and the fourth conductive pattern 815 may be formed to fill a remaining portion of the second opening 640.
Thus, the third isolation pattern 802 may be formed on the first isolation pattern 205 in the first region I of the second substrate 200 to form the second isolation structure 905, and the second through electrode structure 825 including the fourth conductive pattern 815 and the fourth insulation pattern 805 may be formed on the second region II of the second substrate 200.
Referring to
The above structure may be implemented by forming the third insulation layer 800 through processes illustrated with reference to
A portion of the third insulation layer 800 in the first opening 610 may be referred to as the third insulation pattern 802 or the third isolation pattern 802, and the first and third isolation patterns 205 and 802 may form the second isolation structure 905.
Additionally, a portion of the third insulation layer 800 filling the second opening 640 and provided on, and in an example embodiment covering, a sidewall of the fourth conductive pattern 815 protruding from the first surface 201 of the second substrate 200 downwardly may be referred to as the fourth insulation pattern 805, and the fourth conductive pattern 815 and the fourth insulation pattern 805 may form the second through electrode structure 825.
The image sensor may be the image sensors illustrated with reference to
Referring to
The camera module group 1100 may include a plurality of camera modules 1100a, 1100b and 1100c.
Hereinafter, an example configuration of the camera module 1100b is described with reference to
Referring to
The prism 1105 may include a reflection surface 1107 that may change a path of a light L incident onto the prism 1105.
In example embodiments, the prism 1105 may change the path of the light L incident in a first direction X to a second direction Y perpendicular to the first direction X. In addition, the prism 1105 may rotate the reflection surface 1107 around a center axis 1106 in A direction and/or rotate the center axis 1106 in a B direction to align the path of the reflected light along the second direction Y. The OPFE 1110 may move in a third direction Z perpendicular to the first direction X and the second direction Y.
In example embodiments, a rotation angle of the prism 1105 may be equal to or less than about 15 degrees in the positive (+) A direction and equal to or more than about 15 degrees in the negative (−) A direction, but embodiments are not limited thereto.
In example embodiments, the prism 1105 may rotate within about 20 degrees, between about 10 degrees and about 20 degrees, or between about 15 degrees to about 20 degrees in the positive or negative B direction.
In example embodiments, the prism 1105 may move the reflection surface 1107 in the third direction Z that is in parallel with the center axis 1106.
The OPFE 1110 may include optical lenses that are divided into m groups where m is a positive integer. The m lens group may move in the second direction Y to change an optical zoom ratio of the camera module 1100b. For example, the optical zoom ratio may be changed in a range of 3K, 5K, and so on by moving the m lens group, when K is a basic optical zoom ratio of the camera module 1100b.
The actuator 1130 may move the OPFE 1110 or the optical lens to a specific position. For example, the actuator 1130 may adjust the position of the optical lens for accurate sensing such that an image sensor 1142 may be located at a position corresponding to a focal length of the optical lens.
The image sensing device 1140 may include the image sensor 1142, a control logic 1144 and a memory 1146. The image sensor 1142 may be substantially the same as or similar to that of
The memory 1146 may store information such as calibration data 1147 for the operation of the camera module 1100b. For example, the calibration data 1147 may include information for generation of image data based on the provided light L, such as information on the above-described rotation angle, a focal length, an optical axis, and so on. If the camera module 1100b is implemented as a multi-state camera having a variable focal length depending on the position of the optical lens, the calibration data 1147 may include multiple focal length values and auto-focusing values corresponding to the multiple states.
The storage device 1150 may store the image data sensed via the image sensor 1142. The storage device 1150 may be disposed at an outside of the image sensing device 1140, and may be stacked with a sensor chip including the image sensing device 1140. The storage device 1150 may be implemented with an electrically erasable programmable read-only memory (EEPROM), but embodiments are not limited thereto.
Referring to
In example embodiments, one camera module 1100b may have a folded lens structure including the above-described prism 1105 and the OPFE 1110, and the other camera modules 1100a and 1100b may have a vertical structure without the prism 1105 and the OPFE 1110, however, embodiments are not limited thereto.
In example embodiments, one camera module 1100c may be a depth camera configured to measure distance information of an object using an infrared (IR) light. In this case, the application processor 1200 may merge the distance information provided from the depth camera 1100c and image data provided from the other camera modules 1100a and 1100b to generate a three-dimensional depth image.
In example embodiments, at least two camera modules, for example, the camera modules 1100a and 1100b among the camera modules 1100a, 1100b and 1100c may have different field of views, for example, through different optical lenses.
In example embodiments, the camera modules 1100a, 1100b and 1100c may be separated physically from each other. In other words, the camera modules 1100a, 1100b and 1100c may each include a dedicated image sensor 1142.
The application processor 1200 may include an image processing device 1210, a memory controller 1220 and an internal memory 1230. The application processor 1200 may be separated from the camera modules 1100a, 1100b and 1100c. For example, the application processor 1200 may be implemented as one chip and the camera modules 1100a, 1100b and 1100c may implemented as another chip or other chips.
The image processing device 1210 may include a plurality of sub image processors 1212a, 1212b and 1212c, an image generator 1214 and a camera module controller 1216.
The image data generated by the camera modules 1100a, 1100b and 1100c may be provided to the sub image processors 1212a, 1212b and 1212c through distinct image signal lines ISLa, ISLb and ISLc, respectively. For example, image data generated from the camera module 1100a may be provided to the sub image processor 1212a through the image signal line LSLa, image data generated from the camera module 1100b may be provided to the sub image processor 1212b through the image signal line LSLb, and image data generated from the camera module 1100c may be provided to the sub image processor 1212c through the image signal line LSLc. The transfer of the image data may be performed using a camera serial interface (CSI) based on the mobile industry processor interface (MIPI), however, embodiments are not limited thereto.
In example embodiments, one sub image processor may be assigned commonly to two or more camera modules. In this case, a multiplexer may be used to transfer the image data selectively from one of the camera modules to the shared sub image processor.
The image data from the sub image processors 1212a, 1212b and 1212c may be provided to the image generator 1214. The image generator 1214 may generate an output image using the image data from the sub image processors 1212a, 1212b and 1212c according to image generating information or a mode signal.
For example, the image generator 1214 may merge at least a portion of the image data from the camera modules 1100a, 1100b and 1100c having the different fields of view to generate the output image according to the image generating information or the mode signal. In addition, the image generator 1214 may select, as the output image, one of the image data from the camera modules 1100a, 1100b and 1100c according to the image generating information or the mode signal.
In example embodiments, the image generating information may include a zoom factor or a zoom signal. In example embodiments, the mode signal may be a signal based on a selection of a user.
If the image generating information is the zoom factor and the camera modules 1100a, 1100b and 1100c have the different field of views, the image generator 1214 may perform different operations depending on the zoom signal. For example, if the zoom signal is a first signal, the image generator 1214 may merge the image data from the different camera modules to generate the output image. If the zoom signal is a second signal different from the first signal, the image generator 1214 may select, as the output image, one of image data from the camera modules 1100a, 1100b and 1100c.
In example embodiments, the image generator 1214 may receive the image data of different exposure times from the camera modules 1100a, 1100b and 1100c. In this case, the image generator 1214 may perform high dynamic range (HDR) processing with respect to the image data from the camera modules 1100a, 1100b and 1100c to generate the output image having the increased dynamic range.
The camera module controller 1216 may provide control signals to the camera modules 1100a, 1100b and 1100c. The control signals generated by the camera module controller 1216 may be provided to the camera modules 1100a, 1100b and 1100c through the distinct control signal lines CSLa, CSLb and CSLc, respectively.
In example embodiments, one of the camera modules 1100a, 1100b and 1100c may be designated as a master camera according to the image generating information of the mode signal, and the other camera modules may be designated as slave cameras. These data may be included in the control signal, and may be provided to corresponding camera modules 1100a, 1100b and 1100c through the distinct control signal lines CSLa, CSLb and CSLc.
The camera module acting as the master camera may be changed according to the zoom factor or an operation mode signal. For example, if the camera module 1100a has the wider field of view than the camera module 1100b and the zoom factor indicates a lower zoom magnification, the camera module 1100b may be designated as the master camera. In contrast, if the zoom factor indicates a higher zoom magnification, the camera module 1100a may be designated as the master camera.
In example embodiments, the control signals provided from the camera module controller 1216 may include a synch enable signal. For example, if the camera module 1100b is the master camera and the camera modules 1100a and 1100c are the slave cameras, the camera module controller 1216 may provide the synch enable signal to the camera module 1100b. The camera module 1100b may generate a synch signal based on the provided synch enable signal and provide the synch signal to the camera modules 1100a and 1100c through a synch signal line SSL. As such, the camera modules 1100a, 1100b and 1100c may transfer the synchronized image data to the application processor 1200 based on the synch signal.
In example embodiments, the control signals provided from the camera module controller 1216 may include information on the operation mode. The camera modules 1100a, 1100b and 1100c may operate in a first operation mode or a second operation mode based on the information from the camera module controller 1216.
In the first operation mode, the camera modules 1100a, 1100b and 1100c may generate image signals with a first speed (e.g., a first frame rate) and encode the image signals with a second speed higher than the first speed (e.g., a second frame rate higher than the first frame rate) to transfer the encoded image signals to the application processor 1200. The second speed may be lower than thirty times the first speed. The application processor 1200 may store the encoded image signals in the internal memory 1230 or the external memory 1400. The application processor 1200 may read out and decode the encoded image signals to provide display data to a display device. For example, the sub image processors 1212a, 1212b and 1212c may perform the decoding operation and the image generator 1214 may process the decoded image signals.
In the second operation mode, the camera modules 1100a, 1100b and 1100c may generate image signals with a third speed lower than the first speed (e.g., the third frame rate lower than the first frame rate) to transfer the generated image signals to the application processor 1200. In other words, the image signals that are not encoded may be provided to the application processor 1200. The application processor 1200 may process the received image signals or store the receive image signals in the internal memory 1230 or the external memory 1400.
The internal memory 1230 may be controlled by the memory controller 1220.
The PMIC 1300 may provide a power supply voltage to the camera modules 1100a, 1100b and 1100c, respectively. For example, the PMIC 1300 may provide, under control of the application processor 1200, a first power to the camera module 1100a through a power line PSLa, a second power to the camera module 1100b through a power line PSLb, and a third power to the camera module 1100c through a power line PSLc.
The PMIC 1300 may generate the power respectively corresponding to the camera modules 1100a, 1100b and 1100c and control power levels, in response to a power control signal PCON from the application processor 1200. The power control signal PCON may include information on the power depending on the operation modes of the camera modules 1100a, 1100b and 1100c. For example, the operation modes may include a low power mode in which the camera modules 1100a, 1100b and 1100c operate in low powers. The power levels of the camera modules 1100a, 1100b and 1100c may be the same as or different from each other. In addition, the power levels may be changed dynamically or adaptively.
In an image sensor in accordance with one or more example embodiments, the isolation structure may be formed through the substrate including the analog block and the digital block in which the analog circuit pattern and the digital circuit pattern are formed, so that the analog block and the digital block may be electrically insulated from each other. Accordingly, in one or more example embodiments, an electric interference and noise between the analog circuit pattern and the digital circuit pattern may be reduced.
While aspects of example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0095895 | Aug 2022 | KR | national |
