1. Field of the Invention
2. Description of the Related Art
Referring to
The substrate 10 has an first surface 12 on which plurality of first electrodes 15 are formed, and a second surface 14 on which plurality of second electrodes 16 are formed, the first electrodes 15 are corresponding to electrically connect to the second electrodes 16.
The frame layer 18 has a upper surface 20 and a lower surface 22, the lower surface 22 of the frame layer 18 is adhered on the first surface 22 of the substrate 10 to form a cavity 24.
The chip 26 is arranged on the first surface 12 of the substrate 10, and is located within the cavity 24, and is formed with bonding pads 27.
The wire 28 has a first end 30 and a second end 32, the first end 30 is electrically connected the bonding pad 27 of the chip 26, the second end 30 is electrically connected the first electrodes 15 of the substrate 10.
The transparent layer 34 is adhered on the upper surface 20 of the frame layer 18.
An objective of the invention is to provide an image sensor package structure and method for manufacturing the same, and capable of decreasing the size of the package.
To achieve the above-mentioned object, the invention includes a substrate, a chip, a plurality of wires, and a frame layer. The substrate has an upper surface, which is formed with first electrodes, and a lower surface, which is formed with second electrodes corresponding to electrically connect to the first electrodes. The chip has a sensor region and a plurality of bonding pads located at the side of the sensor region of the chip, and is mounted on the upper surface of the substrate. The plurality of wires are electrically connected the bonding pads of the chip to the first electrodes of the substrate. The frame layer is inserted with a transparent layer, and is arranged on the upper surface of the substrate to cover the chip.
Please refer to
The substrate 40 has an upper surface 50, which is formed with a first electrodes 54, and a lower surface 52, which is formed with second electrodes 56 corresponding to electrically connect to the first electrodes 54.
The chip 42 has a sensor region 58 and a plurality of bonding pads 60 located at the side of the sensor region 58 of the chip 42, and is mounted on the upper surface 50 of the substrate 40.
The plurality of wires 44 are electrically connected the bonding pads 60 of the chip 42 to the first electrodes 54 of the substrate 40.
The frame layer 46 is inserted with a transparent layer 48, and is arranged on the upper surface 50 of the substrate 40 to cover the chip 42.
Please refer to
Please refer to
Providing a substrate 40 has an upper surface 50, which is formed with a first electrodes 54, and a lower surface 52, which is formed with second electrodes 56 corresponding to electrically connect to the first electrodes 54.
Providing a chip 42 has a sensor region 58 and a plurality of bonding pads 60 located at the side of the sensor region 58 of the chip 42, and is mounted on the upper surface 50 of the substrate 40.
Providing a plurality of wires 44 are electrically connected the bonding pads 60 of the chip 42 to the first electrodes 54 of the substrate 40.
Providing a frame layer 46 is inserted with a transparent layer 48, and is arranged on the upper surface 50 of the substrate 40 to cover the chip 42. The frame layer 46 is formed with a protection layer 62, and is located under the transparent layer 48 to surround the sensor region 58 of the chip 42.
While the invention has been described by the way of an example and in terms of a preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.
The is a continuation-in-part application of applicant's U.S. patent application Ser. No. 11/404,730, filed on Apr. 14, 2006.
Number | Date | Country | |
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Parent | 11404730 | Apr 2006 | US |
Child | 11986227 | Nov 2007 | US |