Patent Application
20090008729
The present invention relates to a structure of an image sensor package, and more particularly, to a structure of an image sensor utilizing a removable protection film.
In the field of semiconductor devices, the device density is increased and the device dimension is reduced continuously. The demand for the packaging or interconnecting techniques in such high density devices is also increased to fit the situation mentioned above. Conventionally, in the flip-chip attachment method, an array of solder bumps is formed on the surface of the die. The formation of the solder bumps may be carried out by using a solder composite material through a solder mask for producing a desired pattern of solder bumps. The function of chip package includes power distribution, signal distribution, heat dissipation, protection and support . . . and so on. As semiconductor becomes more complicated, the traditional package technique, for example lead frame package, flex package, rigid package technique, can not meet the demand of producing smaller chip with high density elements on the chip.
Complementary metal-oxide semiconductor (CMOS) devices are increasingly in demand for use with electronic devices such as digital cameras. Conventionally, these sensors have been packaged for use by mounting them to a substrate and enclosing them within a housing assembly. The housing assembly incorporates a transparent lid to allow light or other forms of radiation to be received by the sensor. The lid may be a flat window or shaped as a lens to provide optical properties. Due to the conventional structure involved, this packaging technique may be expensive and difficult to manufacture. U.S. Pat. No. 6,809,008 assigned to Motorola, Inc. (Schaumburg, Ill.) disclosed an exemplary system and method for providing an integrated photosensing element suitably adapted for use in CMOS imaging applications.
Furthermore, because conventional package technologies have to divide a dice on a wafer into respective dies and then package the die respectively, therefore, these techniques are time consuming for manufacturing process. Since the chip package technique is highly influenced by the development of integrated circuits, therefore, as the size of electronics has become demanding, so does the package technique. For the reasons mentioned above, the trend of package technique is toward ball grid array (BGA), flip chip (FC-BGA), chip scale package (CSP), Wafer level package (WLP) today. “Wafer level package” is to be understood as meaning that the entire packaging and all the interconnections on the wafer as well as other processing steps are carried out before the singulation (dicing) into chips (dies). Generally, after completion of all assembling processes or packaging processes, individual semiconductor packages are separated from a wafer having a plurality of semiconductor dies. The wafer level package has extremely small dimensions combined with extremely good electrical properties.
WLP technique is an advanced packaging technology, by which the die are manufactured and tested on the wafer, and then singulated by dicing for assembly in a surface-mount line. Because the wafer level package technique utilizes the whole wafer as one object, not utilizing a single chip or die, therefore, before performing a scribing process, packaging and testing has been accomplished; furthermore, WLP is such an advanced technique so that the process of wire bonding, die mount and under-fill can be omitted. By utilizing WLP technique, the cost and manufacturing time can be reduced, and the resulting structure of WLP can be equal to the die; therefore, this technique can meet the demands of miniaturization of electronic devices.
Though the advantages of WLP technique mentioned above, some issues still exist influencing the acceptance of WLP technique. For example, although utilizing WLP technique can reduce the CTE mismatch between IC and the interconnecting substrate, as the size of the device minimizes, the CTE difference between the materials of a structure of WLP becomes another critical factor to mechanical instability of the structure. Furthermore, in this wafer-level chip-scale package, a plurality of bond pads formed on the semiconductor die is redistributed through conventional redistribution processes involving a redistribution layer (RDL) into a plurality of metal pads in an area array type. Solder balls are directly fused on the metal pads, which are formed in the area array type by means of the redistribution process. Typically, all of the stacked redistribution layers are formed over the built-up layer over the die. Therefore, the thickness of the package is increased. This may conflict with the demand of reducing the size of a chip.
Regarding that the conventional methods of packaging image sensor device either using the Chip On Board (COB) or using the Leadless Carrier Cavity (LCC) with wire bonding structure suffered the yield problem during process, it was due to the particle contamination on the micro lens area which can not be removed after process.
Therefore, the present invention provides a solution to the aforementioned problem to protect the micro lens area from particle contamination and to reduce the thickness of the die package during the entire process.
In accordance with the present invention, there is provided a structure of image sensor package comprising a substrate with a die receiving hole formed therein and inter-connecting through holes formed there through. Terminal pads are formed under the inter-connecting through holes and first pads are formed on an upper surface of the substrate. A die having a micro lens area is disposed within the die receiving hole by an adhesion material. Second pads (I/O pads) are formed on the upper edge of the die. Connecting structures formed on the die and the substrate for electrical communication are coupled to the first pads and the second pads. A protection layer is formed on the micro lens area to protect the micro lens from particle contamination. A removable protection film is formed over the protection layer to protect the micro lens from water, oil, dust, and temporary impact. The removable protection film is removed after the formation of the image sensor package and before mounting the lens holder on the top of micro lens area to form the image sensor module.
In accordance with another aspect of the present invention, there is provided a method for assembling image sensor package comprising coating a protection layer with water and oil repellency onto a silicon substrate with micro lens; coating a removable protection film onto the protection layer; opening non-micro lens areas of the substrate; mounting the image sensor package on a printed circuit board (PCB) by the surface mounting technology (SMT) process; and stripping away the removable protection film from the micro lens area. The step of opening non-micro lens areas of the substrate comprises exposure and developing processes to open the non-micro lens areas. Further, the method comprises forming redistribution lines (RDL) or wire bonding before coating a top protection layer and mounting a lens holder on the CMOS Image Sensor (CIS) package area to form a module.
One advantage of the present invention is the removable protection film coated on the micro lens after the wafer fabs out and/or after the protection layer with water and oil repellency is coated.
Another advantage of the present invention is the removable protection film which can be temporarily struck on the micro lens area during the packaging and assembling process.
A still further advantage of the present invention is the removable protection film which can prevent any particle contamination on the micro lens area during the packaging and assembling process.
Another advantage of the present invention is the removable protection film which can be stripped away from the micro lens area after the packaging and assembling process is completed and before a lens holder is put on the die package.
A still further advantage of the present invention is the removable protection film which promotes the easiness and the highest yield of the process.
A still further advantage of the present invention is that no clean process is needed by utilizing the removable protection film.
Another advantage of the present invention is the removable protection film which can be widely applied in many kinds of packaging and assembling processes such as COB, LCC, CSP, FO-WLP, etc.
These and other advantages will become apparent from the following description of preferred embodiments taken together with the accompanying drawings and the appended claims.
The invention will now be described in greater detail with preferred embodiments of the invention and drawings attached. However, it should be appreciated that the preferred embodiments of the invention are described only for illustrating but not for limiting the claims of the invention. Besides the preferred embodiments mentioned herein, the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited expect as specified in the accompanying claims.
The present invention discloses a structure of an image sensor package utilizing a removable protection film.
Furthermore, barrier layers 10 may be formed on the side wall of the substrate 1 for better adhesion with the adhesion material 7 as illustrated in
With reference to
Preferably, the material of the substrate 1 is an organic substrate such as FR5, FR4, BT (Bismaleimide triazine), PCB with defined opening or Alloy42 with pre-etching circuit. Preferably the organic substrate with high Glass transition temperature (Tg) is epoxy type FR5 or BT (Bismaleimide triazine) type substrate for better process performance. The Alloy42 is composed of 42% Ni and 58% Fe. Kovar can also be used and is composed of 29% Ni, 17% Co, and 54% Fe. The glass, ceramic, or silicon can be used as the substrate due to lower CTE.
In one embodiment of the present invention, the dielectric layer 15 and the top dielectric layer 16 is preferably an elastic dielectric material which is made by silicone dielectric based materials comprising siloxane polymers (SINR), Dow Coming WL5000 series, and composites thereof. In another embodiment, the dielectric layer 15 and the top dielectric layer 16 is made by a material comprising benzocyclobutene (BCB), epoxy, polyimides (PI) or resin. Preferably, it is a photosensitive layer for simple process.
In one embodiment of the present invention, the elastic dielectric layer is a kind of material with CTE larger than 100 (ppm/° C.), elongation rate about 40 percent (preferably 30 percent-50 percent), and the hardness of the material is between plastic and rubber. The thickness of the elastic dielectric layer 15 depends on the stress accumulated in the RDL/dielectric layer interface during temperature cycling test.
In one embodiment of the invention, the material of the RDLs 14 comprise Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy; the thickness of the RDLs 14 is between 2 um and 15 um. The Ti/Cu alloy is formed by sputtering technique also as seed metal layers, and the Cu/Au or Cu/Ni/Au alloy is formed by electro-plating; exploiting the electro-plating process to form the RDLs can make the RDLs thick enough to withstand CTE mismatching during temperature cycling. The bonding pads 4 can be Al or Cu or combination thereof. If the structure in
The substrate could be round type such as wafer type, wherein the diameter could be 200, 300 mm or higher. Otherwise, the substrate could be rectangular type such as panel form, and the dimension could be fit into the wire bonder machine. As shown in
The process for the present invention includes coating a protection layer which has water and oil repellency onto the silicon wafer 18 with a thickness around 0.1 um to 0.3 um. Then, a removable protection film is coated onto the protection layer with a thickness around 5 um to 12 um, followed by using exposure and developing processes to open the non-micro lens areas with the removable protection film as illustrated in
Although preferred embodiments of the present invention have been described, it will be understood by those skilled in the art that the present invention should not be limited to the described preferred embodiments. Rather, various changes and modifications can be made within the spirit and scope of the present invention, as defined by the following claims.
