Patent Application
20230282656
The present invention relates to an image sensor comprising an image sensor layer and a capacitor layer.
Image sensors are in wide use in all kinds of electronic devices. For example, there is a recent trend for equipping mobile phones with more and more cameras. At the same time, requirements on image quality increases.
Image sensors generally include photo-sensitive elements, such as CCD sensors or photodiodes. The photo-sensitive element (or elements) in an image sensor pixel may generate a charge that is dependent on the amount of light that is hitting the photo-sensitive element. By measuring the amount of charge generated, the amount of light hitting the image sensor pixel can be determined.
According to one approach using photo-diodes (which may be part of corresponding transistors), photo-currents from pixels may be read out row by row, using a so-called rolling shutter scheme. This approach, however, has inherent problems with image distortion when imaging moving objects.
At least for demanding applications, such as in the industrial sector, the rolling shutter scheme is therefore increasingly replaced by a so-called global shutter scheme, according to which the photo-currents from all pixels in the image sensor are read out simultaneously. Although not suffering from the above-described kind of image distortion of the rolling shutter scheme, the global shutter scheme practically requires a charge storage capacitor per pixel in the image sensor.
The charge storage capability of the charge storage capacitors limits the dynamic range in the pixel. Once the charge storage capacitor of an image sensor pixel is “full”, that pixel is saturated. The obvious solution is to increase the size of the charge storage capacitors, which, however, goes against the desire for higher resolution images and ever smaller and cheaper image sensors.
Different solutions to this problem have been presented, in which the image sensor is provided as a layered image sensor with an image sensor layer including the photo-sensitive elements, and an auxiliary layer including charge storage capacitors. The image sensor layer and the auxiliary layer are bonded together to form the image sensor. Variations of this approach are described in, for example, US 2010/0238334, US 2017/0170224, and US 2017/0345854. Although having advantages over image sensors in which the photo-sensitive element and charge storage capacitor of a pixel are formed in the same layer, there is still room for improvement in relation to the solutions described in these documents.
It would thus be desirable to provide an improved image sensor, in particular an image sensor that provides for an improved relation between image resolution and dynamic range and/or more cost-efficient production.
It is an object of the present invention to provide an improved image sensor, in particular an image sensor that provides for an improved relation between image resolution and dynamic range, and/or more cost-efficient production.
According to a first aspect of the present invention, it is therefore provided an image sensor comprising: an image sensor layer having: a plurality of image sensor layer contact pads; and a plurality of photo-sensitive elements, each being coupled to a respective image sensor layer contact pad in the plurality of image sensor layer contact pads; and a capacitor layer having: a plurality of first capacitor contact structures, each being constituted by a capacitor layer top contact pad bonded to a respective image sensor layer contact pad in the plurality of image sensor layer contact pads of the image sensor layer; a plurality of second capacitor contact structures; and a plurality of capacitors, embedded in a first dielectric material, each capacitor including at least one electrically conductive vertical nanostructure, the at least one electrically conductive vertical nanostructure being electrically conductively connected to one of a respective first capacitor contact structure and a respective second capacitor contact structure, and conductively separated from the other one of the respective first capacitor contact structure and the respective second capacitor contact structure by a layer of a second dielectric material, different from the first dielectric material, conformally coating the at least one electrically conductive vertical nanostructure.
By “vertical” nanostructure should be understood a nanostructure that is arranged perpendicular to a plane parallel to the capacitor layer (and thus to the image sensor, which is a layered structure).
An electrically conductive nanostructure may be formed from an electrically conductive material, or it may be formed from an electrically insulating material and conformally coated with a conductive material, such as a metal.
The present invention is based on the realization that a favorable combination of high dynamic range, high resolution and cost-efficient production for an image sensor can be achieved by providing a capacitor layer with nanostructure-based capacitors embedded in a dielectric material. In particular, the present inventors have found that the use of electrically conductive vertical nanostructures provides for an exceptionally high capacitance per surface area of the capacitor layer, and that capacitors including such electrically conductive vertical nanostructures can be embedded in a dielectric material, which provides for cost-efficient production. In particular, a capacitor layer in which capacitors are embedded in a dielectric material can be made considerably less brittle than a capacitor layer in which the capacitors are formed by etching an inherently brittle semiconductor material, such as silicon. Examples of such more brittle capacitor layers may include capacitor layers in which the capacitors are so-called deep trench type capacitors (TSC) and similar.
According to embodiments, the first dielectric material may have a first relative permittivity, and the second dielectric material may have a second relative permittivity that is at least twice the first relative permittivity.
Hereby, a high capacitance density is provided for, while reducing the parasitic capacitances and/or reducing the risk of cross-talk between capacitors of different image sensor pixels.
According to one non-limiting example, the first relative permittivity may be lower than 3.9, preferably lower than 3.5, and the second relative permittivity may be higher than 7.8, preferably higher than 20.
In embodiments, each capacitor in the plurality of capacitors may be separated from neighboring capacitors in the plurality of capacitors by the first dielectric material. Advantageously, the capacitors may be completely separated from each other by the first dielectric material, to effectively reduce parasitic capacitances and/or cross-talk.
The at least one electrically conductive vertical nanostructure included in each capacitor in the plurality of capacitors has a height and a maximum width, and a ratio between the height and the maximum width may advantageously be at least 5 times.
For instance, the height may be at least 1 μm, and the maximum width may be less than 200 nm.
The “height” of the nanostructure is its length in the vertical direction (perpendicular to a plane parallel to the capacitor layer), and the “maximum width” is the greatest lateral extension (in a plane parallel to the capacitor layer) of the nanostructure. For a trench type capacitor in a prior art device, the maximum width would be the length of the trench.
According to various embodiments, the electrically conductive vertical nanostructures in the capacitor layer may be grown nanostructures. The use of grown nanostructures allows extensive tailoring of the properties of the nanostructures. For instance, the growth conditions may be selected to achieve a morphology giving a large surface area of each nanostructure, which may in turn increase the charge storage capacity of the capacitors in the capacitor layer.
The nanostructures may, for example, be nanowires, nano-horns, nanotubes, nano-walls, crystalline nanostructures, or amorphous nanostructures.
According to various embodiments, the nanostructures may advantageously be carbon nanostructures, such as carbon nanofibers, carbon nanotubes or carbide-derived carbon nanostructures.
According to embodiments, each capacitor in the plurality of capacitors may comprise a plurality of electrically conductive vertical nanostructures, each being electrically conductively connected to one of the respective first capacitor contact structure and the respective second capacitor contact structure, and conductively separated from the other one of the respective first capacitor contact structure and the respective second capacitor contact structure by the layer of the second dielectric material.
In various embodiments, the capacitor layer may comprise a plurality of capacitor layer bottom contact pads at a bottom of the capacitor layer; and each second capacitor contact structure in the plurality of second capacitor contact structures may constitute a respective capacitor layer bottom contact pad in the plurality of capacitor layer bottom contact pads.
In embodiments, the image sensor may additionally comprise a signal processing layer having: a plurality of signal processing layer contact pads, each being bonded to a respective capacitor layer bottom contact pad in the plurality of capacitor layer bottom contact pads; and signal processing circuitry coupled to the signal processing layer contact pads.
In embodiments, the image sensor may additionally comprise additional layers having: a plurality of contact pads, computing processor, memory, sensors, RF for wireless communications etc. each being coupled to the signal processing layer contact pads.
The image sensor according to embodiments of the present invention may be included in an electronic device further comprising processing circuitry coupled to the image sensor, for performing operations on image data acquired from the image sensor.
In embodiments according to the present invention, the different layers may be bonded utilizing any standard bonding techniques known in the art, e.g. die bonding, hybrid bonding, metal to metal bonding, wafer level bonding, wafer to wafer or die to die or die to wafer level bonding etc. without deviating from the scope of the present invention.
According to a second aspect of the present invention, there is provided a method of manufacturing a capacitor layer for an image sensor, comprising the steps of: providing a substrate having a first plurality of discrete conductive material islands thereon; providing, on each discrete conductive material island in the first plurality of discrete conductive material islands, at least one electrically conductive nanostructure in such a way that the electrically conductive nanostructure extends substantially vertically from the discrete conductive material island and a first end of the electrically conductive nanostructure is in electrically conductive contact with the discrete conductive material island; applying a conformal dielectric layer on the electrically conductive nanostructures provided on the discrete conductive material islands; applying a conductive material layer on the conformal dielectric layer, to form a plurality of capacitors, each including at least one electrically conductive nanostructure, the conformal dielectric layer and the conductive material layer; embedding the plurality of capacitors in a dielectric material; forming a second plurality of discrete conductive material islands, in such a way that each discrete conductive material island in the second plurality of discrete conductive material islands makes electrically conductive contact with the conductive material layer on the at least one electrically conductive nanostructure provided on a respective one of the discrete conductive material islands in the first plurality of discrete conductive material islands; and removing the substrate.
In summary, the present invention thus relates to an image sensor comprising an image sensor layer having a plurality of image sensor layer contact pads; and a plurality of photo-sensitive elements, each being coupled to a respective image sensor layer contact pad; and a capacitor layer having: a plurality of first capacitor contact structures, each being constituted by a capacitor layer top contact pad bonded to a respective image sensor layer contact pad of the image sensor layer; a plurality of second capacitor contact structures; and a plurality of capacitors, embedded in a first dielectric material, each capacitor including at least one electrically conductive vertical nanostructure electrically conductively connected to one of a respective first capacitor contact structure and a respective second capacitor contact structure, and conductively separated from the other one of the respective first capacitor contact structure and the respective second capacitor contact structure by a layer of a second dielectric material.
These and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing example embodiments of the invention, wherein:
In the present detailed description, various embodiments of the image sensor according to the present invention are mainly described in the context of an exemplary electronic device, in the form of a mobile phone. It should be noted that the use of the image sensor according to embodiments of the invention is in no way limited to this kind of electronic device, but may be highly useful for other applications, such as industrial applications.
It should be understood that the image sensor according to various embodiments of the present invention may equally well be included in, and useful for, other types of electronic devices, such as, for example: an AR, VR, MR; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a smart watch; a wearable computing device; a digital camera; a CCD camera; a tablet; an ADAS; a server; a computer; a portable computer; a mobile computing device; a battery charger; a USB device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; an automobile; an electric vehicle; a vehicle component; avionics systems; a drone; and a multicopter.
With continued reference to
As is better seen in
To provide for reduced parasitic capacitances and/or a low degree of cross-talk (unwanted capacitive coupling) between neighboring pixels, the first dielectric material 25 may advantageously be a low-k dielectric, preferably a polymer. For a high capacitance density (and high capacitance) for each capacitor 23, the second dielectric in the layer 29 conformally coating the vertical nanostructures 27a-b may advantageously be a high-k dielectric.
To provide for the desired combination of a high resolution and good dynamic range for the image sensor 7, the capacitance density of each capacitor 23 may advantageously be at least 200 fF/μm2, where the relevant area is the foot-print area of the capacitor 23. For the example configuration in
As is schematically indicated in
Even though not explicitly shown in the
The capacitor layer 13 of the second embodiment of the image sensor 7 in
Each signal processing layer contact pad 35 of the signal processing layer 33 is bonded to a respective capacitor layer bottom contact pad 21 of the capacitor layer 13.
Although this is not explicitly shown in the figures, the image sensor 7 according to embodiments may include various additional structures, such as microlenses, color filters, thin-film photo detectors (TFPD), etc, in manners well-known to those skilled in the art of image sensors.
Referring to
The first end 39 of each nanostructure 27a-c is electrically conductively connected to the second capacitor contact structure 21, and the first capacitor structure 19 is arranged adjacent to the second end 41 of each nanostructure 27a-c.
Turning now to
Each even-numbered electrode layer (the second electrode layer 51) in the layered stack 47 is electrically conductively connected to the second capacitor contact structure 21, and each odd-numbered electrode layer (the first electrode layer 43 and the third electrode layer 45) in the layered stack 47 is electrically conductively connected to any other odd-numbered electrode layer in the layered stack (to each other), and thus also to the first capacitor contact structure/capacitor layer top contact pad 19. In the example configuration of
In a first step 100, a substrate is provided. The substrate, which may for example be a glass, silicon, or plastic substrate or any other substrate used and known by the industry, has a first plurality of discrete conductive material islands provided thereon. Between the substrate and the discrete conductive material islands, there may be a so-called sacrificial layer. The discrete conductive material islands, which may advantageously be metal islands, may constitute the second capacitor contact structure 21 in
In the subsequent step 101, at least one electrically conductive nanostructure 27a-c is provided in such a way that the at least one nanostructure 27a-c extends substantially vertically from the discrete conductive material island 21 and a first end 39 of the electrically conductive nanostructure 27a-c is in electrically conductive contact with the discrete conductive material island 21. Advantageously, the at least one nanostructure may be grown from each discrete conductive material island 21, using, per se, known techniques for growing vertical nanostructures.
Thereafter, in step 102, the vertical nanostructures 27a-c, and the portions of the conductive material island 21 left uncovered by the nanostructures 27a-c, may be conformally coated by a layer 29 of a second dielectric material. As was explained further above, the dielectric material of the conformal layer 29 may advantageously be made of a so-called high-k dielectric. The high k-dielectric materials may e.g. be HfOx, TiOx, TaOx, STO, Barium titanate, PZT, or other well-known high k dielectrics. Alternatively, the dielectric can be polymer based e.g. polypropylene, polystyrene, poly(p-xylylene), parylene etc.. Other well-known dielectric materials, such as SiOx or SiNx, etc may also be used as the dielectric layer 29. This dielectric layer 29 may be deposited using any known method suitable for making conformal layers, such as for example via vapor deposition, thermal processes, atomic layer deposition (ALD), etc. In various embodiments it may be advantageous to use more than one dielectric layer or dissimilar dielectric materials with different dielectric constant or different thicknesses of dielectric materials to control the effective dielectric constant or influence the breakdown voltage or the combination of them to control the dielectric film properties.
Advantageously, the dielectric material layer 29 is coated uniformly with atomic uniformity over the nanostructures 27a-c such that the dielectric layer covers the entirety of the nanostructures 27a-c so that the leakage current of the capacitor 23 is minimized. Another advantage of providing the conformal dielectric layer 29 with atomic uniformity is that such a layer 29 can conform to the surface irregularities of the conductive nanostructures 27a-c, which may be introduced during growth of the nanostructures. This provides for an increased total electrode surface area of the capacitor 23, which in turn provides for a higher capacitance density.
In the next step 103, a first conductive material layer 43, or the layered stack 47 in
On top of the first conductive material layer 43, a second conductive material layer 45 is formed in step 104. This second conductive material layer 45 may, for example, include a so-called seed metal layer conformally coated on the first conductive material layer 43. Such a seed metal layer may, for example, be made of Al, Cu or any other suitable seed metal materials. When such a seed metal layer is used, additional metal may be deposited using, for example, a chemical method such as electroplating, electroless plating or any other method known in the art. As is schematically indicated in
In the subsequent step 105, the capacitors 23 are embedded in a dielectric material 25. This dielectric material 25 may, as was mentioned further above, advantageously be a low-k dielectric. For example, suitable spin-on polymers, such as polyimide or BCB or spin on glass, or SiOx or SiNx may be used.
Thereafter, in step 106, the dielectric material 25 embedding the capacitors 23 is planarized at least until the second conductive material layer is exposed, to thereby form the first capacitor contact structures/capacitor layer top contact pads 19. Any suitable plasma treatment, dry chemistry, wet chemistry, or other planarization method, such as CMP, known in the art can be used for planarization.
Finally, in step 107, the substrate is removed, for example by selectively removing the sacrificial layer when such a layer is present on the substrate or polishing the substrate if needed when such sacrificial layer is not present.
Referring to
Steps 200 to 206 of the method according to the second embodiment substantially correspond to steps 100 to 106, respectively, according to the first embodiment described above with reference to
In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2050737-2 | Jun 2020 | SE | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/SE2021/050582 | 6/15/2021 | WO |
