Patent Application
20050176237
The invention relates generally to semiconductor integrated circuit manufacturing and, more particularly, to in-situ liner formation during reactive ion etching (“RIE”).
As wafer fabrication design rules reduce to 0.15 μm linewidths and below, the increased packing density of devices on a chip permits more electrical signal speed from device to device. This density leads to improved chip performance. However, this improved chip performance is only possible if the interconnect system between the devices is optimized. Narrower linewidths lead to increased line resistance. Tightly spaced conductor lines with a dielectric material between them act as capacitors, leading to a degradation in performance from an increased resistance (“R”) and capacitance (“C”). If either or both of these parameters are reduced, then the signal delay reduces, leading to increased chip performance. One method for reducing interconnect resistance is to increase the conductor cross section. However, this contradicts the goal of increased packing density since wider conductors will require more space. Additionally, smaller integrated circuit (“IC”) feature sizes are not achievable with larger linewidths. This has lead the semiconductor industry to search for alternative materials and processes.
Conventionally, aluminum (“Al”) has been used by the semiconductor industry as an interconnect material. Recently, copper (“Cu”) has been introduced as an interconnect material. The use of copper metallization provides improved performance and reliability over aluminum. Copper can lower the interconnect resistance, lowering R and the overall signal delay. Additionally, copper enables the creation of smaller linewidths with the ability to carry the same amount of current as large linewidths, permitting a tighter packing density on each metal level The optimum improvement to RC signal delay is gained when R is reduced and C is lowered by using a low-k dielectric, along with thinner barrier metals.
However, semiconductor processing with copper metallurgy can be complicated, for a number of reasons. One, copper diffuses quickly into oxides and silicon. Therefore, copper must be isolated from the surrounding inter-level dielectric (“ILD”). If the copper reaches the silicon substrate, it will significantly degrade device performance. Additionally, copper cannot be easily patterned using regular plasma etching techniques. Copper dry etching does not produce a necessary volatile by-product during the chemical reaction as required for economical dry etching. Furthermore, copper oxidizes quickly in air at low temperatures (i.e., <200° C.) and does not form a protective layer to stop further oxidation. Therefore, to form copper interconnect wiring, damascene processing has been introduced. Damascene processing eliminates the need to etch copper because a dielectric etch is used to define the critical line width and spacing, rather than the metal etch used with aluminum.
In a damascene process, both the vias and lines for each metal layer are created by etching holes and trenches in the ILD, depositing copper in the etched features and using CMP to remove excess copper. Damascene processing may include trench-first, via-first, and self-aligned etching.
During the RIE step 135, the sputter rate associated with the metal hardmask is finite but non-zero. In a dielectric etch chamber, sputter products from the metal hardmask can be expected to be involatile and will therefore stick to most surfaces. So, when the metal hardmask is exposed to the plasma during the RIE process, some redeposition of sputtered metallic products from the metal hardmask can be expected to occur inside the partially etched feature.
After RIE, in step 140, a diffusion layer of barrier metal (e.g., tantalum and tantalum nitride) is deposited on the bottom and sidewalls of the trenches and vias. If the aforementioned sputtering and redeposition of the metal hardmask occurs during RIE, then it is typically necessary to remove the redeposition products from the etched feature (e.g., from the sidewalls and/or bottom of a trench) before the barrier deposition 140. A copper seed layer is deposited onto the barrier metal in step 145. Copper is then used to fill both the vias and trenches in step 150. Finally, in step 155, excess copper is removed through surface planarization, such as CMP. The resulting surface is a planar structure with copper inlays forming the circuitry in the dielectric.
Because copper has high diffusity in silicon and silicon dioxide, which can destroy device performance, the aforementioned layer of barrier metal can be critical for copper metallurgy. Copper typically requires complete encapsulation by a thin-film barrier layer that functions as an adhesion promoter and as an effective diffusion barrier. For copper interconnect metallurgy, tantalum (“Ta”), tantalum nitride (“TaN”), and tantalum silicon nitride (“TaSiN”) have been implemented as barrier metals. Heretofore, barrier metals have been deposited in a separate chamber as a separate processing step (Step 140,
It is therefore desirable to provide a solution that reduces the possibility of damage to low-k dielectrics caused by exposure to air during damascene processing. Exemplary embodiments of the present invention exploit metal hardmask sputtering redeposition that occurs during RIE, thereby to produce the desired barrier layer during RIE while also avoiding air break exposure of the low-k dielectric.
The above and further advantages of the invention may be better understood by referring to the following description in conjunction with the accompanying drawings in which corresponding numerals in the different figures refer to the corresponding parts, in which:
The present invention can reduce the possibility of damage to the low-k dielectrics caused by exposure to air during processing, such as (single or dual) damascene processing. Exemplary embodiments of the present invention can provide this by incorporating the deposition of a barrier layer into an RIE step. As used hereinbelow, the term metal liner or metallic liner refers to a liner that contains, but need not consist exclusively of, metal.
Exemplary embodiments of the present invention modify RIE parameters to form a metallic liner (or barrier layer) during the RIE step of damascene processing (i.e., in-situ) rather than applying the metallic liner as a separate processing step.
As mentioned above, during conventional RIE at 135 in
An exemplary in-situ liner process in accordance with exemplary embodiments of the present invention can include a metal hardmask, for example TaN, as the liner target. In some exemplary embodiments, the addition of a fluorocarbon gas, such as CF4, in the RIE process can trigger changes to the liner. The pairing of TaN and CF4 can result in the deposition of a Ta-containing liner along feature sidewalls. By controlling discharge parameters, it is possible to control the sidewall angle of the RIE profile and, thus, the liner angle.
In some exemplary embodiments, the etch process illustrated in
In addition to the exemplary advantages described above, by eliminating the need for a separate liner deposition step after etching, in-situ liner deposition reduces turn around time, cost, and other related factors in semiconductor integrated circuit manufacturing.
Although exemplary embodiments of the invention are described above in detail, this does not limit the scope of the invention, which can be practiced in a variety of embodiments. For example, although specific examples of etching an organic dielectric are described above, workers in the art will recognize that the invention is applicable to either organic or inorganic dielectrics, whether dense or porous. Also, although a TEL SCCM etch tool is specified in some examples above, workers in the art will recognize that other etch tools, for example a LAM HPT etch tool, can be used to practice the invention.
