In-situ monitoring and method to determine accumulated printed wiring board thermal and/or vibration stress fatigue using a mirrored monitor chip and continuity circuit

Abstract

A monitoring system includes a monitor chip or chips soldered to a printed wiring board. By mirroring a function IC chip interface with the monitor chip, the consumed and remaining thermal/and or vibration-fatigue life of the function IC chip based on the life-environment actually experienced through monitoring of the monitor chip is readily determined. The monitor chip includes monitoring interconnections and/or circuitry which determines the number and/or location of failed-open solder terminations of the monitor chip.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The various features and advantages of this invention will become apparent to those skilled in the art from the following detailed description of the currently preferred embodiment. The drawings that accompany the detailed description can be briefly described as follows:

FIG. 1 is a general perspective view of exemplary electronic integrated circuits mounted to a printed wiring board using surface mount solder terminations.

FIG. 2 is a termination layout diagram of the solder terminations of these exemplary components.

FIG. 3 is a exemplary diagram showing interconnections between particular solder termination points on the underside of the electronic component with internal signal paths within the devices.

FIG. 4 is a block diagram of showing the co-placement of a functional integrated circuit and a monitoring integrated circuit package.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 illustrates an electronic package 10 having a function IC chip 12 which is wire bonded to a lead frame/package 14 with a number of wires 18. The function IC chip 12 and wires 18 are preferably encapsulated in an encapsulation material 35. The function IC chip 12 as utilized herein may be any semiconductor chip which performs any desired function. Shown here as an example package types are Ball Grid Arrays (BGA). Ball Grid Arrays (BGA) are widely used to electrically and mechanically connect substrate (typically ceramic) carrying semiconductor chips to a card. The BGA attachment method commonly consists of an array of metal pads which are soldered to connecting pads on both the Printed Wiring Board (PWB).

The wires 18 are routed through the BGA package 14 to terminals, or pads 16, on the opposite surface of the BGA package 14. Similar to the flip-chip process, the pads 16 form a pad pattern 20 (FIG. 2) that serves as interconnects between the integrated circuit chip 12 and its corresponding conductor pattern 22 on a printed circuit board 27.

One pad pattern 20 (FIG. 2) and a complimentary PWB conductor pattern 22 having circuit traces 24 (FIG. 3) for a ball grid array package of the function IC chip 12 is illustrated. It should be understood, however, that any pattern will likewise be usable with the present invention. The pad pattern 20 on the surface of the board 14, conductor pattern 22 on the surface of the PWB 27 to which the BGA 14 is to be soldered, and soldering of the BGA 14 to the conductor pattern 22 requires significant precision. As with the flip chip process, the size and composition of the conductor pattern 22 is closely controlled to achieve the required reliability, bond integrity and electrical characteristics, while concurrently eliminating the potential for electrical shorting between the pad pattern 20, the conductor pad pattern 22, and adjacent conductor traces 24.

A monitor chip 34 proximate the function IC chip 12 is wire bonded to a BGA 14′ with a number of wires 26 which mirror the wires 18 through a monitor pad pattern 28 having a multitude of pads 16′ which mirrors pad pattern 20 (FIG. 2). Likewise, a complimentary substrate conductor pattern 30 having circuit traces 32 which mirror conductor pattern 22 and circuit traces 24. By mirroring the function IC chip 12 substrate interface with the monitor chip 34 substrate interface, the thermal and/or vibration-fatigue life of the IC chip 12 based on the life-environment actually experienced through monitoring of the monitor chip 34 is readily determined. Preferably, the function IC chip 12 and monitor chip 34 are located proximate each other on the PWB 27 such that the thermal and/or vibration-fatigue experienced thereby is essentially identical. That is, the monitor chip 34, having the same solder termination substrate interface as the function IC chip 12, experiences essentially the same thermal fatigue and/or mechanical vibration as the function IC chip 12 for the determination of total accumulated fatigue of the essentially identical solder terminations.

The monitor chip 34 includes monitoring or continuity circuits which determine the number and/or location of failed-open solder terminations of the solder termination PWB interface. The monitoring circuitry may contain daisy chain wiring, or other known circuitry that can be monitored with circuits internal or external of the monitor chip 34 to determine the percentage of total fatigue life experienced by the function IC chip. By utilizing the characteristic relationship of cycles and total stress to failure of the monitor chip 34 and function IC chip 24, the monitoring circuitry can determine the likely percentage of the design stress-to-failure that has likely occurred for the function IC chip 12 calculated, for example only, by Miner's rule of accumulated stress.

The large number of solder terminations using the monitor chip 34 facilitates calculation of the total accumulated fatigue using a large sample set of individual terminations which provides higher levels of accurate total fatigue estimation through large sample sizes than individual accumulated stress types of in-situ sensors.

Furthermore, the monitoring chip 34 monitoring circuit may be configured to be less durable than the function IC chip 12. That is, under-fill material or application characteristics may be modified to produce know-cycle-to-failure conditions for ball grid arrays that are less durable than that of the function IC chip 12. Other characteristics such as “glob top” or other encapsulation materials 35′ (FIG. 1) or characteristics may be modified to produce the desired distributions of failed device-mounting terminations for measurements of the accumulated stress.

While the invention has been described above with reference to its use for the ball grid array package, the teachings of this invention is equally suited for use with flip chips or any other packaging method for electronics, as noted above.

It should be understood that although a particular component arrangement is disclosed in the illustrated embodiment, other arrangements will benefit from the instant invention.

Although particular step sequences are shown, described, and claimed, it should be understood that steps may be performed in any order, separated or combined unless otherwise indicated and will still benefit from the present invention.

The foregoing description is exemplary rather than defined by the limitations within. Many modifications and variations of the present invention are possible in light of the above teachings. The preferred embodiments of this invention have been disclosed, however, one of ordinary skill in the art would recognize that certain modifications would come within the scope of this invention. It is, therefore, to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described. For that reason the following claims should be studied to determine the true scope and content of this invention.

Claims

1. An electronic component comprising: a printed circuit board;a function IC chip having a function IC chip solder termination pattern between said function IC chip and said printed circuit board; anda monitor chip having a monitor chip solder termination pattern between said monitor chip and said printed circuit board, said monitor chip solder termination pattern representative of said function IC chip solder termination pattern to determine an accumulated vibration stress fatigue experienced by said function IC chip.

2. The component as recited in claim 1, wherein said monitor chip solder termination pattern is identical to said function IC chip solder termination pattern.

3. The component as recited in claim 1, wherein said monitor chip includes monitoring circuitry which determines the number of failed-open solder terminations.

4. The component as recited in claim 1, wherein said vibration stress fatigue includes thermal fatigue.

5. A method of determining a thermal and/or vibration-fatigue life experienced by a printed circuit board comprising the steps of: (A) representing a function IC chip solder termination pattern of a function IC chip with a monitor chip solder termination pattern of a monitor chip; and(B) determining a number of monitor chip solder terminations within the monitor chip solder termination pattern that have failed and are electrically open.

6. A method as recited in claim 5, further comprising the step of: (C) determining a percentage of the electrically open monitor chip solder terminations to determine an accumulated vibration stress fatigue.

7. A method as recited in claim 5, wherein said step (A) further comprises: (a) configuring the monitor chip to be less durable than the function IC chip; and(b) selecting a monitor chip packaging type to be less durable than the function IC chip.

8. A method as recited in claim 5, wherein said step (B) further comprises: (a) monitoring the monitor chip through an internal monitoring circuit.

9. A method as recited in claim 5, wherein said step (B) further comprises: (a) monitoring the monitor chip through an external monitoring circuit.

10. A method as recited in claim 5, wherein said step (A) further comprises: (a) identically mirroring the function IC chip solder termination pattern of the function IC chip with the monitor chip solder termination pattern of the monitor chip