Patent Application
20240045684
State of the art AI uses different 32-bit and 16-bit floating point formats such as, for example, Brain floating point 16 (also known as, for example, Bloat16 or BF16), Institute of Electrical and Electronics Engineers (IEEE) half-precision floating point (also known as, for example, FP16 or float16) and single-precision floating point (also known as, for example, FP32 or float32).
Various embodiments in accordance with the present disclosure will be described with reference to the drawings, in which:
The present disclosure relates to methods, apparatus, systems, and non-transitory computer-readable storage media for converting FP16 to an 8-bit floating point (FP8) using a single instruction.
In contrast to the IEEE 754-standardized 16-bit (FP16) variant, BF16 does not compromise on range when being compared to FP32. FP32 numbers have 8 bits of exponent and 24 bits of mantissa (including the one implicit). BF16 cuts 16 bits from the 24-bit FP32 mantissa to create a 16-bit floating point datatype. In contrast FP16, roughly halves the FP32 mantissa to 10 explicit bits and reduces the exponent to 5 bits to fit the 16-bit datatype envelope.
Although BF16 offers less precision than FP16, it is typically better suited to support deep learning tasks. FP16's range is not enough to accomplish deep learning training out-of-the-box due to its limited range. BF16 does not suffer from this issue and the limited precision may actually help to generalize the learned weights in the neural net training task. In other words, lower precision can be seen as offering a built-in regularization property.
In some examples, an 8-bit floating point format (FP8) provides some advantages over a larger floating point format. For example, an 8-bit floating point format may reduce pressure on memory and bandwidth used for machine learning (such as weights, activations, and gradient values used for training and/or inference of neural networks). As shown, the IEEE and BF16 formats have a fixed number of bits allocated to the fraction (or mantissa which is the fraction bits+1 bit) and exponent fields. Additionally, in some examples, a fixed exponent bias may be provided for a FP16 or BF16 number. As eight bits allows for a small number of mantissa and exponent bits than FP16 or BF16 it may be advantageous to have some variance in FP8 formats (e.g., ensure high accuracy and convergence when training machine learning models).
In machine learning, different parameters, namely weights, gradients and activations, have different precision and range requirements to achieve high training accuracy and/or convergence. This allows for different allocations of the number of exponent and fraction (mantissa bits) depending on the parameter being represented.
An example FP8 format is shown in 107. In some examples, this is called a bfloat8-bit floating point (BF8) format. As shown, this format uses 1 bit for a sign, 5 bits for the exponent, and 2 bits for the fraction (or 1+2 bits for the mantissa). An example FP8 format is shown in 109. In some examples, this is called a hybrid8-bit floating point (HF8) format. As shown, this format uses 1 bit for a sign, 4 bits for the exponent, and 3 bits for the fraction (or 1+3 bits for the mantissa).
Normalized numbers, subnormal (denormal) numbers, and zeroes are supported in both FP8 formats. In some examples, infinity and not-a-number (NaN) encodings are not supported, however, in some examples one or more are. In examples where infinities are not supported, a maximum exponent value is not reserved for encoding NaN and +/−infinity and just used to represent normalized floating-point numbers.
In examples where infinities and NaN are supported, the are mapped to 0x80. In some examples, for a NaN on an overflow, the value may be upconverted to IEEE754 NaN. In some examples, infinities and NaN raise exceptions for a hardware status register to delineate NaN from overflow.
In some examples, a zero is represented by an encoding with all zeroes the exponent and the fraction. Encodings with an all zero exponent and non-zero fraction represent denormal numbers. In the HF8 format, an exponent=00002 and mantissa=0002 represents numerical value of zero, while exponent=00002 and mantissa=0012, 0102, 0112, 1002, 1012, 1102, and 1112 represent the denormal numbers. Similarly, in the BF8 format an exponent=000002 and mantissa=002 represents numerical value of zero, while exponent=000002 and mantissa=012, 102, and 112 represent the denormal numbers.
In some examples, the FP8 formats utilize a variable exponential bias (e.g., a 6-bit unsigned integer value used as a bias). A bias skews the range of representable values more on the smaller numeric values at the expense of larger numerical values. In these examples, a numerical value of a normalized floating point number is (1)sign×2exponent-bias×1. mantissa and the numerical value of a denormal floating point number is (1)sign×2exponent-bias×0. mantissa. In some examples, the bias is provided by one or more packed data registers (e.g., SIMD or vector) where each data element position of the one or more packed data registers is to provides a bias value for a corresponding data element position of a source and/or destination. In some examples, the bias is provided by one or more general purpose registers where each general purpose register provides a bias to be used for each data element of a particular source and/or destination. Note that in some examples, a single general purpose register is used for a plurality of sources and/or destination. In some examples, the maximum bias is 16 for BF8 and 8 for HF8.
In some examples, not-a-number (NANs) and infinities are defined similarly to other IEEE floating points format, using an all-ones exponents. However, it is also acceptable in some examples to define versions of instructions that support other formats where “negative zero” is used to denote NANs and infinities, and the all-ones exponent is used to encode normal floating point numbers.
In some examples, hardware support for FP8 supports one or more status (condition code) flags: invalid, denormal, overflow, and underflow. An arithmetic operation with a denormal operand will set the denormal exception flag, while an arithmetic operation with any NaN operand or no useful definable result will set the invalid exception flag. An arithmetic operation with a result that that overflows or underflows a destination will set the overflow and underflow exception flags respectively in some examples.
Recent work has also shown that 8-bit float point formats, such as BF8 (using a 1-5-2 format (1-bit sign, 5-bit exponent, and 2-bit fraction or a 1-4-3 format), are a viable option for input data for mixed precision computation such as fused multiply-add (FMA) with BF8 inputs and a FP32 accumulator. To prepare higher-precision outputs to be used as the next operation's inputs, in some embodiments, those outputs need to be converted/rounded to FP8 numbers. Using 8-bit floating-point format instead of single-precision in at least some matrix operations is expected to alleviate memory utilization and bandwidth issues while providing a non-trivial performance upside (e.g., on the order of 2×) even during the compute operation. Additionally, numerical accuracy studies have shown that the precision of the Deep Learning application is not compromised. However, extensive workload studies have shown, that from time to time its required to avoid classic round-to-nearest behavior during these down converts. Instead, a stochastic rounding operation is needed. Examples herein relate to conversion using a provided bias term, including variable in-place, 2nd source merging and/or saturating.
Current experiments show bandwidth issues on the various cache levels and DRAM. So, as matrix compute capabilities speed up significantly (2×), the memory sub-systems capabilities only increase modestly due to reduce memory footprint. However, it has been found important to achieve convergence that FMAs accumulate into single-precision, IEEE float32. That means it may be important down-convert a result to FP8 after the operation completes.
In some examples, BF8-based operations support round to nearest even (RNE) and stochastic rounding. In some examples, HF8-based operations support round to nearest even (RNE) and stochastic rounding. In some examples, hybrid operations using both HF8 and BF8 are supported.
Some processors offer float16 compute and int8/int16 compute stacks. To convert a number from IEEE float16 to FP8 requires the detour via various int8/int8 instructions as the bias term can be implemented this way, however its execution is very slow.
That means in an end-to-end BF8 or HF8 flow for deep learning a downconvert from IEEE float16 to BF8 or HF8 may be needed and also, for gaining even better performance, to add the downconvert from IEEE float32 to BF8 or HF8. This has even a bigger impact as in practice with an at least twice as fast BF8/HF8 matrix multiplication unit than using IEEE FP32/float16/bfloat16.
There are no previously proposed instructions for performing a convert from FP16 or FP32 to BF8/HF8 using biased rounding with a per-element bias. So, building a conversion infrastructure capable of converting between these data formats is expected to help to balance compute and speed-up execution.
Embodiments detailed herein describe instructions and instructional support for performing this conversion/rounding using a bias term for rounding. In particular, a FP16 or FP32 value is converted/rounded to a FP8 value. In particular, embodiments of at least one instruction to convert from FP16 or FP32 to FP8 are detailed. One or more of these instructions, when executed, convert two vectors (up to 32 16-bit elements in a 512-bit register) to 8-bit FP8 using bias terms from a third vector. Hardware-assisted conversion may also afford the opportunity to “hide” the conversion infrastructure from software (SW) and the operating system (OS), for example, by performing arithmetic on a converted vector while converting the next vector. Further, the described instructions obviate the need for manual hands-on tuning by the users or administrators. Converting at a vector level is a reasonable extension of the existing architecture.
By computing the 64/32 bias terms through a software based LFSR (e.g., a vectorized xoroshiro128++) these pseudorandom numbers can then be used as bias terms to implement a stochastic rounding mechanism. The described instructions help to streamline software development and to improve execution speed as it handles in hardware: a) inf/nan and b) denormal handing when adding the bias term and afterwards downconverting the modified IEEE float16/FP32 number to BF8/HF8.
Execution of examples of some instructions is to cause a conversion, using a per-element biased rounding mechanism, of a plurality of packed FP16 values in two packed data source operands (e.g., a SIMD/packed data/vector registers or a memory location) having a plurality of FP16 data elements) using bias terms from a source/destination vector to a plurality of packed FP8 values and store those values in a packed data destination operand (e.g., a SIMD/packed data/vector register or memory location). In some embodiments, the instruction format utilizes a writemask or predicate, which is used to determine which data element positions of the destination are to be updated, zeroed, etc.
Execution of examples of some instructions is to cause a conversion, using a per-element biased rounding mechanism, of a plurality of packed FP32 values in two packed data source operands (e.g., a SIMD/packed data/vector registers or a memory location) having a plurality of FP32 data elements) using bias terms from a source/destination vector to a plurality of packed FP8 values and store those values in a packed data destination operand (e.g., a SIMD/packed data/vector register or memory location). In some embodiments, the instruction format utilizes a writemask or predicate, which is used to determine which data element positions of the destination are to be updated, zeroed, etc.
In some examples, a default definition for downconversion is compression toward the LSBs of the destination. However, similar instructions can support in-place convert in which the elements in the destination are not compressed and placed within the corresponding 16-bit/32-bit space of the source. This placement can also be variable (e.g., 4 options for FP16 as source and 2 options for FP32 as source) based on imm8 bits or a dedicated instructions.
In addition to the above, more similar instructions can be defined in which another source which was already converted using in-place method, is merged (logical OR) as part of the downconvert instruction.
As such, a processor or core implementing the instruction will execute according to the opcode of the instruction a conversion of each of the elements of the sources from FP16 to FP8 using bias terms from the source/destination and store each converted element into a corresponding data element position of the specified source/destination vector. Note that the two sources are treated as being one large source for the purposes of data element positions. For example, for 512-bit sources a first of the sources has data element positions 0-15 and the second of the sources has data element positions 16-31 with respect to the source/destination. In some embodiments, the conversion is to include truncation and rounding, as necessary.
In some embodiments, the FP16 to BF8 conversion instruction has a mnemonic of VCVTBIAS2PH2BF8 where VCVT indicates a convert, BIAS indicates using bias terms, 2PH indicates two packed FP16 sources, 2 indicates “to”, and BF8 indicates the 1-5-2 version of FP8. An embodiment of a format for the FP16 to BF8 conversion instruction is VCVTBIAS2PH2BF8 SRCDST, SRC1, SR2. In some embodiments, VCVTBIAS2PH2BF8 is the opcode mnemonic of the instruction. SRCDST indicates a packed data source/destination operand location and SRC1 and SRC2 indicate packed data source operand locations. Example operand sizes include, but are not limited to 64-bit, 128-bit, 256-bit, 512-bit, and 1024-bit. For example, SRC1, SRC2, and SRCDST may be 512-bit registers, where the SRC1 and SRC2 are to store 32 FP16 elements and the SRCDST has storage for 64 BF8 elements (after conversion) and 64 bias terms (to use during conversion). A benefit of VCVTBIAS2PH2BF8 is that the register space and cache ports are used efficiently as to max out their corresponding widths in some embodiments. Note that writemasking may also be used in some examples.
In some examples, SRCDST is a field for the destination operand identifier, such as packed data register or memory. SRC1 is one or more fields for the source operands identifier, such as a packed data register and/or memory. In some examples, the opcode is provided by at least field 1603, SRCDST field is provided by field 1744, the first source is provided by bits VVVV of one of 2005, BPJ17, or 2117, or provided by at least 1746. In some examples, the opcode is provided by at least field 1603, SRCDST field is provided by at least field 1744, the first source is provided by bits VVVV of one of 2005, BPJ17, or 2117, or the source is a memory location provided by at least 1746 and/or the SIB byte 1704
In some embodiments, the FP16 to HF8 conversion instruction has a mnemonic of VCVTBIAS2PH2HF8 where VCVT indicates a convert, BIAS indicates using bias terms, 2PH indicates two packed FP16 sources, 2 indicates “to”, and HF8 indicates the 1-4-3 version of FP8. An embodiment of a format for the FP16 to BF8 conversion instruction is VCVTBIAS2PH2HF8 SRCDST, SRC1, SR2. In some embodiments, VCVTBIAS2PH2HF8 is the opcode mnemonic of the instruction. SRCDST indicates a packed data source/destination operand location and SRC1 and SRC2 indicate packed data source operand locations. Example operand sizes include, but are not limited to 64-bit, 128-bit, 256-bit, 512-bit, and 1024-bit. For example, SRC1, SRC2, and SRCDST may be 512-bit registers, where the SRC1 and SRC2 are to store 32 FP16 elements and the SRCDST has storage for 64 HF8 elements (after conversion) and 64 bias terms (to use during conversion). A benefit of VCVTBIAS2PH2HF8 is that the register space and cache ports are used efficiently as to max out their corresponding widths in some embodiments. Note that writemasking may also be used in some examples.
In some embodiments, the FP32 to BF8 conversion instruction has a mnemonic of VCVTBIAS2PS2BF8 where VCVT indicates a convert, BIAS indicates using bias terms, 2PS indicates two packed FP32 sources, 2 indicates “to”, and BF8 indicates the 1-5-2 version of FP8. An embodiment of a format for the second FP32 to BF8 conversion instruction is VCVTBIAS2PS2BF8 SRCDST, SRC1, SR2. In some embodiments, VCVTBIAS2PS2BF8 is the opcode mnemonic of the instruction. SRCDST indicates a packed data source/destination operand location and SRC1 and SRC2 indicate packed data source operand locations. Example operand sizes include, but are not limited to 64-bit, 128-bit, 256-bit, 512-bit, and 1024-bit. For example, SRC1, SRC2, and SRCDST may be 512-bit registers, where the SRC1 and SRC2 are to store 16 FP32 elements and the SRCDST has storage for 64 BF8 elements (after conversion) and 64 bias terms (to use during conversion). A benefit of VCVTBIAS2PS2BF8 is that the register space and cache ports are used efficiently as to max out their corresponding widths in some embodiments. Note that writemasking may also be used in some examples.
In some examples, SRCDST is a field for the destination operand identifier, such as packed data register or memory. SRC1 is one or more fields for the source operands identifier, such as a packed data register and/or memory. In some examples, the opcode is provided by at least field 1603, SRCDST field is provided by field 1744, the first source is provided by bits VVVV of one of 2005, BPJ17, or 2117, or provided by at least 1746. In some examples, the opcode is provided by at least field 1603, SRCDST field is provided by at least field 1744, the first source is provided by bits VVVV of one of 2005, BPJ17, or 2117, or the source is a memory location provided by at least 1746 and/or the SIB byte 1704
In some embodiments, the FP32 to HF8 conversion instruction has a mnemonic of VCVTBIAS2PS2HF8 where VCVT indicates a convert, BIAS indicates using bias terms, 2PS indicates two packed FP32 sources, 2 indicates “to”, and HF8 indicates the 1-4-3 version of FPB. An embodiment of a format for the second FP32 to BF8 conversion instruction is VCVTBIAS2PHSHF8 SRCDST, SRC1, SR2. In some embodiments, VCVTBIAS2PS2HF8 is the opcode mnemonic of the instruction. SRCDST indicates a packed data source/destination operand location and SRC1 and SRC2 indicate packed data source operand locations. Example operand sizes include, but are not limited to 64-bit, 128-bit, 256-bit, 512-bit, and 1024-bit. For example, SRC1, SRC2, and SRCDST may be 512-bit registers, where the SRC1 and SRC2 are to store 16 FP32 elements and the SRCDST has storage for 64 HF8 elements (after conversion) and 64 bias terms (to use during conversion). A benefit of VCVTBIAS2PS2HF8 is that the register space and cache ports are used efficiently as to max out their corresponding widths in some embodiments. Note that writemasking may also be used in some examples.
In some examples, SRCDST is a field for the destination operand identifier, such as packed data register or memory. SRC1 is one or more fields for the source operands identifier, such as a packed data register and/or memory. In some examples, the opcode is provided by at least field 1603, SRCDST field is provided by field 1744, the first source is provided by bits VVVV of one of 2005, BPJ17, or 2117, or provided by at least 1746. In some examples, the opcode is provided by at least field 1603, SRCDST field is provided by at least field 1744, the first source is provided by bits VVVV of one of 2005, BPJ17, or 2117, or the source is a memory location provided by at least 1746 and/or the SIB byte 1704
In some embodiments, k1 indicates the use of writemasking/predication. One or more of the operands may be a memory location. In some embodiments, the destination is encoded using at least one or more fields for ModRM:reg(w), the first source is encoded using at least one more fields from a prefix (e.g., vvvv(r)), and the second source is encoded using at least one or more fields for ModRM:r/m(r).
A processor implementing the VCVTBIAS2PH2BF8/VCVTBIAS2PH2HF8/VCVTBIAS2PS2BF8/VCVTBIAS2PS2HF8 instructions may include: fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a source vector including 2N IEEE float16 or FP21 elements, and a destination vector including 2N BF8/HF8 floating-point format elements. In some examples, prior to the actual operation the destination vector is be loaded with 2N 8 bit bias terms as the destination register is treated as a source/destination register. As described, the opcode is to cause the processor to convert each of the elements of the source vector to the BF8/HF8 floating-point format, the conversion is to include bias addition, truncation and rounding and, as necessary, and to store each converted element into a corresponding location of the specified destination vector. The processor would also include decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode. Depending on the implementation the instruction may include masking features. Important to note is that the source datatype is twice as wide as the destination datatype. During the conversion denormals should be preserved and the biases are added to the lower bit values of the IEEE values before down converting.
As shown, each of the packed data sources 201 and 203 include N FP16 elements. Depending upon the implementation, the packed data source 1 201 and packed data source 2 203 are a packed data register (e.g., a XMM, YMM, ZMM, vector, SIMD, etc. register), or a memory location.
A pre-execution packed data source/destination 231(A) stores a plurality of packed biases (e.g., 8-bit bias terms). The packed data source 1 201, packed data source 2 203, and the pre-execution packed data source/destination 231(A) (acting as a source) are fed into execution circuitry 209 to be operated on. In particular, execution circuitry 209 performs the FP16 to FP8 conversion using FP16 to FP8 combinational logic 211. Details of embodiments of operations of that combinational logic 211 are described as flow diagrams later.
Post-execution packed data source/destination 231 stores the results of the conversions of the FP16 data elements of packed data sources 201 and 203 in corresponding positions of the packed data destination 231. For example, packed data source position 0 (far right) of packed data source 2 203 is stored in packed data destination position 0 (far right). While the most significant packed data element position of packed data source 1 201 is stored in the most significant packed data element position of the packed data destination 231.
The instruction 301 is received by decode circuitry 305. For example, the decode circuitry 305 receives this instruction from fetch logic/circuitry. The instruction includes fields for an opcode, first and second sources, and a destination. In some embodiments, the sources and destination are registers, and in other embodiments one or more are memory locations.
More detailed embodiments of at least one instruction format will be detailed later. The decode circuitry 305 decodes the instruction into one or more operations. In some embodiments, this decoding includes generating a plurality of micro-operations to be performed by execution circuitry (such as execution circuitry 309). The decode circuitry 305 also decodes instruction prefixes. In some embodiments, the decode circuitry 305 translates between instruction sets and then decodes the translated instruction(s).
In some embodiments, register renaming, register allocation, and/or scheduling circuitry 307 provides functionality for one or more of: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), 2) allocating status bits and flags to the decoded instruction, and 3) scheduling the decoded instruction for execution on execution circuitry out of an instruction pool (e.g., using a reservation station in some embodiments).
Registers (register file) and/or memory 308 store data as operands of the instruction to be operated on by execution circuitry 309. Example register types include packed data registers, general purpose registers, and floating-point registers.
Execution circuitry 309 executes the decoded instruction. Example detailed execution circuitry is shown in
In some embodiments, retirement/write back circuitry 311 architecturally commits the destination register into the registers or memory 308 and retires the instruction.
At 401, a single VCVTBIAS2PH2BF8/VCVTBIAS2PH2HF8/VCVTBIAS2PS2BF8/VCVTBIAS2PS2HF8instruction is fetched. The single VCVTBIAS2PH2BF8/VCVTBIAS2PH2HF8/VCVTBIAS2PS2BF8/VCVTBIAS2PS2HF8instruction includes one or more fields to identify two source operands (e.g., addressing field(s) 1605), one or more fields to identify a source/destination operand (e.g., addressing field(s) 1605), and one or more fields for an opcode (e.g., opcode 1602), the opcode to indicate that execution circuitry is to convert packed half-precision floating point data or single-precision floating point data (depending on the opcode or some other data element identifier) from the identified first and second sources to packed FP8 data using bias terms from the source/destination and store the packed FP8 data into corresponding data element positions of the identified source/destination. In some embodiments, the MOD R/M byte, vvvv of prefix and/or SIB byte provide, at least partially, the operand locations.
In some embodiments, the fetched instruction is translated into one or more instructions at 402. For example, the fetched instruction is translated into one or more instructions of a different instruction set architecture.
The fetched instruction (or translated one or more instructions) is/are decoded at 303. For example, the fetched VCVTBIAS2PH2BF8/VCVTBIAS2PH2HF8/VCVTBIAS2PS2BF8/VCVTBIAS2PS2HF8instruction is decoded by decode circuitry such as that detailed herein.
Data values associated with the source operands of the decoded instruction are retrieved at 405. For example, when one or more of the source operands are memory operands, the data from the indicated memory location is retrieved.
At 407, the decoded single instruction is executed, or the translated one or more instructions are executed, by execution circuitry (hardware) such as that detailed herein. For the VCVTBIAS2PH2BF8 or VCVTBIAS2PH2HF8 instruction, the execution will cause execution circuitry to convert packed half-precision floating point data or single-precision floating point data from the identified first and second sources to packed FP8 data using bias terms from the identified source/destination and store the packed FP8 data into corresponding data element positions of the identified source/destination.
In some embodiments, the instruction is committed or retired at 409.
A plurality of actions may be applicable to each data element of the second source and include one or more of 501-517. Note that the per element evaluation may be done serially or in parallel.
At 501 a determination of if a writemask applies. For example, was a writemask used? If so, was the corresponding bit position of the writemask or predicate set to allow a resulting conversion to be stored for the data element?
When the writemask applies, a determination of if the second source is memory and single element broadcasting enabled is made 503 in some embodiments. In some embodiments, bit 20 of 1601(C) is used for the broadcasting setting.
When those conditions are true, a temporary value (t) is set to be a value stored in the initial element position of the source at 505 in some embodiments. When those conditions are not true, a temporary value (t) is set to be a value stored in the element position of the source at 407. A conversion of the temporary value t from FP16 to BF8 using bias terms (as needed) from the source/destination is made at 509. The table below illustrates how t is converted according to some embodiments.
In some embodiments, a different function (“convert_to_fp16_bfloat8_RNO”) is used. The table below illustrates how t is converted according to some embodiments.
The converted value is stored into a corresponding byte location in the destination at 511. For example, source[1] is stored in destination[1].
If the writemask does not apply (e.g., not set), then a determination of if zeroing being used is made at 513. When zeroing is used, no changes are made to a value in a corresponding byte location of the destination at 517. When zeroing is not used (e.g., merge masking is used), a value in a corresponding byte location position of the destination is set to be zero at 515.
The first source is evaluated at 518 and this evaluation may include several actions. At 519 a determination of if a writemask applies. For example, was a writemask used? If so, was the corresponding bit position of the writemask or predicate set to allow a resulting conversion to be stored for the data element?
When the writemask applies, a temporary value (t) is set to be a value to be stored in the initial element position of the source at 520. A conversion of the temporary value t from FP16 to BF8 using bias terms (as needed) from the source/destination at 522.
The table below illustrates how t is converted according to some embodiments.
In some embodiments, a different function (“convert_to_fp16_bfloat8_RNO”) is used. The table below illustrates how t is converted according to some embodiments.
The converted value is stored into a corresponding byte location in the destination at 522. Note that this corresponding location needs to account for the storage from the second source. For example, source1[0] is stored in destination[N].
If the writemask does not apply (e.g., not set), then a determination of if is zeroing being used is made at 523. When zeroing is used, no changes are made to a value in a corresponding byte location of the destination at 525. When zeroing is not used (e.g., merge masking is used), a value in a corresponding byte location position of the destination is set to be zero at 527.
Other examples of pseudocode for the conversion from FP16 to FP8 are as follows:
As shown, each of the packed data sources 801 and 803 include N FP32 elements. Depending upon the implementation, the packed data source 1 801 and packed data source 2 803 are a packed data register (e.g., a XMM, YMM, ZMM, vector, SIMD, etc. register), or a memory location.
A pre-execution packed data source/destination 831(A) stores a plurality of packed biases (e.g., 8-bit bias terms). The packed data source 1 801, packed data source 2 803, and the pre-execution packed data source/destination 831(A) (acting as a source) are fed into execution circuitry 809 to be operated on. In particular, execution circuitry 809 performs the FP32 to FP8 conversion using FP32 to FP8 combinational logic 811. Details of embodiments of operations of that combinational logic 811 are described as flow diagrams later.
Post-execution packed data source/destination 831 stores the results of the conversions of the FP32 data elements of packed data sources 801 and 803 in corresponding positions of the packed data destination 831. For example, packed data source position 0 (far right) of packed data source 2 803 is stored in packed data destination position 0 (far right). While the most significant packed data element position of packed data source 1 801 is stored in the most significant packed data element position of the packed data destination 831.
Other examples of pseudocode for the conversion from FP32 to FP8 are as follows:
The instructions detailed above may be used in a variety of computer architectures and environments, utilize one or more instruction formats, etc. Examples of architectures, formats, etc. that support these instructions are detailed below.
Detailed below are descriptions of example computer architectures. Other system designs and configurations known in the arts for laptop, desktop, and handheld personal computers (PC)s, personal digital assistants, engineering workstations, servers, disaggregated servers, network devices, network hubs, switches, routers, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, micro controllers, cell phones, portable media players, hand-held devices, and various other electronic devices, are also suitable. In general, a variety of systems or electronic devices capable of incorporating a processor and/or other execution logic as disclosed herein are generally suitable.
Processors 1170 and 1180 are shown including integrated memory controller (IMC) circuitry 1172 and 1182, respectively. Processor 1170 also includes interface circuits 1176 and 1178; similarly, second processor 1180 includes interface circuits 1186 and 1188. Processors 1170, 1180 may exchange information via the interface 1150 using interface circuits 1178, 1188. IMCs 1172 and 1182 couple the processors 1170, 1180 to respective memories, namely a memory 1132 and a memory 1134, which may be portions of main memory locally attached to the respective processors.
Processors 1170, 1180 may each exchange information with a network interface (NW I/F) 1190 via individual interfaces 1152, 1154 using interface circuits 1176, 1194, 1186, 1198. The network interface 1190 (e.g., one or more of an interconnect, bus, and/or fabric, and in some examples is a chipset) may optionally exchange information with a coprocessor 1138 via an interface circuit 1192. In some examples, the coprocessor 1138 is a special-purpose processor, such as, for example, a high-throughput processor, a network or communication processor, compression engine, graphics processor, general purpose graphics processing unit (GPGPU), neural-network processing unit (NPU), embedded processor, or the like.
A shared cache (not shown) may be included in either processor 1170, 1180 or outside of both processors, yet connected with the processors via an interface such as P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.
Network interface 1190 may be coupled to a first interface 1116 via interface circuit 1196. In some examples, first interface 1116 may be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect or another I/O interconnect. In some examples, first interface 1116 is coupled to a power control unit (PCU) 1117, which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors 1170, 1180 and/or co-processor 1138. PCU 1117 provides control information to a voltage regulator (not shown) to cause the voltage regulator to generate the appropriate regulated voltage. PCU 1117 also provides control information to control the operating voltage generated. In various examples, PCU 1117 may include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).
PCU 1117 is illustrated as being present as logic separate from the processor 1170 and/or processor 1180. In other cases, PCU 1117 may execute on a given one or more of cores (not shown) of processor 1170 or 1180. In some cases, PCU 1117 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other examples, power management operations to be performed by PCU 1117 may be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, power management operations to be performed by PCU 1117 may be implemented within BIOS or other system software.
Various I/O devices 1114 may be coupled to first interface 1116, along with a bus bridge 1118 which couples first interface 1116 to a second interface 1120. In some examples, one or more additional processor(s) 1115, such as coprocessors, high throughput many integrated core (MIC) processors, GPGPUs, accelerators (such as graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interface 1116. In some examples, second interface 1120 may be a low pin count (LPC) interface. Various devices may be coupled to second interface 1120 including, for example, a keyboard and/or mouse 1122, communication devices 1127 and storage circuitry 1128. Storage circuitry 1128 may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device which may include instructions/code and data 1130 and may implement the storage 'ISAB03 in some examples. Further, an audio I/O 1124 may be coupled to second interface 1120. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor system 1100 may implement a multi-drop interface or other such architecture.
Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high-performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip (SoC) that may be included on the same die as the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Example core architectures are described next, followed by descriptions of example processors and computer architectures.
Thus, different implementations of the processor 1200 may include: 1) a CPU with the special purpose logic 1208 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores, not shown), and the cores 1202(A)-(N) being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor with the cores 1202(A)-(N) being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 1202(A)-(N) being a large number of general purpose in-order cores. Thus, the processor 1200 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 1200 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).
A memory hierarchy includes one or more levels of cache unit(s) circuitry 1204(A)-(N) within the cores 1202(A)-(N), a set of one or more shared cache unit(s) circuitry 1206, and external memory (not shown) coupled to the set of integrated memory controller unit(s) circuitry 1214. The set of one or more shared cache unit(s) circuitry 1206 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some examples interface network circuitry 1212 (e.g., a ring interconnect) interfaces the special purpose logic 1208 (e.g., integrated graphics logic), the set of shared cache unit(s) circuitry 1206, and the system agent unit circuitry 1210, alternative examples use any number of well-known techniques for interfacing such units. In some examples, coherency is maintained between one or more of the shared cache unit(s) circuitry 1206 and cores 1202(A)-(N). In some examples, interface controller units circuitry 1216 couple the cores 1202 to one or more other devices 1218 such as one or more I/O devices, storage, one or more communication devices (e.g., wireless networking, wired networking, etc.), etc.
In some examples, one or more of the cores 1202(A)-(N) are capable of multi-threading. The system agent unit circuitry 1210 includes those components coordinating and operating cores 1202(A)-(N). The system agent unit circuitry 1210 may include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores 1202(A)-(N) and/or the special purpose logic 1208 (e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.
The cores 1202(A)-(N) may be homogenous in terms of instruction set architecture (ISA). Alternatively, the cores 1202(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores 1202(A)-(N) may be capable of executing an ISA, while other cores may be capable of executing only a subset of that ISA or another ISA.
In
By way of example, the example register renaming, out-of-order issue/execution architecture core of
The front-end unit circuitry 1330 may include branch prediction circuitry 1332 coupled to instruction cache circuitry 1334, which is coupled to an instruction translation lookaside buffer (TLB) 1336, which is coupled to instruction fetch circuitry 1338, which is coupled to decode circuitry 1340. In one example, the instruction cache circuitry 1334 is included in the memory unit circuitry 1370 rather than the front-end circuitry 1330. The decode circuitry 1340 (or decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decode circuitry 1340 may further include address generation unit (AGU, not shown) circuitry. In one example, the AGU generates an LSU address using forwarded register ports, and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode circuitry 1340 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. In one example, the core 1390 includes a microcode ROM (not shown) or other medium that stores microcode for certain macroinstructions (e.g., in decode circuitry 1340 or otherwise within the front-end circuitry 1330). In one example, the decode circuitry 1340 includes a micro-operation (micro-op) or operation cache (not shown) to hold/cache decoded operations, micro-tags, or micro-operations generated during the decode or other stages of the processor pipeline 1300. The decode circuitry 1340 may be coupled to rename/allocator unit circuitry 1352 in the execution engine circuitry 1350.
The execution engine circuitry 1350 includes the rename/allocator unit circuitry 1352 coupled to retirement unit circuitry 1354 and a set of one or more scheduler(s) circuitry 1356. The scheduler(s) circuitry 1356 represents any number of different schedulers, including reservations stations, central instruction window, etc. In some examples, the scheduler(s) circuitry 1356 can include arithmetic logic unit (ALU) scheduler/scheduling circuitry, ALU queues, address generation unit (AGU) scheduler/scheduling circuitry, AGU queues, etc. The scheduler(s) circuitry 1356 is coupled to the physical register file(s) circuitry 1358. Each of the physical register file(s) circuitry 1358 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point, status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. In one example, the physical register file(s) circuitry 1358 includes vector registers unit circuitry, writemask registers unit circuitry, and scalar register unit circuitry. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, etc. The physical register file(s) circuitry 1358 is coupled to the retirement unit circuitry 1354 (also known as a retire queue or a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) (ROB(s)) and a retirement register file(s); using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.). The retirement unit circuitry 1354 and the physical register file(s) circuitry 1358 are coupled to the execution cluster(s) 1360. The execution cluster(s) 1360 includes a set of one or more execution unit(s) circuitry 1362 and a set of one or more memory access circuitry 1364. The execution unit(s) circuitry 1362 may perform various arithmetic, logic, floating-point or other types of operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar integer, scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point). While some examples may include a number of execution units or execution unit circuitry dedicated to specific functions or sets of functions, other examples may include only one execution unit circuitry or multiple execution units/execution unit circuitry that all perform all functions. The scheduler(s) circuitry 1356, physical register file(s) circuitry 1358, and execution cluster(s) 1360 are shown as being possibly plural because certain examples create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating-point/packed integer/packed floating-point/vector integer/vector floating-point pipeline, and/or a memory access pipeline that each have their own scheduler circuitry, physical register file(s) circuitry, and/or execution cluster—and in the case of a separate memory access pipeline, certain examples are implemented in which only the execution cluster of this pipeline has the memory access unit(s) circuitry 1364). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.
In some examples, the execution engine unit circuitry 1350 may perform load store unit (LSU) address/data pipelining to an Advanced Microcontroller Bus (AMB) interface (not shown), and address phase and writeback, data phase load, store, and branches.
The set of memory access circuitry 1364 is coupled to the memory unit circuitry 1370, which includes data TLB circuitry 1372 coupled to data cache circuitry 1374 coupled to level 2 (L2) cache circuitry 1376. In one example, the memory access circuitry 1364 may include load unit circuitry, store address unit circuitry, and store data unit circuitry, each of which is coupled to the data TLB circuitry 1372 in the memory unit circuitry 1370. The instruction cache circuitry 1334 is further coupled to the level 2 (L2) cache circuitry 1376 in the memory unit circuitry 1370. In one example, the instruction cache 1334 and the data cache 1374 are combined into a single instruction and data cache (not shown) in L2 cache circuitry 1376, level 3 (L3) cache circuitry (not shown), and/or main memory. The L2 cache circuitry 1376 is coupled to one or more other levels of cache and eventually to a main memory.
The core 1390 may support one or more instructions sets (e.g., the x86 instruction set architecture (optionally with some extensions that have been added with newer versions); the MIPS instruction set architecture; the ARM instruction set architecture (optionally with optional additional extensions such as NEON)), including the instruction(s) described herein. In one example, the core 1390 includes logic to support a packed data instruction set architecture extension (e.g., AVX1, AVX2), thereby allowing the operations used by many multimedia applications to be performed using packed data.
In some examples, the register architecture 1500 includes writemask/predicate registers 1515. For example, in some examples, there are 8 writemask/predicate registers (sometimes called k0 through k7) that are each 16-bit, 32-bit, 64-bit, or 128-bit in size. Writemask/predicate registers 1515 may allow for merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and/or zeroing (e.g., zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given writemask/predicate register 1515 corresponds to a data element position of the destination. In other examples, the writemask/predicate registers 1515 are scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits per 64-bit vector element).
The register architecture 1500 includes a plurality of general-purpose registers 1525. These registers may be 16-bit, 32-bit, 64-bit, etc. and can be used for scalar operations. In some examples, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.
In some examples, the register architecture 1500 includes scalar floating-point (FP) register file 1545 which is used for scalar floating-point operations on 32/64/80-bit floating-point data using the x87 instruction set architecture extension or as MMX registers to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.
One or more flag registers 1540 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, compare, and system operations. For example, the one or more flag registers 1540 may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, the one or more flag registers 1540 are called program status and control registers.
Segment registers 1520 contain segment points for use in accessing memory. In some examples, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.
Model specific registers or machine specific registers (MSRs) 1535 control and report on processor performance. Most MSRs 1535 handle system-related functions and are not accessible to an application program. For example, MSRs may provide control for one or more of: performance-monitoring counters, debug extensions, memory type range registers, thermal and power management, instruction-specific support, and/or processor feature/mode support. Machine check registers 1560 consist of control, status, and error reporting MSRs that are used to detect and report on hardware errors. Control register(s) 1555 (e.g., CR0-CR4) determine the operating mode of a processor (e.g., processor 1170, 1180, 1138, 1115, and/or 1200) and the characteristics of a currently executing task. In some examples, MSRs 1535 are a subset of control registers 1555.
One or more instruction pointer register(s) 1530 store an instruction pointer value. Debug registers 1550 control and allow for the monitoring of a processor or core's debugging operations.
Memory (mem) management registers 1565 specify the locations of data structures used in protected mode memory management. These registers may include a global descriptor table register (GDTR), interrupt descriptor table register (IDTR), task register, and a local descriptor table register (LDTR) register.
Alternative examples may use wider or narrower registers. Additionally, alternative examples may use more, less, or different register files and registers. The register architecture 1500 may, for example, be used in register file/memory 'ISAB08, or physical register file(s) circuitry 1358.
Instruction Set Architectures.
An instruction set architecture (ISA) may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, location of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) on which that operation is to be performed and/or other data field(s) (e.g., mask). Some instruction formats are further broken down through the definition of instruction templates (or sub-formats). For example, the instruction templates of a given instruction format may be defined to have different subsets of the instruction format's fields (the included fields are typically in the same order, but at least some have different bit positions because there are less fields included) and/or defined to have a given field interpreted differently. Thus, each instruction of an ISA is expressed using a given instruction format (and, if defined, in a given one of the instruction templates of that instruction format) and includes fields for specifying the operation and the operands. For example, an example ADD instruction has a specific opcode and an instruction format that includes an opcode field to specify that opcode and operand fields to select operands (source1/destination and source2); and an occurrence of this ADD instruction in an instruction stream will have specific contents in the operand fields that select specific operands. In addition, though the description below is made in the context of x86 ISA, it is within the knowledge of one skilled in the art to apply the teachings of the present disclosure in another ISA.
Examples of the instruction(s) described herein may be embodied in different formats. Additionally, example systems, architectures, and pipelines are detailed below. Examples of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.
The prefix(es) field(s) 1601, when used, modifies an instruction. In some examples, one or more prefixes are used to repeat string instructions (e.g., 0xF0, 0xF2, 0xF3, etc.), to provide section overrides (e.g., 0x2E, 0x36, 0x3E, 0x26, 0x64, 0x65, 0x2E, 0x3E, etc.), to perform bus lock operations, and/or to change operand (e.g., 0x66) and address sizes (e.g., 0x67). Certain instructions require a mandatory prefix (e.g., 0x66, 0xF2, 0xF3, etc.). Certain of these prefixes may be considered “legacy” prefixes. Other prefixes, one or more examples of which are detailed herein, indicate, and/or provide further capability, such as specifying particular registers, etc. The other prefixes typically follow the “legacy” prefixes.
The opcode field 1603 is used to at least partially define the operation to be performed upon a decoding of the instruction. In some examples, a primary opcode encoded in the opcode field 1603 is one, two, or three bytes in length. In other examples, a primary opcode can be a different length. An additional 3-bit opcode field is sometimes encoded in another field.
The addressing information field 1605 is used to address one or more operands of the instruction, such as a location in memory or one or more registers.
The content of the MOD field 1742 distinguishes between memory access and non-memory access modes. In some examples, when the MOD field 1742 has a binary value of 11 (11b), a register-direct addressing mode is utilized, and otherwise a register-indirect addressing mode is used.
The register field 1744 may encode either the destination register operand or a source register operand or may encode an opcode extension and not be used to encode any instruction operand. The content of register field 1744, directly or through address generation, specifies the locations of a source or destination operand (either in a register or in memory). In some examples, the register field 1744 is supplemented with an additional bit from a prefix (e.g., prefix 1601) to allow for greater addressing.
The R/M field 1746 may be used to encode an instruction operand that references a memory address or may be used to encode either the destination register operand or a source register operand. Note the R/M field 1746 may be combined with the MOD field 1742 to dictate an addressing mode in some examples.
The SIB byte 1704 includes a scale field 1752, an index field 1754, and a base field 1756 to be used in the generation of an address. The scale field 1752 indicates a scaling factor. The index field 1754 specifies an index register to use. In some examples, the index field 1754 is supplemented with an additional bit from a prefix (e.g., prefix 1601) to allow for greater addressing. The base field 1756 specifies a base register to use. In some examples, the base field 1756 is supplemented with an additional bit from a prefix (e.g., prefix 1601) to allow for greater addressing. In practice, the content of the scale field 1752 allows for the scaling of the content of the index field 1754 for memory address generation (e.g., for address generation that uses 2scale*index+base).
Some addressing forms utilize a displacement value to generate a memory address. For example, a memory address may be generated according to 2scale*index+base+displacement, index*scale+displacement, r/m+displacement, instruction pointer (RIP/EIP)+displacement, register+displacement, etc. The displacement may be a 1-byte, 2-byte, 4-byte, etc. value. In some examples, the displacement field 1607 provides this value. Additionally, in some examples, a displacement factor usage is encoded in the MOD field of the addressing information field 1605 that indicates a compressed displacement scheme for which a displacement value is calculated and stored in the displacement field 1607.
In some examples, the immediate value field 1609 specifies an immediate value for the instruction. An immediate value may be encoded as a 1-byte value, a 2-byte value, a 4-byte value, etc.
Instructions using the first prefix 1601(A) may specify up to three registers using 3-bit fields depending on the format: 1) using the reg field 1744 and the R/M field 1746 of the MOD R/M byte 1702; 2) using the MOD R/M byte 1702 with the SIB byte 1704 including using the reg field 1744 and the base field 1756 and index field 1754; or 3) using the register field of an opcode.
In the first prefix 1601(A), bit positions 7:4 are set as 0100. Bit position 3 (W) can be used to determine the operand size but may not solely determine operand width. As such, when W=0, the operand size is determined by a code segment descriptor (CS.D) and when W=1, the operand size is 64-bit.
Note that the addition of another bit allows for 16 (24) registers to be addressed, whereas the MOD R/M reg field 1744 and MOD R/M R/M field 1746 alone can each only address 8 registers.
In the first prefix 1601(A), bit position 2 (R) may be an extension of the MOD R/M reg field 1744 and may be used to modify the MOD R/M reg field 1744 when that field encodes a general-purpose register, a 64-bit packed data register (e.g., a SSE register), or a control or debug register. R is ignored when MOD R/M byte 1702 specifies other registers or defines an extended opcode.
Bit position 1 (X) may modify the SIB byte index field 1754.
Bit position 0 (B) may modify the base in the MOD R/M R/M field 1746 or the SIB byte base field 1756; or it may modify the opcode register field used for accessing general purpose registers (e.g., general purpose registers 1525).
In some examples, the second prefix 1601(B) comes in two forms—a two-byte form and a three-byte form. The two-byte second prefix 1601(B) is used mainly for 128-bit, scalar, and some 256-bit instructions; while the three-byte second prefix 1601(B) provides a compact replacement of the first prefix 1601(A) and 3-byte opcode instructions.
Instructions that use this prefix may use the MOD R/M R/M field 1746 to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.
Instructions that use this prefix may use the MOD R/M reg field 1744 to encode either the destination register operand or a source register operand, or to be treated as an opcode extension and not used to encode any instruction operand.
For instruction syntax that support four operands, vvvv, the MOD R/M R/M field 1746 and the MOD R/M reg field 1744 encode three of the four operands. Bits[7:4] of the immediate value field 1609 are then used to encode the third source register operand.
Bit[7] of byte 2 2017 is used similar to W of the first prefix 1601(A) including helping to determine promotable operand sizes. Bit[2] is used to dictate the length (L) of the vector (where a value of 0 is a scalar or 128-bit vector and a value of 1 is a 256-bit vector). Bits[1:0] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). Bits[6:3], shown as vvvv, may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.
Instructions that use this prefix may use the MOD R/M R/M field 1746 to encode the instruction operand that references a memory address or encode either the destination register operand or a source register operand.
Instructions that use this prefix may use the MOD R/M reg field 1744 to encode either the destination register operand or a source register operand, or to be treated as an opcode extension and not used to encode any instruction operand.
For instruction syntax that support four operands, vvvv, the MOD R/M R/M field 1746, and the MOD R/M reg field 1744 encode three of the four operands. Bits[7:4] of the immediate value field 1609 are then used to encode the third source register operand.
The third prefix 1601(C) can encode 32 vector registers (e.g., 128-bit, 256-bit, and 512-bit registers) in 64-bit mode. In some examples, instructions that utilize a writemask/opmask (see discussion of registers in a previous figure, such as
The third prefix 1601(C) may encode functionality that is specific to instruction classes (e.g., a packed instruction with “load+op” semantic can support embedded broadcast functionality, a floating-point instruction with rounding semantic can support static rounding functionality, a floating-point instruction with non-rounding arithmetic semantic can support “suppress all exceptions” functionality, etc.).
The first byte of the third prefix 1601(C) is a format field 2111 that has a value, in one example, of 62H. Subsequent bytes are referred to as payload bytes 2115-2119 and collectively form a 24-bit value of P[23:0] providing specific capability in the form of one or more fields (detailed herein).
In some examples, P[1:0] of payload byte 2119 are identical to the low two mm bits. P[3:2] are reserved in some examples. Bit P[4] (R′) allows access to the high 16 vector register set when combined with P[7] and the MOD R/M reg field 1744. P[6] can also provide access to a high 16 vector register when SIB-type addressing is not needed. P[7:5] consist of R, X, and B which are operand specifier modifier bits for vector register, general purpose register, memory addressing and allow access to the next set of 8 registers beyond the low 8 registers when combined with the MOD R/M register field 1744 and MOD R/M R/M field 1746. P[9:8] provide opcode extensionality equivalent to some legacy prefixes (e.g., 00=no prefix, 01=66H, 10=F3H, and 11=F2H). P[10] in some examples is a fixed value of 1. P[14:11], shown as vvvv, may be used to: 1) encode the first source register operand, specified in inverted (1s complement) form and valid for instructions with 2 or more source operands; 2) encode the destination register operand, specified in 1s complement form for certain vector shifts; or 3) not encode any operand, the field is reserved and should contain a certain value, such as 1111b.
P[15] is similar to W of the first prefix 1601(A) and second prefix 1611(B) and may serve as an opcode extension bit or operand size promotion.
P[18:16] specify the index of a register in the opmask (writemask) registers (e.g., writemask/predicate registers 1515). In one example, the specific value aaa=000 has a special behavior implying no opmask is used for the particular instruction (this may be implemented in a variety of ways including the use of a opmask hardwired to all ones or hardware that bypasses the masking hardware). When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one example, preserving the old value of each element of the destination where the corresponding mask bit has a 0. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one example, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the opmask field allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While examples are described in which the opmask field's content selects one of a number of opmask registers that contains the opmask to be used (and thus the opmask field's content indirectly identifies that masking to be performed), alternative examples instead or additional allow the mask write field's content to directly specify the masking to be performed.
P[19] can be combined with P[14:11] to encode a second source vector register in a non-destructive source syntax which can access an upper 16 vector registers using P[19]. P[20] encodes multiple functionalities, which differs across different classes of instructions and can affect the meaning of the vector length/rounding control specifier field (P[22:21]). P[23] indicates support for merging-writemasking (e.g., when set to 0) or support for zeroing and merging-writemasking (e.g., when set to 1).
Example examples of encoding of registers in instructions using the third prefix 1601(C) are detailed in the following tables.
Program code may be applied to input information to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor, or any combination thereof.
The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.
Examples of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Examples may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
One or more aspects of at least one example may be implemented by representative instructions stored on a machine-readable medium which represents various logic within the processor, which when read by a machine causes the machine to fabricate logic to perform the techniques described herein. Such representations, known as “intellectual property (IP) cores” may be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that make the logic or processor.
Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
Accordingly, examples also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such examples may also be referred to as program products.
Emulation (Including Binary Translation, Code Morphing, Etc.).
In some cases, an instruction converter may be used to convert an instruction from a source instruction set architecture to a target instruction set architecture. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), morph, emulate, or otherwise convert an instruction to one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on processor, off processor, or part on and part off processor.
Example embodiments include, but are not limited to:
References to “one example,” “an example,” etc., indicate that the example described may include a particular feature, structure, or characteristic, but every example may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same example. Further, when a particular feature, structure, or characteristic is described in connection with an example, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other examples whether or not explicitly described.
Moreover, in the various examples described above, unless specifically noted otherwise, disjunctive language such as the phrase “at least one of A, B, or C” or “A, B, and/or C” is intended to be understood to mean either A, B, or C, or any combination thereof (i.e. A and B, A and C, B and C, and A, B and C).
The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the disclosure as set forth in the claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202241044392 | Aug 2022 | IN | national |
