Patent Application
20230335628
The present application claims priority to Korean Patent Application No. 10-2022-0047300, filed Apr. 18, 2022, the entire contents of which are incorporated herein for all purposes by this reference.
The present disclosure relates to an insulated gate bipolar transistor (IGBT) and a method of manufacturing the same. More particularly, the present disclosure relates to an insulated gate bipolar transistor (IGBT) including a termination region, a second ring region having a first conductivity type, in contact with a first ring region having the first conductivity type to improve breakdown voltage characteristics of the IGBT, and a method of manufacturing the same.
An insulated gate bipolar transistor (IGBT) is an ideal device combining the advantages of a MOSFET and a bipolar transistor: an insulated gate structure and a high current density. Specifically, the IGBT has the advantage of bipolar operation, which can significantly reduce on-resistance by generating conductivity modulation.
As a power semiconductor device, an insulated gate bipolar transistor typically must withstand voltages up to a predetermined breakdown voltage when the gate is turned off, and reliable operation at high temperatures is an important factor of the IGBT.
Therefore, the present disclosure intends to provide a novel insulated gate bipolar transistor with an improved structure capable of ensuring high-temperature reliability and a high breakdown voltage, and a method of manufacturing the same. The details will be described below.
The present disclosure has been made to solve the problems occurring in the related art, an objective of the present disclosure is to provide an insulated gate bipolar transistor including a first ring region (e.g., a heavily doped first conductivity type region) in a drift region of the transistor and within a termination region, to enable the transistor to withstand a relatively high voltage, and to provide a manufacturing method thereof.
In addition, another objective of the present disclosure is to provide an insulated gate bipolar transistor including a second ring region (e.g., a lightly doped first conductivity type region) in contact with the first ring region (or a first side thereof) to deter reaching a critical electric field at a certain time, and to provide a manufacturing method thereof.
In addition, a further objective of the present disclosure is to provide an insulated gate bipolar transistor having improved high temperature reverse bias (HTRB) characteristics by including the second ring, which can move a breakdown point to a position or location under the second ring region, and to provide a manufacturing method thereof.
To achieve the above-mentioned objectives, the present disclosure proposes various embodiments described below.
In a first aspect, one or more embodiments relates to an insulated gate bipolar transistor including a collector electrode; a collector layer on the collector electrode; a drift region on or over the collector layer; a field oxide on a surface of the drift region in a termination region (e.g., of the insulated gate bipolar transistor); a first ring region in the drift region (e.g., in the termination region); a second ring region in contact with the first ring region in the drift region; and a field plate on the field oxide and connected to the first ring region.
In another embodiment, the first ring region may comprise a heavily doped first conductivity type region, and the second ring region may comprise a lightly doped first conductivity type region.
In a further embodiment, the first ring region and the second ring region may be at a surface of the drift region or adjacent to the drift region, and the second ring region has a depth that is about half of a depth of the first ring region.
In a yet further embodiment, the second ring region may be in contact with a first side of the first ring region, and the first side of the first ring region may be relatively far or distant from a neighboring or adjacent active region (e.g., of an adjacent IGBT).
In a yet further embodiment of the present disclosure, the second ring region may be in contact with first and second sides of the first ring region, the first side being relatively far or distant from the neighboring or adjacent active region, the second side being relatively close or nearer to the neighboring or adjacent active region (e.g., closer to the neighboring or adjacent active region than the first side).
In a yet further embodiment, the field plate may be connected to the first ring region via a contact hole in the field oxide.
In a second aspect, one or more embodiments relate to an insulated gate bipolar transistor including a collector electrode; a collector layer having a first conductivity type on the collector electrode; a drift region having a second conductivity type on or over the collector layer; a body region having the first conductivity type in the drift region (and, for example, in an active region of the insulated gate bipolar transistor); a plurality of trench gates in (e.g., extending to a lower end of) the body region (e.g., in the active region); an interlayer insulating film on or over the trench gates; an emitter region having the second conductivity type on the body region; an emitter electrode on the interlayer insulating film; a field oxide on the drift region (e.g., in a termination region of the IGBT); a first ring region comprising a heavily doped first conductivity type region in the drift region (e.g., in the termination region; a second ring region comprising a lightly doped first conductivity type region in the drift region, the second ring region being in contact with the first ring region (e.g., in the drift region); and a field plate through and/or on the field oxide, connected to the first ring region.
In another embodiment, the insulated gate bipolar transistor further includes a body contact having the first conductivity type, in contact with the emitter region in the body region.
In a further embodiment, the insulated gate bipolar transistor further includes a buffer layer having the second conductivity type, on the collector layer.
In a yet further embodiment, each of the trench gates includes a trench, a gate insulating film on an inner wall surface of the trench, and a gate electrode on the gate insulating film (e.g., filling the trench).
In a yet further embodiment, a plurality of the first ring regions may be spaced from each other in the drift region and may be connected to respective ones of a plurality of the field plates (e.g., at one side thereof), and a plurality of the second ring regions may be spaced from each other and in contact with respective ones of the first ring regions in the drift region.
In a yet further embodiment, each of the second ring regions is electrically connected to at least one side of an adjacent or corresponding one of the first ring regions.
In a yet further embodiment, each of the second ring regions may have a height or depth smaller than that of an adjacent one of the first ring regions.
In a third aspect, one or more embodiments relates to a method of manufacturing an insulated gate bipolar transistor including forming a collector layer on a substrate; forming a drift region on or over the collector layer; forming a body region on or in the drift region (e.g., in an active region of the insulated gate bipolar transistor); forming a plurality of trench gates (e.g., extending from the body region to the drift region); forming an emitter region on or in the body region (e.g., between adjacent ones of the trench gates), spaced from each other; forming an interlayer insulating film on or over the trench gates; forming a plurality of first ring regions on or in the drift region (e.g., in a termination region of the insulated gate bipolar transistor); and forming a plurality of second ring regions on or in the drift region such that the second ring regions are in contact with respective ones of the first ring regions.
In another embodiment, forming the first ring region and forming the second ring region includes forming a plurality of first implantation layers, each of which comprises a heavily doped first conductivity type region, on or in the drift region (and, e.g., in the termination region); forming a plurality of second implantation layers, each of which comprises a lightly doped first conductivity type region, such that the second implantation layers are in contact with the respective or corresponding ones of the first implantation regions; and diffusing the first implant layer and the second implant layer (e.g., by thermal diffusion and/or activation).
In a further embodiment, the method further includes forming a field oxide on the drift region (e.g., in the termination region); and forming a plurality of field plates electrically connected to corresponding ones of the first ring regions, through and/or on the field oxide.
In a yet further embodiment, the method further includes forming an emitter electrode (e.g., in the active region) on the interlayer insulating film and the body region. The emitter electrode and the field plate may be formed substantially simultaneously.
In a yet further embodiment, each of the second ring regions may be connected to at least one side of a corresponding one of the first ring regions.
With the configurations described above, the present disclosure has various advantages described below.
The first ring region, which comprises a heavily doped first conductivity type region in the drift region, may be in the termination region of the insulated gate bipolar transistor, and may increase the breakdown voltage of the transistor.
In addition, the second ring region, which comprises a lightly doped first conductivity type region, may contact at least one side of the first ring region, to deter or delay reaching the critical electric field at or to a certain time, thereby improving the breakdown voltage characteristics of the transistor.
In addition, as described above, due to the formation of the second ring region, a breakdown point (e.g., of the insulated gate bipolar transistor) may move to a position or location under the second ring region, thereby improving the HTRB characteristics of the transistor.
On the other hand, even if some effects are not explicitly mentioned herein, when the not-mentioned effects are expected from the technical features of the present disclosure, such effects and potential effects may be treated as if described in the present specification.
Hereinafter, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Embodiments of the present disclosure may be modified in various forms, and the scope of the present disclosure should not be construed as being limited to the following examples, but should be interpreted based on the matters described in the claims. In addition, the present embodiments are provided as a reference for more completely explaining the present disclosure to those with average knowledge of the art.
As used in the present specification, the singular form may include the plural form, unless it clearly points out otherwise in the context. Furthermore, when used herein, “comprise” and/or “comprising” specify the presence or addition of one or more shapes, numbers, steps, operations, members, elements, and/or groups, and do not exclude the presence or addition of one or more other shapes, numbers, steps, operations, members, elements, and/or groups.
Hereinafter, when one component (or layer) is described as being on another component (or layer), it should be noted that the one component may be directly on the other component, or one or more third components or layers may be between the one component and the other component. In addition, when an element is expressed as being directly on or above another element, no other element is between the one element and the other element. Also, being on the “upper”, “lower”, “one side” or “side” of a component means a relative positional relationship.
In the embodiments described below, the first conductivity type may be P-type, and the second conductivity type may be N-type, but is not necessarily limited thereto.
Referring to
Herein, an insulated gate bipolar transistor 1 according to one or more embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Referring to
First, the structure of the active region A1 will be described in detail below.
On a collector electrode 110 comprising, for example, a metal alloy (e.g., an AlMoNiAu alloy), is a collector layer 120, comprising a high-concentration impurity region having a first conductivity type (e.g., as a conductor or semiconductor layer). A buffer layer 130 is on the collector layer 120 and may comprise a high-concentration impurity region having a second conductivity type. In addition, a drift region 140 comprising an impurity region having the second conductivity type is on the buffer layer 130. For example, the drift region 140 may comprise a low-concentration impurity region having the second conductivity type. As will be described later, the collector layer 120, the buffer layer 130, and the drift region 140 may be in the active region A1, the peripheral region A3, and the termination region A2 (e.g., extend from the active region A1 to the termination region A2).
A body region 150 comprising an impurity region having the first conductivity type is on or in the drift region 140, and a channel region (not identified) is in the body region 150. The channel region is a portion of the body region 150 that is inverted to the second conductivity type when the gate voltage exceeds a turn-on threshold to form a current path.
A trench gate 160 is in the body region 150. It is preferable that such the gate 160 penetrates the body region 150 from the uppermost surface of the body region 150 into the drift region 140 (e.g., so that the bottom of the gate 160 is approximately within the drift region 140). A plurality of the trench gates 160 may be horizontally spaced apart from each other, and body region portions 150 may be between adjacent, spaced apart trench gates 160.
Each trench gate 160 includes a gate insulating layer 161 and a gate electrode 163 on an inner wall of the gate insulating layer 161 (e.g., filling the trench). For example, the gate insulating layer 161 may comprise a silicon oxide layer, and the gate electrode 163 may comprise a polysilicon layer doped with second conductivity type impurities. As described above, a plurality of trench gates 160 are spaced apart from each other by a predetermined distance. The gate electrode 163 may face the body region 150 having the first conductivity type through the gate insulating layer 161, thereby forming a channel in the body region 150 (e.g., when the gate electrode 163 has a voltage thereon within a predetermined range).
The gates 160 may be covered with an interlayer insulating layer 170. The interlayer insulating film 170 may comprise, for example, a doped or undoped silicate glass (e.g., a borophosphosilicate glass [BPSG]), but is not limited thereto. In addition, an emitter electrode 190 is on the surface of the device. An emitter region 181 and a body contact 183, which will be described later, are in the body region 150, at an uppermost surface thereof. The emitter electrode 190 may comprise, for example, a conductive metal film or a doped polysilicon film.
At the surface of the body region 150, emitter regions 181, which comprise high-concentration impurity regions having the second conductivity type, are spaced apart from each other and may have a band shape, for example. One side of the emitter region 181 is in contact with the gate insulating film 161, and an opposite side is in contact with or overlaps with the body contact 183, which comprises a high-concentration impurity region having the first conductivity type (to be described later).
The body contacts 183 contact or partially overlap the emitter regions 181 (between adjacent gates 160) and the body region 150. The impurity concentration of the body contact 183 is higher than that of the body region 150, and since carriers (e.g., electrons or holes) can easily move through the body contact 183, the switching speed may increase.
Looking at the specific operation method of the insulated gate bipolar transistor 1 of the present disclosure, when a positive voltage or voltage differential is applied between the emitter electrode 190 and the collector electrode 110, and a voltage higher than the threshold voltage is applied to the gate electrode 163 (e.g., to turn on the gate 160), the channel region inverts to the second conductivity type. Thereafter, electrons from the emitter electrode 190 move to the collector electrode 110 via the emitter region 181, the channel region, the drift region 140, and the collector layer 120. Accordingly, current flows from the collector electrode 110 to the emitter electrode 190.
When the device 1 is off, a voltage or voltage differential may be applied between the collector electrode 110 and the emitter electrode 190 so that the voltage is distributed in an opposite direction between the body region 150 and the drift region 140. As the voltage between the collector electrode 110 and the emitter electrode 190 gradually increases, the device 1 may eventually enter a breakdown state. In this state, the electric field may be concentrated on, in or at the P-N junction region and a region at or adjacent to the bottom of the trench gate 160.
When the gate is turned off, the electron and hole carriers in the drift region 140 respectively move to the collector electrode 110 and the emitter electrode 190. The holes move to the emitter electrode 190 through the body contact 183.
Hereinafter, the structure of the termination region A2 will be described in detail.
Referring to
The first ring region 330 may extend in the termination region A2 and/or the drift region 140 through P-N bonding or along a P-N interface, thereby providing high breakdown voltage characteristics. The first ring region 330 comprises a high-concentration impurity doped region having the first conductivity type and may have a high electric field peak value in the P-N junction region. In particular, a breakdown occurs in the IGBT when the critical electric field value is reached. Referring to
In order to prevent this problem, referring to
The second ring region 340 may contact a side of the first ring region 330 relatively distant from the active region A1 and/or a side of the first ring region 330 nearer or adjacent to the active region A1, but is not limited thereto. In addition, it is preferable that the second ring region 340 has a depth about half of that of the first ring region 330, measured from an uppermost surface of the drift region 140.
Hereinafter, a method of manufacturing an insulated gate bipolar transistor according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Meanwhile, when an embodiment can be implemented differently, each process or step may occur in a different order from the described order. For example, two processes or steps described may be performed substantially concurrently or in a reverse order.
Referring to
Then, the drift region 140 is formed on the upper side of the buffer layer 130. The drift region 140 may comprise silicon having a low concentration of second conductivity type impurities therein. The drift region 140 may be formed by, for example, epitaxial growth, similarly to the buffer layer 130. However, the drift region 140 may comprise a plurality of cycles of epitaxial growth, optionally followed by ion implantation when the epitaxial growth does not include the impurities.
Thereafter, the first ring region 330 and the second ring region 340 are formed in the termination region A2. One or more of each of the ring regions 330 and 340 are formed in the termination region A2, and it is preferable that a plurality of the first ring regions 330 and a plurality of the second ring regions 340 are formed in the termination region A2. This will be explained in detail.
Referring to
Then, referring to
Thereafter, a field oxide 310 is formed on the drift region 140 in the termination region A2. The field oxide 310 may comprise, for example, undoped silicon dioxide, and be formed by local oxidation of silicon (LOCOS), but is not limited thereto.
Referring to
Then, referring to
Subsequently, an oxide film (e.g., silicon dioxide) is conventionally formed on the inner wall of the trenches to form the gate insulating film 161. In one embodiment, in the presence of the patterned oxide film or patterned bilayer, the body region 150 exposed in the trenches may be thermally oxidized to form the gate insulating film 161. Alternatively, after removal of the patterned oxide film or patterned bilayer, a silicon dioxide layer may be conformally deposited into the trenches and onto the uppermost surface of the body region 150. Then, polysilicon doped with second conductivity type impurities is deposited on the silicon dioxide layer including the gate insulating film 161 to fill the trenches. The polysilicon doped with second conductivity type impurities and the silicon dioxide layer on or above the uppermost surface of the body region 150 are removed conventionally (e.g., by etchback or wet etching), in which case the field oxide 310 may be conventionally protected (e.g., with a photoresist).
After that, referring to
Referring to
After that, an interlayer insulating film 170 is formed on the body region 150 and the gates 160. An insulating film (e.g., a multi-layer insulating film) is deposited on the body region 150 and the gates 160, then the insulating film is etched using a photoresist pattern (not shown) as a mask. Thus, the interlayer insulating film 170 covering at least the gates 160 is formed. Then, the photoresist pattern (not shown) is removed.
Referring to
At this time, the field plate(s) 320 may also be formed in the termination region A2. Contact holes (not shown) may be formed by etching the field oxide 310 over the first ring region(s) 330 in the termination region A2 (optionally at the same time that the insulating film forming the interlayer insulating film 170 is etched), and a field plate film (not shown) is blanket-deposited on the resulting structure. The material of the emitter electrode 190 and the field plate film may be the same, but the invention is not limited thereto. Thereafter, the field plate film may be etched to form the field plate(s) 320 on the individual first ring regions 330.
Referring to
The above detailed description is illustrative of the present disclosure. In addition, the above description shows and describes various embodiments of the present disclosure, and the present disclosure may be used in various environments such that various embodiments are diversely combined or modified. That is, various changes or modifications to the embodiments are possible without departing from the scope of the concept of the disclosure disclosed herein, the scope equivalent to the written disclosure, and/or the scope of skill or knowledge in the relevant art. The embodiments are provided to describe various states for implementing the technical idea of the present disclosure, and various changes required in the specific applications and uses of the present disclosure are possible. Therefore, the detailed description of the present disclosure is not intended to limit the present disclosure to the disclosed embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0047300 | Apr 2022 | KR | national |
