Claims
- 1. An integrated circuit, comprising:a memory cell array; circuits peripheral to said array; a conductor coupling said array to said peripheral circuits, said conductor having a first horizontal portion with a first thickness in said array and a second horizontal portion with a second thickness in said peripheral circuits wherein said second thickness differs from said first thickness; wherein said conductor comprises tungsten silicide.
- 2. An integrated circuit, comprising:a memory cell array including wordlines formed on a substrate and bitlines and capacitors formed over said wordlines, said bitlines having a first thickness horizontally and pitch; and circuits peripheral to said array including transistors formed in said substrate and conductors over said transistors, said conductors having a second thickness horizontally and pitch; wherein said bitlines and conductors are formed in a common conductive layer and said first thickness and said second thickness differ; wherein said bitlines and conductors comprises tungsten silicide.
CROSS REFERENCE
This application claims priority under 35 USC §120 and is a continuation of application Ser. No. 08/970,222 filed Nov. 14, 1997 now abandoned.
US Referenced Citations (11)
Continuations (1)
|
Number |
Date |
Country |
Parent |
08/970222 |
Nov 1997 |
US |
Child |
09/776212 |
|
US |