The present disclosure is generally related to an integrated circuit device including multiple via connectors and a metal structure having a ladder shape.
Advances in technology have resulted in smaller and more powerful computing devices. For example, a variety of portable personal computing devices, including wireless telephones such as mobile and smart phones, tablets and laptop computers are small, lightweight, and easily carried by users. These devices can communicate voice and data packets over wireless networks. Further, many such devices incorporate additional functionality such as a digital still camera, a digital video camera, a digital recorder, and an audio file player. Also, such devices can process executable instructions, including software applications, such as a web browser application, that can be used to access the Internet. As such, these devices can include significant computing and networking capabilities.
In some implementations of a memory (e.g., a static random access memory (SRAM)) that use a 1-dimensional (1D) metal design to form a first metal layer (i.e., a “metal-1” or M1 layer), different metal “tracks” are used for a word line of a memory cell and for a power line of the memory cell. In some implementations, a word line may be formed in a second metal layer (i.e., a “metal-2” or M2 layer), and a word line connecting pad may be formed in the first metal layer. To form word line connecting pads, a cut process may be performed using a cut metal pattern. As integrated circuit design sizes decrease (i.e., scale) with fabrication technology, dimensions of the cut metal pattern, such as a width of the cut metal pattern or a pitch between the cut metal pattern and a proximate metal line, also decrease. As the dimensions of the cut metal pattern continue to decrease, patterning the cut metal pattern becomes more difficult.
The present disclosure describes an integrated circuit that includes multiple via connectors and a metal structure that is separate from and that encircles (e.g., surrounds) the multiple metal connectors. For example, the metal structure may have a ladder shape and may encircle the multiple via connectors. The via connectors and the metal structure may be included in a first metal layer (e.g., a “metal-1” or M1 layer) of an integrated circuit. Each via connector may be coupled to a group of vias that are configured to couple a circuit component included in a first layer (e.g., a circuit component layer beneath the first metal layer) and a word line included in a second metal layer (e.g., a “metal-2” or M2 layer). In a particular implementation, a via connector (and a corresponding group of vias) may be configured to couple a gate of a transistor included in the first layer to the word line included in the second metal layer. Because the metal structure is separate from the multiple via connectors, each via connector is isolated from other via connectors and thereby enables each group of vias to couple together different elements from the first layer and the second metal layer. Additionally, the metal structure having the ladder shape may be formed using one or more mandrels and multiple spacers during a fabrication process. Because the metal structure encircles the multiple via connectors, the via connectors are formed without performing a cut process using a cut metal pattern.
In a particular aspect, an apparatus includes a first via and a second via. The apparatus includes a first via connector coupled to the first via and a second via connector coupled to the second via. The apparatus further includes a metal structure separated from and encircling the first via connector and the second via connector.
In another particular aspect, a method of fabricating an integrated circuit device includes forming a first layer that includes one or more circuit elements. The method further includes forming a second layer that includes a first via connector, a second via connector, and a metal structure, the metal structure separated from and encircling the via connectors.
In a particular aspect, an apparatus includes means for coupling a first group of vias. The apparatus includes means for coupling a second group of vias. The apparatus further includes means for conducting. The means for conducting may be separate from and may encircle the means for coupling the first group of vias and the means for coupling the second group of vias.
In another particular aspect, a non-transitory computer-readable medium stores instructions that, when executed by a processor, cause the processor to perform operations including initiating formation of a first layer that includes a first circuit element and a second circuit element. The operations include initiating formation of multiple mandrel structures. The operations include initiating deposition of spacing material proximate to each of the multiple mandrel structures to form spacers. The operations include initiating removal of the multiple mandrel structures. The operations include initiating performance of a hard mask etch process to form trenches around the spacers. The operations include initiating removal of the spacers. The operations include initiating filling of the trenches with metal to produce a first via connector, a second via connector, and a metal structure. The metal structure may be separate from and may encircle the first via connector and the second via connector. The operations further include initiating patterning of a first via coupled to the first circuit element and the first via connector and patterning of a second via coupled to the second circuit element and the second via connector.
One particular advantage provided by at least one of the disclosed aspects is an integrated circuit that includes multiple via connectors and a metal structure that is separate from and encircles the multiple via connectors. By forming such a metal structure, multiple via connectors may be formed without use of a cut metal pattern, thereby reducing complexity and/or cost of a fabrication process. Additionally, the metal structure may have a ladder shape, which may enable use of fewer vias than other implementations, and may reduce VSS fluctuations on the metal structure.
Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the claims.
Referring to
As illustrated in
The first via connector 102 may be coupled to a first group of vias that includes a first via 110 (V1) and second via 120 (V2), and the second via connector 104 may be coupled to a second group of vias that includes a third via 112 (V3) and a fourth via 122 (V4). The first via 110 and the third via 112 may be included in the same via layer, and the second via 120 and the fourth via 122 may be included in the same via layer, as illustrated in
Because the metal structure 106 is separate from each of the via connectors 102 and 104, each of the via connectors (e.g., 102 and 104) is isolated and may be coupled to different devices or structures in the circuit element layer 140 and the second metal layer 144. For example, the first via connector 102 may be electrically isolated from (e.g., not electrically coupled to) the second via connector 104. The first via connector 102 may be coupled to a different elements in the circuit element layer 140 and the second metal layer 144 than the second via connector 104.
In some implementations, metal lines in the first metal layer 142 may be aligned in a first alignment direction (e.g., horizontally), and metal lines in the second metal layer 144 may be aligned in a second alignment direction (e.g., vertically). For example, the via connectors 102 and 104 may be routed in a first alignment direction, and the word lines 150 and 152 may be routed in a second alignment direction, as illustrated in
In some implementations, the integrated circuit device 100 may include or correspond to a memory device (e.g., a memory including one or more memory cells). For example, the integrated circuit device 100 may include or correspond to a static random access memory (SRAM) device. The word lines 150 and 152 may be coupled to SRAM cells of the SRAM device, and the transistors 130 and 132 may correspond to transistors, such as pass-gate transistors, of an SRAM cell. In a particular implementation, the SRAM cell may be a six transistor (6T) SRAM cell.
In some implementations, the first via connector 102 and the second via connector 104 may include (or be referred to as) “word line connection pads.” The first via connector 102 may include or correspond to a word line connection pad coupled to the first word line 150 of a memory cell. Additionally, the second via connector 104 may include or correspond to a word line connection pad coupled to the second word line 152 of a memory cell.
In some implementations, the metal structure 106 includes a voltage source connection. For example, the metal structure 106 may be a metal line that is coupled to a voltage source of a memory. In some implementations, the metal structure 106 may be coupled to a voltage source (VSS). In other implementations, the metal structure 106 may be coupled to ground. One or more transistors of the memory may be coupled to VSS (or ground) by being coupled to the metal structure 106. In a particular implementation, the metal structure 106 may be a voltage source connection for two adjacent memory cells. In this implementation, the metal structure 106 may be referred to as a “merged VSS line.”
In a particular aspect, the first via connector 102 may couple the first via 110 to the second via 120, and the first via 110 and the second via 120 may form a first via group. The second via connector 104 may couple the third via 112 to the fourth via 122, and the third via 112 and the fourth via 122 may for a second via group. Additionally, the first via 110 may couple the first gate 134 of the first transistor 130 to the first via connector 102, and the second via 120 may couple the first via connector 102 to the first word line 150. In some implementations, the first gate 134 is included in a first layer (e.g., the circuit element layer 140) of the integrated circuit device 100. The first via connector 102, the second via connector 104, and the metal structure 106 are included in the first metal layer 142 of the integrated circuit device 100. The first word line 150 is included in the second metal layer 144 of the integrated circuit device 100. In some implementations, the integrated circuit device 100 includes or corresponds to a SRAM device. The first transistor 130 and the first word line 150 may be included in a 6T memory cell of the SRAM device.
By forming the via connectors 102 and 104 and the metal structure 106, as further described herein, the via connectors 102 and 104 may be formed without performing a cut process using a cut metal pattern. Because the metal structure 106 is separate from and encircles the via connectors 102 and 104, each of the via connectors 102 and 104 are able to be coupled to different structures in other layers of the integrated circuit device 100. Coupling the via connectors 102 and 104 to different structures may reduce complexity of routing in the integrated circuit device 100. Additionally, because the metal structure 106 is formed separate from and encircling the via connectors 102 and 104, the metal structure 106 may be formed without using a cut metal pattern, as further described herein. Forming the metal structure 106 without using a cut metal pattern reduces complexity and/or cost of a fabrication process of the integrated circuit device 100. Additionally, the metal structure 106 may have reduced VSS fluctuations due to the ladder shape as compared to VSS lines in other memories that do not have a ladder shape.
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Because the multiple via connectors 102 and 104 and the metal structure 106 are formed using the multiple mandrel structures, the via connectors 102 and 104 are formed without performing a cut process using a cut metal pattern. To illustrate, in other fabrication processes, small metal structures such as the via connectors 102 and 104 that have a tight pitch to surrounding metal structures (e.g., the metal structure 106) are formed by forming larger metal structures and performing a cut process using a cut mask to remove portions of the larger metal structure, resulting in the small metal structures. Performing a cut process using a cut metal pattern increases complexity and cost of a fabrication process. Thus, the steps illustrated in
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Because the multiple via connectors 102 and 104 and the metal structure 106 are formed using the multiple mandrel structures, the via connectors 102 and 104 and the metal structure 106 are formed without performing a cut process using a cut metal pattern. Performing a cut process using a cut metal pattern increases complexity and cost of a fabrication process. Thus, the steps illustrated in
Referring to
In a particular implementation, the multiple mandrel structures may include a mandrel structure having a ladder shape. For example, the multiple mandrel structures may include the mandrel structure 702 of
The method further includes removing the multiple mandrel structures, at 1008. For example, the mandrel structures shown in
The method 1000 further includes filling the trenches with metal to produce a first via connector, a second via connector, and a metal structure, at 1014. Examples of the first via connector 102, the second via connector 104, and the metal structure 106 are shown in
The method 1000 may form multiple via connectors and a metal structure that is separate from and encircles the multiple via connectors. By forming such a metal structure, multiple via connectors may be formed without performing a cut process using a cut metal pattern, thereby reducing complexity and/or cost of a fabrication process.
The method 1000 of
Referring to
The device 1100 includes a processor 1110, such as a digital signal processor (DSP), coupled to a memory 1132. The processor 1110 may include the integrated circuit device 100 of
The memory 1132 includes instructions 1168 (e.g., executable instructions) such as computer-readable instructions or processor-readable instructions. The instructions 1168 may include one or more instructions that are executable by a computer, such as the processor 1110.
In conjunction with one or more of the described aspects of
The apparatus may further include means for conducting. The means for conducting may be separated from and may encircle the means for coupling the first group of vias and the means for coupling the second group of vias. The means for conducting may include or correspond to the metal structure 106, one or more other structures or circuits configured to couple a first group of vias, or any combination thereof.
One or more of the disclosed embodiments may be implemented in a system or an apparatus, such as the device 1100, that may include a communications device, a fixed location data unit, a mobile location data unit, a mobile phone, a cellular phone, a satellite phone, a computer, a tablet, a portable computer, or a desktop computer. Additionally, the device 1100 may include a set top box, an entertainment unit, a navigation device, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a video player, a digital video player, a digital video disc (DVD) player, a portable digital video player, any other device that stores or retrieves data or computer instructions, or a combination thereof. As another illustrative, non-limiting example, the system or the apparatus may include remote units, such as mobile phones, hand-held personal communication systems (PCS) units, portable data units such as personal data assistants, global positioning system (GPS) enabled devices, navigation devices, fixed location data units such as meter reading equipment, or any other device that stores or retrieves data or computer instructions, or any combination thereof.
The foregoing disclosed devices and functionalities may be designed and configured into computer files (e.g. RTL, GDSII, GERBER, etc.) stored on computer readable media. Some or all such files may be provided to fabrication handlers to fabricate devices based on such files. Resulting products include semiconductor wafers that are then cut into semiconductor dies and packaged into semiconductor chips. The semiconductor chips are then employed in devices described above.
Physical device information 1202 is received at the manufacturing process 1200, such as at a research computer 1206. The physical device information 1202 may include design information representing at least one physical property of a semiconductor device, such as the integrated circuit device 100 of
In a particular implementation, the library file 1212 includes at least one data file including the transformed design information. For example, the library file 1212 may include a library of semiconductor devices including the integrated circuit device 100 of
The library file 1212 may be used in conjunction with the EDA tool 1220 at a design computer 1214 including a processor 1216, such as one or more processing cores, coupled to a memory 1218. The EDA tool 1220 may be stored as processor executable instructions at the memory 1218 to enable a user of the design computer 1214 to design a circuit including the integrated circuit device 100 of
The design computer 1214 may be configured to transform the design information, including the circuit design information 1222, to comply with a file format. To illustrate, the file formation may include a database binary file format representing planar geometric shapes, text labels, and other information about a circuit layout in a hierarchical format, such as a Graphic Data System (GDSII) file format. The design computer 1214 may be configured to generate a data file including the transformed design information, such as a GDSII file 1226 that includes information describing the integrated circuit device 100 of
The GDSII file 1226 may be received at a fabrication process 1228 to manufacture the integrated circuit device 100 of
For example, the fabrication process 1228 may include a processor 1234 and a memory 1235 to initiate and/or control the fabrication process 1228. The memory 1235 may include executable instructions such as computer-readable instructions or processor-readable instructions. The executable instructions may include one or more instructions that are executable by a computer such as the processor 1234.
The fabrication process 1228 may be implemented by a fabrication system that is fully automated or partially automated. For example, the fabrication process 1228 may be automated according to a schedule. The fabrication system may include fabrication equipment (e.g., processing tools) to perform one or more operations to form a semiconductor device. For example, deposit one or more materials, epitaxially grow one or more materials, conformally deposit one or more materials, apply a hardmask, apply an etching mask, perform etching, perform planarization, form a dummy gate stack, form a gate stack, perform a standard clean 1 type, etc.
The fabrication system (e.g., an automated system that performs the fabrication process 1228) may have a distributed architecture (e.g., a hierarchy). For example, the fabrication system may include one or more processors, such as the processor 1234, one or more memories, such as the memory 1235, and/or controllers that are distributed according to the distributed architecture. The distributed architecture may include a high-level processor that controls or initiates operations of one or more low-level systems. For example, a high-level portion of the fabrication process 1228 may include one or more processors, such as the processor 1234, and the low-level systems may each include or may be controlled by one or more corresponding controllers. A particular controller of a particular low-level system may receive one or more instructions (e.g., commands) from a high-level system, may issue sub-commands to subordinate modules or process tools, and may communicate status data back to the high-level system. Each of the one or more low-level systems may be associated with one or more corresponding pieces of fabrication equipment (e.g., processing tools). In a particular aspect, the fabrication system may include multiple processors that are distributed in the fabrication system. For example, a controller of a low-level system component of the fabrication system may include a processor, such as the processor 1234.
Alternatively, the processor 1234 may be a part of a high-level system, subsystem, or component of the fabrication system. In another aspect, the processor 1234 includes distributed processing at various levels and components of a fabrication system.
Thus, the processor 1234 may include processor-executable instructions that, when executed by the processor 1234, cause the processor 1234 to initiate or control formation of an integrated circuit device. In a particular aspect, the processor 1234 may perform operations including initiating formation of a first layer that includes a first circuit element and a second circuit element. The operations may include initiating formation of multiple mandrel structures. The operations may include initiating deposition of spacing material proximate to each of the multiple mandrel structures to form spacers. The operations may include initiating removal of the multiple mandrel structures. The operations may include initiating performance of a hard mask etch process to form trenches around the spacers. The operations may include initiating removal of the spacers. The operations may include initiating filling of the trenches with metal to produce a first via connector, a second via connector, and a metal structure, the metal structure separated from and encircling the first via connector and the second via connector. The operations may further include initiating patterning of a first via coupled to the first circuit element and the first via connector and patterning of a second via coupled to the second circuit element and the second via connector. One or more of the operations may be performed by controlling one of more deposition tools, such as a molecular beam epitaxial growth tool, a flowable chemical vapor deposition (FCVD) tool, a conformal deposition tool, or a spin-on deposition tool, one or more removal tools, such as a chemical removal tool, a reactive gas removal tool, a hydrogen reaction removal tool, or a standard clean 1 type removal tool, one or more etchers, such as a wet etcher, a dry etcher, or a plasma etcher, one or more dissolving tools, such as a developer or developing tool, one or more other tools, or a combination thereof.
The executable instructions included in the memory 1235 may enable the processor 1234 to initiate formation of a semiconductor device such as the integrated circuit device 100 of
The die 1236 may be provided to a packaging process 1238 where the die 1236 is incorporated into a representative package 1240. For example, the package 1240 may include the single die 1236 or multiple dies, such as a system-in-package (SiP) arrangement. The package 1240 may be configured to conform to one or more standards or specifications, such as Joint Electron Device Engineering Council (JEDEC) standards.
Information regarding the package 1240 may be distributed to various product designers, such as via a component library stored at a computer 1246. The computer 1246 may include a processor 1248, such as one or more processing cores, coupled to a memory 1250. A printed circuit board (PCB) tool may be stored as processor executable instructions at the memory 1250 to process PCB design information 1242 received from a user of the computer 1246 via a user interface 1244. The PCB design information 1242 may include physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device corresponding to the package 1240 including the integrated circuit device 100 of
The computer 1246 may be configured to transform the PCB design information 1242 to generate a data file, such as a GERBER file 1252 with data that includes physical positioning information of a packaged semiconductor device on a circuit board, as well as layout of electrical connections such as traces and vias, where the packaged semiconductor device corresponds to the package 1240 including the integrated circuit device 100 of
The GERBER file 1252 may be received at a board assembly process 1254 and used to create PCBs, such as a representative PCB 1256, manufactured in accordance with the design information stored within the GERBER file 1252. For example, the GERBER file 1252 may be uploaded to one or more machines to perform various steps of a PCB production process. The PCB 1256 may be populated with electronic components including the package 1240 to form a representative printed circuit assembly (PCA) 1258.
The PCA 1258 may be received at a product manufacture process 1260 and integrated into one or more electronic devices, such as a first representative electronic device 1262 and a second representative electronic device 1264. For example, the first representative electronic device 1262, the second representative electronic device 1264, or both, may include or correspond to the wireless communication device 1100 of
A device that includes the integrated circuit device 100 of
Although one or more of
Those of skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software executed by a processor, or combinations of both. Various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or processor executable instructions depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The steps of a method or algorithm described in connection with the disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disk, a removable disk, a compact disc read-only memory (CD-ROM), or any other form of non-transient storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a computing device or a user terminal In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal
The previous description is provided to enable a person skilled in the art to make or use the disclosed implementations. Various modifications to these implementations will be readily apparent to those skilled in the art, and the principles defined herein may be applied to other implementations without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the implementations shown herein but is to be accorded the widest scope possible consistent with the principles and novel features as defined by the following claims.
The present application claims priority from U.S. Provisional Patent Application No. 62/114,563, filed Feb. 10, 2015 and entitled “INTEGRATED CIRCUIT DEVICE INCLUDING MULTIPLE VIA CONNECTORS AND A METAL STRUCTURE HAVING A LADDER SHAPE,” the content of which is expressly incorporated herein by reference in its entirety.
Number | Date | Country | |
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62114563 | Feb 2015 | US |