Claims
- 1. A method of inlaid interconnect fabrication, comprising the steps of:(a) provide a dielectric layer; (b) form a silicon carbide layer on said dielectric layer; (c) form vias and trenches in said silicon carbide and dielectric layers; (d) deposit conducting material on said silicon carbide and dielectric; and (e) planarize to remove said conducting material outside of said vias and trenches with said silicon carbide as a planarization stop.
- 2. The method of claim 1, wherein:(a) said planarize is by chemical mechanical polishing.
RELATED APPLICATIONS
This application claims priority from provisional application Serial No. 60/104,454, filed 10/16/98.
The following copending patent applications disclose related subject matter: Ser. No. 09/217,123, filed 12/21/98 (T26419). These applications have a common assignee with the present application.
US Referenced Citations (5)
Number |
Name |
Date |
Kind |
4351894 |
Yonezawa et al. |
Sep 1982 |
A |
5362669 |
Boyd et al. |
Nov 1994 |
A |
5578523 |
Fiordalice et al. |
Nov 1996 |
A |
5817572 |
Chiang et al. |
Oct 1998 |
A |
5958793 |
Patel et al. |
Aug 1999 |
A |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/104454 |
Oct 1998 |
US |