Patent Application
20120032339
The present invention relates to an integrated circuit structure. More particularly, the present invention relates to an integrated circuit structure with a through via for heat evacuating.
Packaging technology for integrated circuit structures has been to continuously developed to meet the demand toward miniaturization and mounting reliability. Recently, as the miniaturization and high functionality of electric and electronic products are required, various techniques have been disclosed in the art.
By using a stack of at least two chips, in the case of a memory device for example, it is possible to produce a product having a memory capacity which is two times as large as that obtainable through semiconductor integration processes. Also, a stack package provides advantages not only through an increase in memory capacity but also in view of a mounting density and mounting area utilization efficiency. Due to this fact, research and development of stack package technology has accelerated.
As an example of a stack package, a through-silicon via (TSV) has been disclosed in the art. The stack package using a TSV has a structure in which the TSV is disposed in a chip so that chips are physically and electrically connected with each other through the TSV. A vertical hole is defined through a predetermined portion of each chip at a wafer level. A dielectric layer is disposed on the sidewall of the vertical hole. With a metal layer disposed on the dielectric layer, an electrolytic substance, i.e. a metal, is filled into the vertical hole through an electroplating process to form a TSV. Next, the TSV is exposed through back-grinding of the backside of a wafer.
After the wafer is sawed and separated into individual chips, at least two chips can be vertically stacked, one atop the other, on one of the substrates using one or more of the TSV. Thereupon, the upper surface of the substrate including the stacked chips is molded, and solder balls are mounted on the lower surface of the substrate, by which the manufacture of a stack package is completed.
As is known, semiconductor chips generate heat while operating. Different thermal expansion coefficients between silicon and metal or to metallic substance can causes stresses in a semiconductor chip as its temperature rises and falls during operation, which is a phenomenon that can significantly deteriorate the integrity and the reliability of silicon/metal junctions in a chip during the operation of the semiconductor chip. Displacements of respective materials vary when operation temperature is changed, and if the stress caused by the difference in thermal expansion coefficient cannot be relieved, a fracture of the package may result.
Furthermore, the heat from operating chips usually causes dysfunction of the integrated circuit structure. When the temperature of the chip increases, it becomes relevant for cases of relatively small-cross-section wires, because such temperature increase may affect the normal behavior of integrated circuit structure. Thus, the problem of heat dissipation in integrated circuit structures has attracted increasing interest in recent years due to the miniaturization of semiconductor devices.
To solve the problems of the above-mentioned prior art, the present invention discloses an integrated circuit structure comprising a semiconductor substrate, an active device disposed on a first region of the semiconductor substrate, a layer stack disposed on a second region of the semiconductor substrate, a through via penetrating through the layer stack and the semiconductor substrate, and a third dielectric layer between the through via and the semiconductor substrate. In one embodiment of the present invention, the layer stack includes a first dielectric layer disposed on the semiconductor substrate and a heat-conducting member disposed on the first dielectric layer.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set is forth in the appended claims.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the invention.
In one embodiment of the present invention, the layer stack 132 includes a dielectric layer such as a silicon oxide layer 1321 disposed on the semiconductor substrate 12, a polysilicon layer 1323 disposed on the oxide layer 1321, and a metal layer 1324 disposed on the polysilicon layer 1323. In one embodiment of the present invention, a dielectric layer such as a silicon nitride layer 1325 is then formed to cover the oxide layer 1321, the polysilicon layer 1323 and the metal layer 1234.
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In one embodiment of the present invention, the polysilicon layer 1323 and the metal layer 1324 forms a heat-conducting member 1322A, and the heat-conducting member 1322A and the through via 141 forms a heat conductor 1326A of the integrated circuit structure 10A for evacuating the operating heat generated by the transistor 11 from the semiconductor substrate 12 to the outside of the integrated circuit structure 10A. In another embodiment of the present invention, the heat-conducting material could be selected from the group consisting of tin, tungsten, copper, polysilicon and a combination thereof. In this embodiment shown in
In one embodiment of the present invention, the transistor 11 includes a gate conductor 110 above the semiconductor substrate 12, and the layer structure of the gate conductor 110 is substantially the same as that of the heat-conducting member 1322A, i.e., the gate conductor 110 includes a polysilicon layer 111 and a metal layer 113, and can be fabricated in the same process as the polysilicon layer 1323 and the metal layer 1324 of the layer stack 132. In one embodiment of the present invention, the through via 141 substantially penetrates through the center of the heat-conducting member 1322A such that the heat conductor 1326 has an antenna profile.
In one embodiment of the present invention, the distance between the transistor 11 and the dielectric layer 15 is preferably between 4 pm and 8 pm so as to prevent the through via 141 from interfering with the transistor 11. In addition, in order to ensure sufficient insulation characteristics of the dielectric layer 15, the thickness of the dielectric layer 15 is preferably between 0.5 μm and 2 μm. Due to the miniaturization of the integrated circuit structure 10A, the chip-operating heat usually causes unexpected effects on the integrated circuit structure device. Since the heat conductor 1326A including the polysilicon layer 1323, the metal layer 1324 and the through via 141 is capable of conducting the operating heat of the transistor 11 away from the transistor 11, the integrated circuit structure 10A of the present invention could have a better heat dissipation result through the heat conductor 1326A.
The thermal conductivity of the oxide layer 1321 and the nitride layer 1325 is relatively low (Kox˜1.4 W/m K). Thus, the thickness of the oxide layer 1321 in the present invention is attenuated such that the transfer of the transistor-operating heat from the transistor 11 out of the integrated circuit structure 10A is implemented through the semiconductor substrate 12, the oxide layer 1321, the heat-conducing member 1322A to the upper end and the bottom end of the through via 141, while maintaining a proper insulation characteristic of the oxide layer 1321. In one embodiment of the present invention, the thickness of the oxide layer 1321 is preferably between 10 Å and 30 Å. In particular, the second region 122 of the semiconductor substrate 12 is a keep out zone where no active device is disposed such that no extra area is needed for implementing the heat conductor 1326A, while the enhanced heat-dissipation mechanism is fulfilled.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
