INTEGRATED CIRCUIT STRUCTURES HAVING A BORON ETCH-STOP LAYER AND METHODS, DEVICES AND SYSTEMS RELATED THERETO

Abstract

An integrated circuit structure comprising a boron etch-stop layer on a surface of the integrated circuit structure having a full-width half-maximum (FWHM) thickness value less than 100 nanometers, wherein the boron etch-stop layer is substantially free of germanium and carbon. In one embodiment, the boron etch-stop layer has a FWHM thickness value less than 20 nanometers and may contain added germanium or carbon. Systems and devices containing same are also disclosed. Chemical vapor deposition (CVD) may be used to form the boron etch-stop layer.

Description

TECHNICAL FIELD

The subject matter herein relates to integrated circuit (IC) structures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 1B, 1C and 1D are cross-sectional views of a prior art bond and etch back silicon on insulator (BESOI) fabrication technique.

FIGS. 2A, 2B and 2C are cross-sectional views indicating a method to determine etch-stop efficiency in embodiments of the invention.

FIG. 3 is a graph indicating relative etch rates for an ethylenediamine-pyrocatechol (EDP) wet-chemical etchant as a function of boron concentration contained within a silicon (100) substrate at different annealing temperatures in embodiments of the invention.

FIG. 4 is a graph indicating a diffusion constant of boron as a function of germanium content at 800° C. in embodiments of the invention.

FIG. 5 is a graph indicating full-width half-maximum (FWHM) depth of a boron profile produced in accordance with the present invention and measured after thermal annealing steps in embodiments of the invention.

FIG. 6 is a graph indicating boron diffusion depth in SiGe:C:B at various anneal temperatures in embodiments of the invention.

FIG. 7 is a graph indicating boron diffusion profiles and relative depth in a remote carbon method in embodiments of the invention.

DETAILED DESCRIPTION

General Background

Several material systems have emerged as key facilitators to extend Moore's law well into the next decade. These key facilitators include silicon-on-insulator (SOI), silicon-germanium (SiGe), and strained silicon. With reference to SOI and related technologies, there are numerous advantages associated with an insulating substrate. These advantages include reduced parasitic capacitances, improved electrical isolation, and reduced short-channel effects. Advantages of SOI can be combined with energy bandgap and carrier mobility improvements offered by Si_1-xGe_x and strained silicon devices.

SOI substrates generally include a thin layer of silicon on top of an insulator. Integrated circuit components are formed in and on the thin layer of silicon. The insulator can be comprised of insulators such as silicon dioxide (SiO₂), sapphire, or various other insulative materials.

Currently, several techniques are available to fabricate SOI substrates. One technique for fabricating SOI substrates is separation by implantation of oxygen (SIMOX). In a SIMOX process, oxygen is implanted below a surface of a silicon wafer. A subsequent anneal step produces a buried silicon dioxide layer with a silicon overlayer. However, the time required for an implantation in a SIMOX process can be extensive and, consequently, cost prohibitive. Moreover, an SOI substrate formed by SIMOX may be exposed to high surface damage and contamination.

Another technique is bond-and-etch-back SOI (BESOI), where an oxidized wafer is diffusion-bonded to a non-oxidized wafer. With reference to FIG. 1A, a silicon device wafer 100 and a silicon handle wafer 150 comprise the major components for forming a BESOI wafer. The silicon device wafer 100 includes a first silicon layer 101, which will serve as a device layer, an etch-stop layer 103, and a second silicon layer 105. The etch-stop layer 103 is frequently comprised of boron. The silicon handle wafer 150 includes a lower silicon dioxide layer 107A, a silicon substrate layer 109, and an upper silicon dioxide layer 107B. The lower 107A and upper 107B silicon dioxide layers are frequently thermally grown oxides formed concurrently.

In FIG. 1B, the silicon device wafer 100 and the silicon handle wafer 150 are brought into physical contact and bonded, one to the other. The initial bonding process is followed by a thermal anneal, thus strengthening the bond. The silicon device wafer 100 in the bonded pair is thinned. Initially, most of the second silicon layer 105 is removed by mechanical grinding and polishing until only a few tens of micrometers (i.e., “microns” or μm) remain. A high-selectivity wet or dry chemical etch removes remaining portions of the second silicon layer 105, stopping on the etch-stop layer 103. (Selectivity is discussed in detail, below.) An end-result of the second silicon layer 105 etch process is depicted in FIG. 1C.

During the etching process, the silicon handle wafer 150 is protected by a coated mask layer (not shown). In FIG. 1D, the etch-stop layer 103 has been removed using another high-selectivity etchant. As a result of these processes, the first silicon layer 101, serving as a device layer, is transferred to the silicon handle wafer 150. A backside of the silicon substrate layer 109 is ground, polished, and etched to achieve a desired overall thickness.

To ensure BESOI substrates are thin enough for subsequent fabrication steps, as well as meeting contemporary demands for ever-decreasing physical size and weight constraints, BESOI requires the presence of the etch-stop layer 103 during the layer transfer process. Currently, two main layer transfer technologies exist, namely selective chemical etching (as discussed above) and splitting of a hydrogen-implanted layer from a device layer (a hydrogen implantation and separation process). Both technologies meet requirements of advanced semiconductor processing.

In the hydrogen implantation and separation process, hydrogen (H₂) is implanted into silicon having a thermally grown silicon dioxide layer. The implanted H₂ embrittles the silicon substrate underlying the silicon dioxide layer. The H₂ implanted wafer may be bonded with a second silicon wafer having a silicon dioxide overlayer. The bonded wafer may be cut across the wafer at a peak location of the hydrogen implant by appropriate annealing.

The BESOI process described is relatively free from ion implant damage inherent in the SIMOX process. However, the BESOI process requires a time consuming sequence of grinding, polishing, and chemical etching.

As described above, the BESOI process is a manufacturing-oriented technique to build silicon on insulator substrates and is partially dependent upon chemical etching. Etch-stop performance is described by a mean etch selectivity, S, which defines an etch rate ratio of silicon to the etch-stop layer

$S=\frac{R_{\mathrm{Si}}}{R_{\mathrm{es}}}$

where R_Si is an etch rate of silicon and R_es is an etch rate of the etch-stop. Therefore, a selectivity value where S=1 relates to a case of no etch selectivity.

One method to evaluate etch-stop efficiency is to measure a maximum etch step height across an etch-stop and non-etch-stop boundary. In FIG. 2A, an etch-stop 203A is formed by ion implantation into a portion of a silicon substrate 201A. The etch-stop 203A has a thickness d₁ at time t=0 (i.e., prior to application of any etchant). At time t=t₁ (FIG. 2B) a partially etched silicon substrate 201B is etched to a depth h₁. The etch-stop 203A is now a partially etched etch-stop 203B. The partially etched etch-stop 203B is etched to a thickness of d₂. At time t=t₂ (FIG. 2C), the partially etched etch-stop 203B has been completely etched and a fully etched silicon substrate 201C achieves a maximum etch step height of h₂. An etch rate of the etch-stop 203A (FIG. 2A) is partially dependent upon both an implanted dopant material as well as an implant profile of the dopant employed. From a practical point of view, the maximum etch step is critical since it determines an acceptable thickness variation of the device wafer after grinding and polishing prior to etch back in the BESOI process.

For example, if a maximum etch step is three (3) units, the allowable thickness non-uniformity of the device wafer after the usual mechanical thinning procedure should be less than 1.5 units. The mean etch selectivity, S, can be derived from the effective etch-stop layer thickness d₁ and the maximum etch step h₂ as

$\begin{array}{c}S=\frac{\frac{d_1+h_2}{t}}{\frac{d_1}{t}}\\ \Downarrow \\ S=1+\frac{h_2}{d_1}\end{array}$

where t is the etch time required to reach the maximum etch step height h₂. In the prior example, t₂ is the etch time required to reach the maximum etch step height h₂.

Aqueous alkaline solutions are commonly used anisotropic silicon etchants. Two categories of aqueous alkaline solutions employed are pure inorganic aqueous alkaline solutions such as potassium hydroxide (KOH), sodium hydroxide (NaOH), cesium hydroxide (CsOH), and ammonium hydroxide (NH₄OH) and organic alkaline aqueous solutions such as ethylenediamine-pyrocatechol-water (aqueous EDP), tetramethyl ammonium hydroxide (TMAH or (CH₃)₄NOH)), and hydrazine (H₄N₂). Silicon etch rates of all aqueous alkaline etchants are reduced significantly if silicon is doped with boron in concentrations exceeding 2×10¹⁹ cm⁻³. FIG. 3 graphically indicates a rapid falloff in relative etch rate as a function of boron concentration using EDP as an etchant.

As detailed above, boron (B) is traditionally provided via ion implantation. However, problems arise with using boron as an etch-stop, as boron diffuses readily in pure silicon. Therefore, any etch non-uniformity is increasingly an issue as device design rules continue to decline. A boron etch-stop layer of the prior art is frequently hundreds of nanometers in width (at full-width half-maximum (FWHM)).

The boron etch-stop layer becomes very wide following thermal treatments performed subsequent to the implant, due to boron outdiffusion. One subsequent thermal treatment is a high temperature bonding step of the layer transfer process in BESOI processing. The boron outdiffusion is greatly enhanced by transient enhanced diffusion (TED) due to lattice damage and a large presence of silicon interstitial (S_I) atoms. The lattice damage and the large number of S_I atoms each contribute to anomalously high quantities of diffusion.

Widths of boron in ion implanted profiles can be greater than 200 nm to 300 nm depending on chosen quantities of ion implant energy and dosage. Typically, high dosage requirements also lead to a great deal of concentration-dependent outdiffusion. Therefore, the transferred silicon device layer thickness can exhibit a very wide thickness range since the etch process itself will have a wide profile range over which to stop on the boron-doped layer. The wide layer range poses significant process integration problems, especially when forming a deep (or even a shallow) trench isolation region. The inventor has therefore recognized a need for an extremely thin and robust etch-stop layer having a high etchant selectivity in comparison with silicon.

EXEMPLARY EMBODIMENTS OF THE INVENTION

In an exemplary embodiment, the invention comprises an etch-stop layer having a semiconductor layer having a first surface and a boron layer formed below the first surface of the semiconductor layer. The boron layer has a full-width half-maximum (FWHM) thickness value of less than 100 nanometers. The boron layer is formed by a chemical vapor deposition (CVD) system.

In another exemplary embodiment, the invention comprises a method to fabricate an etch-stop. The method includes flowing a carrier gas over a substrate in a chemical vapor deposition chamber, flowing a silicon precursor gas over the substrate in the deposition chamber and flowing a boron precursor gas over the substrate in the deposition chamber. The boron precursor gas forms a boron layer to act as the etch-stop and forms below a first surface of the substrate. The boron layer is less than 100 nanometers in thickness when measured as a full-width half-maximum (FWHM) value.

In another exemplary embodiment, the invention comprises a method to form an electronic device. The method includes flowing a boron precursor gas over a substrate in a chemical vapor deposition chamber such that the boron precursor gas forms a boron layer thereby acting as an etch-stop layer. The etch-stop layer is formed below a first surface of the substrate and is less than 100 nanometers in thickness when measured as a full-width half-maximum (FWHM) value. One or more dielectric spacers are formed on a surface of the substrate to provide a self-aligning structure. The one or more dielectric spacers are doped with carbon atoms. The carbon atoms are remotely injected from the one or more dielectric spacers by annealing the substrate, thereby allowing the carbon atoms to diffuse into the etch-stop layer.

In another exemplary embodiment, the invention comprises an etch-stop layer comprising a semiconductor substrate having a first surface and a boron layer formed below the first surface of the semiconductor substrate. The boron layer has a full-width half-maximum (FWHM) thickness value of less than 100 nanometers and is formed by a chemical vapor deposition (CVD) system. A germanium profile comprised of germanium atoms is formed substantially within the boron layer and has a germanium fraction of less than one percent to about 20 percent. A carbon profile comprised of carbon atoms is formed substantially within the boron layer and has a concentration within the profile area of between 10¹⁸ and 10²¹ atoms per cubic centimeter.

Disclosed herein is an exemplary fabrication method and a structure resulting therefrom for a boron-doped nanoscale etch-stop. The boron is doped into either a silicon (Si) substrate or film, or a compound semiconductor substrate or film. The compound semiconductor film may be chosen from a Group III-V semiconductor compound such as SiGe, GaAs, or InGaAs. Alternatively, a Group II-VI semiconductor compound may be chosen such as ZnSe, CdSe, or CdTe. The boron-doped nanoscale etch-stop described herein has particular applications in BESOI processing. However, the disclosed boron etch-stop is not limited only to BESOI applications.

A BESOI substrate fabricated in accordance with one exemplary embodiment of the invention has particular applications in low-power and radiation-hardened CMOS devices. Incorporation of embodiments of the invention in various electronic devices simplifies certain fabrication processes, improves scalability of devices, improves sub-threshold slopes, and reduces parasitic capacitances.

In one embodiment, an “as grown” boron profile remains very narrow (e.g., less than 100 nm) by forming an ultra-thin (for example, less than 100 nm) boron profile with chemical vapor deposition (CVD) instead of ion implantation and, in some embodiments, by including germanium and carbon. The boron profile in this case remains very narrow even after significant subsequent thermal treatments up to approximately 1000° C. for about 10 seconds or more. Details of exemplary CVD process steps are outlined below.

Silicon interstitial pairing with boron results in a rate of diffusion that is generally much greater than occurs with boron alone. The intrinsic diffusion coefficient (D_Si) of silicon in silicon is approximately 560 whereas the intrinsic diffusion coefficient of boron (D_B) in silicon is approximately one (1). Incorporating carbon (C) into boron-doped silicon minimizes a Si—B pair formation and thus reduces an overall rate of boron outdiffusion. In a heterojunction bipolar transistor (HBT), for example, the reduced boron outdiffusion results in less spreading of a p-type SiGe base region. Narrow base widths reduce transit times of minority carriers and improve a device shutoff frequency, f_t. Adding carbon and/or germanium, the boron diffusion can be effectively mitigated at temperatures of approximately 1000° C. for 10 seconds or longer.

A device or substrate designer may prefer boron over carbon and/or Ge as an etch-stop, depending on device requirements. For example, a design decision may be driven by a preferred majority carrier type and concentration, or a minority carrier type and concentration. One skilled in the art will recognize that adding carbon to a boron-doped layer will diminish carrier mobility. Consequently, more boron is required to compensate for the diminished carrier effect. A skilled artisan will further recognize that the addition of Ge to form a strained lattice in elemental or compound semiconductors enhances in-plane majority carrier hole mobility, but diminishes in-plane majority carrier electron mobility. Therefore, if boron is added to a carbon and/or germanium-doped lattice, the fabrication process should be completely characterized. The process will be a function of gas flows, temperatures, and pressures.

Further, intrinsic diffusivity of boron (D_B^int), measured in units of an area transfer rate (e.g., cm²/sec), in silicon can be substantial. However, the addition of Ge results in a significant reduction of intrinsic boron diffusivity. (Intrinsic diffusivity of boron refers specifically to the diffusivity of a lone boron atom with no influence from diffusion “enhancing” species such as silicon interstitials as described above). FIG. 4 indicates measured rates of intrinsic boron diffusivity at 800° C. as a function of Ge content, x, in Si_1-xGe_x in an embodiment of the invention.

FIG. 5 is a profile graph 500 in an embodiment of the invention representing data from a secondary-ion mass spectrometry (SIMS) profile of boron diffusion in carbon and Ge-doped silicon. A location of the Ge is illustrated by a lower 501 and an upper 503 vertical line positioned at 50 nm and 85 nm depths, respectively. The boron remains relatively fixed up to temperatures of 1000° C., then diffuses rapidly at higher temperatures (anneal times are ten (10) seconds at each temperature). However, the presence of both carbon and Ge, as introduced under embodiments of the present invention, reduces boron outdiffusion. Depending on concentrations and temperatures involved, the presence of carbon and Ge reduces overall boron diffusion by a factor of ten or more.

With reference to FIG. 6, a graph 600 in an embodiment of the invention indicates boron diffusion depths in SiGe:C:B and a germanium fraction. Boron profiles are displayed in the graph 600 following growth of SiGe:C:B where the subsequent thermal anneals, in this example, relate to bond steps. The graph 600 indicates boron in SiGe with carbon substantially present throughout portions of the structure. Thus, the graph 600 is a complete carbon method for providing a narrow boron profile. A germanium fraction indicates an increased germanium profile substantially within the boron layer. The germanium fraction is within a range from less than one percent to about 20%. As indicated, the profile width for the boron concentration at 1000° C. extends from roughly 62 nm to less than 82 nm. Consequently, the FWHM value is less than about 20 nm. Consequently, the etch-stop is on a nanoscale level. In an exemplary embodiment, the boron etch-stop is formed by chemical vapor deposition (CVD) techniques.

FIG. 7 illustrates an embodiment in which profiles of B, C, and Ge are shown with reference to a placement of outer spacers fabricated in a remote carbon injection method. In the remote injection method, carbon is only present in outer spacer regions as indicated. In a specific exemplary embodiment, the spacer regions are comprised of SiGe. A remote carbon technique, suitable for adding carbon in various embodiments described herein, is disclosed in U.S. patent application Ser. No. 11/166,287 filed Jun. 23, 2005, entitled “Method for Growth and Optimization of Heterojunction Bipolar Film Stacks by Remote Injection,” and commonly assigned to Atmel Corporation, San Jose, Calif. The Ser. No. 11/166,287 application is hereby incorporated by reference in its entirety.

Remote Carbon Injection Technique

Briefly, the remote carbon injection technique entails a carbon implantation or diffusion step in a semiconductor fabrication process to inject carbon atoms into, for example, a semiconductor device layer and surrounding regions. Alternatively, the carbon implantation or diffusion step may be performed into an insulating layer. The carbon is derived from a carbon precursor such as methyl silane (CH₃SiH₃). Carbon precursor injection can be accomplished by techniques such as LPCVD (low pressure chemical vapor deposition), UHCVD (ultra-high vacuum CVD), MBE (molecular beam epitaxy), or ion implantation.

In one embodiment, the carbon injection is followed by a thermal anneal step. The thermal anneal step allows the carbon to diffuse into, for example, a base region of a transistor. Note that, even though a carbon precursor may be injected outside of the base region, the position of the carbon after anneal is within the base region due to an energetically favorable diffusion mechanism. Therefore, remote injection is a means of doping a semiconductor with carbon and provides numerous advantages over conventional fabrication methods, discussed above (e.g., preventing boron outdiffusion thus allowing a higher boron-dopant concentration). Therefore, an injection location and not necessarily a final resting place of carbon following thermal cycles determines a definition of remote carbon injection.

If self-aligning techniques incorporating dielectric spacers are employed, for example, in transistor fabrication, the remote injection can occur during or after growth of a base-emitter spacer (BE) or a base-collector spacer (BC). (Formation of neither the BE nor BC spacer are shown, although such techniques are well-known in the art). Carbon injection may be performed at multiple points during fabrication of either the base, BC, BE, collector, and/or emitter regions. Thermal anneal cycles are then implemented to provide activation energy for the carbon to diffuse from the dielectric spacer into the one or more various semiconductor regions. A final position of carbon after anneal is within the semiconductor through a diffusion mechanism. Advantages of remote carbon injection thus include a reduced boron outdiffusion and a significant reduction in the transistor base resistance.

A skilled artisan will recognize that many other techniques of fabricating an etch-stop layer, other than remote carbon injection, may be utilized. General techniques for implementing these various techniques are described in detail, below. Various permutations of the general etch-stop fabrication method based on the methods disclosed herein may be employed. For example, a boron etch-stop may be fabricated by in-situ boron doping of silicon by CVD in which the silicon contains neither germanium nor carbon. Additionally, a boron etch-stop may be fabricated by in-situ boron doping of SiGe by CVD in which the SiGe contains no carbon. Further, a boron etch-stop may be fabricated by in-situ boron doping of silicon-carbide (SiC) by CVD in which the SiC contains no germanium. In each of these cases, the boron-doped semiconductor could be implanted by an ion implantation or molecular beam epitaxial (MBE) process. Following any implant step, a flash anneal (e.g., from 900° C. to 1200° C. for one (1) second to five (5) seconds) or a laser anneal (e.g., less than a one second pulse) may be used in order to alleviate any ion implantation damage and still maintain a narrow distribution of boron. If boron is either implanted or diffused, carbon and/or germanium may also be added.

CVD Reactor Fabrication Process

Overall, process conditions can vary widely depending upon particular devices fabricated, specific equipment types employed, and various combinations of starting materials. Also, as is known to a skilled artisan, various dopant profiles may be achieved by certain gases being injected simultaneously and/or ramping the gas flow rates. In a specific exemplary embodiment, the process conditions entail flowing hydrogen (H₂) as a carrier gas in a chemical vapor deposition (CVD) system at a flow rate between 5 standard liters per minute (slpm) and 100 slpm. Alternatively, inert gases such as nitrogen (N₂), argon (Ar), helium (He), xenon (Xe), and fluorine (F₂) are all suitable carrier gases. Silane (SiH₄) may be used as a silicon precursor gas, flowing between 5 standard cubic centimeters per minute (sccm) and 1000 sccm. Alternatively, disilane (Si₂H₆) or another silicon precursor gas, may be used in place of silane. Disilane deposits silicon at a faster rate and lower temperature than silane.

Diborane (B₂H₆) may be used as a boron precursor gas, flowing at between 5 sccm and 1000 sccm. Additionally, boron trichloride (BCl₃) or any other boron precursor gas may be used in place of diborane. Methyl silane (CH₃SiH₃), or another carbon precursor gas, flowing at between 5 sccm and 1000 sccm may be employed as the carbon precursor. Germanium tetrahydride (GeH₄) or another germanium precursor gas flowing at between 5 sccm and 1000 sccm may be employed as the germanium precursor gas.

For a low pressure CVD (LPCVD) reactor, growth temperatures may be in an exemplary range of 550° C. to 750° C. with processing pressures from 1 Torr to 100 Torr.

CONCLUSION

In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, although process steps and techniques are shown and described in detail, a skilled artisan will recognize that other techniques and methods may be utilized which are still included within a scope of the appended claims. For example, there are frequently several techniques used for depositing a film layer (e.g., chemical vapor deposition, plasma-enhanced vapor deposition, epitaxy, atomic layer deposition, etc.). Although not all techniques are amenable to all film types described herein, one skilled in the art will recognize that multiple methods for depositing a given layer and/or film type may be used.

Additionally, many industries allied with the semiconductor industry could make use of the remote carbon injection technique. For example, a thin-film head (TFH) process in the data storage industry or an active matrix liquid crystal display (AMLCD) in the flat panel display industry could readily make use of the processes and techniques described herein. The term “semiconductor” should be recognized as including the aforementioned and related industries. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. An integrated circuit structure comprising a boron etch-stop layer located on a surface of the integrated circuit structure and having a full-width half-maximum (FWHM) thickness value less than 100 nanometers, wherein the boron etch-stop layer is substantially free of germanium and carbon.

2. The integrated circuit structure of claim 1 comprising a substrate selected from silicon, silicon-germanium, and silicon carbide.

3. The integrated circuit structure of claim 1 comprising a film selected from epitaxial silicon, epitaxial silicon-carbide, and epitaxial silicon-germanium.

4. The integrated circuit structure of claim 1 comprising a deposited silicon film.

5. The integrated circuit structure of claim 1 wherein the boron etch-stop layer is less than about 20 nanometers in thickness when measured as a FWHM value.

6. (canceled)

7. The integrated circuit structure of claim 5 further comprising a carbon concentration of between 1018 and 1021 atoms per cubic centimeter in the boron etch-stop layer.

8. The integrated circuit structure of claim 5 further comprising a germanium concentration fraction of less than one percent to about 20 percent in the boron etch-stop layer.

9. The integrated circuit structure of claim 5 comprising a silicon-based semiconductor structure.

10. The integrated circuit structure of claim 9 wherein the silicon-based semiconductor structure is a compound semiconductor film selected from a Group II through Group VI semiconductor compound and combinations thereof.

11. The integrated circuit structure of claim 10 wherein the semiconductor compound is selected from SiGe, GaAs, InGaAs, ZnSe, CdSe, CdTe, and combinations thereof.

12. An electronic device comprising: an integrated circuit structure; anda boron etch-stop layer located on the integrated circuit structure and having a full-width half-maximum (FWHM) thickness value of less than 20 nanometers.

13. The electronic device of claim 12 comprising a heterojunction bipolar transistor.

14. The electronic device of claim 12 comprising a bond-and-etch-back silicon-on-insulator (BESOI) substrate.

15. The electronic device of claim 14 wherein the BESOI substrate is a complementary metal-oxide semiconductor (CMOS) device.

16. The electronic device of claim 12 further comprising a carbon concentration of between 1018 and 1021 atoms per cubic centimeter in the boron etch-stop layer.

17. The electronic device of claim 12 further comprising a germanium concentration fraction of less than one percent to about 20 percent in the boron etch-stop layer.

18. The electronic device of claim 12 further comprising one or more carbon-doped spacers on the electronic device to provide a source of carbon atoms for the etch-stop layer.

19. A system comprising: an integrated circuit structure;a boron etch-stop layer located on a surface of the integrated circuit structure and having a full-width half-maximum (FWHM) thickness value of less than 20 nanometers; anda liquid crystal display or data storage coupled to the integrated circuit structure.

20. The system of claim 19 wherein the boron etch-stop layer further comprises an additional elemental concentration selected from a carbon concentration of between 1018 and 1021 atoms per cubic centimeter, a germanium concentration fraction of less than one percent to about 20 percent, and combinations thereof.

21. The system of claim 20 wherein the integrated circuit structure is a silicon-based semiconductor structure.

22. A method comprising: flowing a carrier gas over an integrated circuit structure in a chemical vapor deposition chamber;flowing a silicon precursor gas over the integrated circuit structure in the deposition chamber; andflowing a boron precursor gas over the integrated circuit structure in the deposition chamber to form a boron etch-stop layer on the integrated circuit structure which is less than 100 nanometers in thickness when measured as a full-width half-maximum (FWHM) value.

23. The method of claim 22 wherein the carrier gas is selected from hydrogen, nitrogen, argon, helium, xenon, fluorine, and combinations thereof.

24. The method of claim 23 wherein the boron etch-stop layer is less than about 20 nanometers in thickness when measured as a FWHM value.

25. The method of claim 22 wherein the silicon precursor gas is silane or disilane flowing at between five (5) standard cubic centimeters per minute (sccm) and 1000 sccm.

26. The method of claim 22 wherein the boron precursor gas is diborane or boron trichloride flowing at between five (5) and 1000 sccm.

27. The method of claim 22 further comprising: flowing a carbon precursor gas over the integrated circuit structure; andflowing a germanium precursor gas over the integrated circuit structure to limit a diffusivity value of boron atoms within the boron etch-stop layer.

28. The method of claim 27 wherein the carbon precursor gas is methyl silane flowing at between five (5) and 1000 sccm and the germanium precursor gas is germanium tetrahydride flowing at between five (5) and 1000 sccm.

29. The method of claim 27 wherein temperatures in the chemical vapor deposition chamber are between 550 and 750° C. and pressures are between one (1) and 100 Torr, and the integrated circuit structure is a bond-and-etch-back silicon-on-insulator (BESOI) wafer comprised of a silicon device wafer and a silicon handle wafer, wherein the silicon device wafer includes a first silicon layer covered by the boron etch-stop layer and a second silicon layer, and the silicon device wafer includes a lower silicon dioxide layer covered by a silicon substrate layer and an upper silicon dioxide layer, wherein the method further comprises: diffusion bonding the silicon device wafer to the silicon handle wafer to form a BESOI wafer having a diffusion bond;thermally annealing the BESOI wafer to strengthen the diffusion bond; andthinning the BESOI wafer to remove most of the second silicon layer.

30. The method of claim 29 wherein the thinning step is followed by an etching step to remove a remaining portion of the second silicon layer up to the boron etch-stop layer.

31. The method of claim 29 wherein the thinning step is followed by a hydrogen implantation and separation step.

32. The method of claim 29 wherein the annealing occurs at approximately 1000° C. for about 10 seconds or more.