The present disclosure relates to the fabrication of integrated circuits, and in particular, to the fabrication of vias.
Modern electronic systems are often composed of integrated circuits (ICs) fabricated on small rectangular portions of flat wafers. The small rectangular portions of the wafers are commonly known as dies and as chips. Individual components of a given integrated circuit are formed by the addition of successive thin planer layers of various materials and the subsequent removal of portions of the added layers which results in the formation of patterned layers on the wafers. Selected areas of particular patterned layers are then coupled together conductively to form the components and the circuits.
An important part of this process is the creation of vias or openings between one or more upper layers and one or more lower layers to provide paths by which elements of the upper and lower layers can be conductively interconnected. Vias are formed between the upper and lower layers by the removal of selected areas of layers intermediate between the upper and lower layers.
There is a continuing trend toward manufacturing integrated circuits with higher component densities. This down-scaling of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher cost efficiency in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer. Smaller feature sizes of necessity mean smaller via sizes.
Example embodiments of the present disclosure will be described below with reference to the included drawings such that like reference numerals refer to like elements and in which:
For simplicity and clarity of illustration, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. Numerous details are set forth to provide an understanding of the illustrative embodiments described herein. The embodiments may be practiced without these details. In other instances, well-known methods, procedures, and components have not been described in detail to avoid obscuring the disclosed embodiments. The description is not to be considered as limited to the scope of the exemplary embodiments shown and described herein.
The terms “a” or “an”, as used herein, are defined as one or more than one. The term “plurality”, as used herein, is defined as two or more than two. The term “another”, as used herein, is defined as at least a second or more. The terms “including” and/or “having”, as used herein, are defined as comprising (i.e., open language). The term “coupled”, as used herein, is defined as connected, although not necessarily directly, and not necessarily mechanically. The term “or” as used herein is to be interpreted as an inclusive or meaning any one or any combination. Therefore, “A, B or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B and C”. An exception to this definition will occur only when a combination of elements, functions, steps or acts are in some way inherently mutually exclusive.
Reference throughout this document to “one embodiment”, “certain embodiments”, “an embodiment”, “an example”, “an implementation”, “an example” or similar terms means that a particular feature, structure, or characteristic described in connection with the embodiment, example or implementation is included in at least one embodiment, example or implementation of the present invention. Thus, the appearances of such phrases or in various places throughout this specification are not necessarily all referring to the same embodiment, example or implementation. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, examples or implementations without limitation.
Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”
As shown in the drawings for purposes of illustration, novel techniques are disclosed herein for integrated circuit via structures and methods for the fabrication of integrated circuit via structures. Via structure patterning schemes are disclosed which can be used in a single or a double via structure patterning process.
Previously an organic planarization layer (OPL) has been used as a via mask in preparation for final metal deposition in typical trench processes. As taught herein, a coating layer is inserted beneath the organic planarization layer. This coating layer is a hard layer the material of which could be, but is not limited to, an oxide. It is a sacrificial layer during via etch and subsequent trench etching and prevents dielectric damage during organic planarization layer strip removal. It also enables the use of a thinner titanium nitride (TiN) hard mask which needs to be eventually removed or faceted for non-void post-etch metal filling in via and trench locations. Also, the titanium nitride will experience less exposure to cumulative etching and can have less corner rounding and improvement in self-aligned critical dimension control. Via profile bowing may also be improved as a result of less dielectric damage generated during the organic planarization layer strip process.
The techniques disclosed can result in improved self aligned vias In addition, associated insulating layers have ultra low dielectric constants which can result in improvements in resistances and capacitances between various layers.
The material of the base layer 105 could be, but is not limited to, an oxide, an ultra low dielectric constant (ULK) oxide, or Tetraethyl orthosilicate (TEOS); the material of the conductive layer 110 could be, but is not limited to, copper; the material of the protective layer 115 could be, but is not limited to, a nitride, cyclique nitride or cobalt nitride; the material of the dielectric layer 125 could be, but is not limited to, an oxide, an ultra low dielectric constant (ULK) oxide, or Tetraethyl orthosilicate (TEOS); the material of the sacrificial adhesive layer 130 could be, but is not limited to, an oxide or Tetraethyl orthosilicate; the material of the hard mask layer 135 could be, but is not limited to, titanium nitride (TiN); and the material of the coating layer 145 could be, but is not limited to, a conformal deposition of an oxide, a nitride, or boron nitride such as, for example, a low temperature oxide (LTO) deposited by atomic-layer deposition (ADL) or a plasma-enhanced atomic layer deposition (PEALD) of silicon dioxide. The initial via pattern layer 160 can, in various optional implementations, comprise one or more sub-layers, the details of which will be discussed in connection with the appropriate subsequent figures.
The base layer 105 is used as a dielectric layer to avoid shorts between other conductive traces and the via; the conductive layer 110 is used to electrically interconnect various elements of the integrated circuit structure 100; the dielectric layer 125 is used to avoid shorts between the other conductive traces and the via; the sacrificial adhesive layer 130 provides adhesion between the dielectric layer 125 and the hard mask layer 135; and the coating layer 145 provides the required shrink for the via and aids to preserve the dielectric 125 from being exposed to a plasma source of damage.
In block 1020, an initial via pattern layer 160 overlays the coating layer 145. The initial via pattern layer 160 comprises a lower initial layer 165, an upper initial layer 170, and a photoresist layer 175. Processing techniques and materials for representative implementations are disclosed above. Block 1020 then transfers control to block 1030.
In block 1030, one or more initial openings 260 are created in the initial via pattern layer 160. Processing techniques and materials for representative implementations are disclosed above. Block 1030 then transfers control to block 1040.
In block 1040, the photoresist layer 175 and the upper initial layer 170 are removed from the integrated circuit structure 100. Processing techniques and materials for representative implementations are disclosed above. Processing techniques and materials for representative implementations are disclosed above. Block 1040 then transfers control to block 1050.
In block 1050, the pattern of the one or more initial openings 260 is etched into the coating layer 145 and through openings in the hard mask layer 135. Processing techniques and materials for representative implementations are disclosed above. Processing techniques and materials for representative implementations are disclosed above. Block 1050 then transfers control to block 1060.
In block 1060, the one or more vias are etched through the sacrificial adhesive layer 130. Processing techniques and materials for representative implementations are disclosed above. Processing techniques and materials for representative implementations are disclosed above. Block 1060 then transfers control to block 1070.
In block 1070, the coating layer 145 is removed. Processing techniques and materials for representative implementations are disclosed above. Processing techniques and materials for representative implementations are disclosed above. Block 1070 then transfers control to block 1080.
In block 1080, the one or more vias are etched through the dielectric layer 125 and through the protective layer 115. Processing techniques and materials for representative implementations are disclosed above. Processing techniques and materials for representative implementations are disclosed above. Block 1080 then terminates the process.
In block 1120, a coating layer 145 overlays the oxide hard mask layer 140. Processing techniques and materials for representative implementations are disclosed above. Block 1120 then transfers control to block 1130.
In block 1130, an initial via pattern layer 160 overlays the coating layer 145. The initial via pattern layer 160 comprises a lower initial layer 165, an upper initial layer 170, and a photoresist layer 175. Processing techniques and materials for representative implementations are disclosed above. Block 1130 then transfers control to block 1140.
In block 1140, one or more initial openings 260 are created in the initial via pattern layer 160. The initial via pattern layer 160 could in this step comprise a top layer 185 having one or more multi-patterned via openings 360 etched into it or could be single patterned. Processing techniques and materials for representative implementations are disclosed above. Block 1140 then transfers control to block 1150.
In block 1150, the photoresist layer 175 and the upper initial layer 170 are removed from the integrated circuit structure 100. Processing techniques and materials for representative implementations are disclosed above. Processing techniques and materials for representative implementations are disclosed above. Block 1150 then transfers control to block 1160.
In block 1160, the pattern of the one or more initial openings 260 is etched into the coating layer 145 and through openings in the hard mask layer 135. Processing techniques and materials for representative implementations are disclosed above. Processing techniques and materials for representative implementations are disclosed above. Block 1160 then transfers control to block 1170.
In block 1170, the one or more vias are etched through the sacrificial adhesive layer 130. Processing techniques and materials for representative implementations are disclosed above. Processing techniques and materials for representative implementations are disclosed above. Block 1170 then transfers control to block 1180.
In block 1180, the coating layer 145 is removed. Processing techniques and materials for representative implementations are disclosed above. Processing techniques and materials for representative implementations are disclosed above. Block 1180 then transfers control to block 1190.
In block 1190, the one or more vias are etched through the dielectric layer 125 and through the protective layer 115. Processing techniques and materials for representative implementations are disclosed above. Processing techniques and materials for representative implementations are disclosed above. Block 1190 then terminates the process.
In a representative embodiment, a method 1000 for creating one or more vias in an integrated circuit structure 100 is disclosed. The method 1000 comprises depositing a coating layer 145 over a hard mask layer 135 on the integrated circuit structure 100; locating an initial via pattern layer 160 over the coating layer 145; and etching the pattern of the one or more initial openings 260 in the coating layer 145 and through openings in the hard mask layer 135. The coating layer 145 is a conformal deposition of an oxide, a boron nitride, or other nitride. The initial via pattern layer 160 has one or more initial openings 260 located therein.
In another representative embodiment, another method 1100 for creating one or more vias in an integrated circuit structure 100 is disclosed. The method 1100 comprises depositing an oxide hard mask layer 140 over a hard mask layer 135 on the integrated circuit structure 100; depositing a coating layer 145 over the oxide hard mask layer 140 on the integrated circuit structure 100; locating an initial via pattern layer 160 over the coating layer 145; and etching the pattern of the initial openings 260 in the coating layer 145 extending through openings in the oxide hard mask layer 140 and through openings in the hard mask layer 135. The coating layer 145 is a conformal deposition of an oxide, a boron nitride, or other nitride. The initial via pattern layer 160 has one or more initial openings 260.
In still another representative embodiment, an integrated circuit structure 100 is disclosed. The integrated circuit structure 100 comprises a coating layer 145 located over a hard mask layer 135 on the integrated circuit structure 100; and an initial via pattern layer 160 located over the coating layer 145. The coating layer 145 is a conformal deposition of an oxide, a boron nitride, or other nitride. An initial via pattern layer 160 has one or more initial openings 260 located therein, and the pattern of the one or more initial openings 260 was etched into the coating layer 145 and through openings in the hard mask layer.
The embodiments of the present disclosure described above are intended to be merely exemplary. It will be appreciated by those of skill in the art that alterations, modifications and variations to the illustrative embodiments disclosed herein may be made without departing from the scope of the present disclosure. Moreover, selected features from one or more of the above-described exemplary embodiments may be combined to create alternative embodiments not explicitly shown and described herein.
The present disclosure may be embodied in other specific forms without departing from its spirit or essential characteristics. The described exemplary embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the disclosure is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.