The technical field generally relates to integrated circuits and methods for producing integrated circuits, and more particularly relates to integrated circuits with transistors overlying a bowed substrate and methods for producing the same.
The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate. Spaced-apart source and drain regions are on opposite sides of a channel in the substrate between which a current can flow. A gate insulator is disposed between the gate electrode and the channel to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through the channel in the substrate underlying the gate electrode between the source and drain regions.
In many cases, a FET is positioned between two shallow trench isolation (STI) insulators, and the device width of the entire FET is the distance between the two STI insulators. Manufacturing processes include a certain amount of variability, so the distance between STI insulators does vary somewhat from one FET to another. The variability of the FET is determined by the variations of the distance between two STI insulators (ΔW, or width variation) divided by the total device width between the two STI insulators (W, or width). The device width between two STI insulators is effectively the distance along the surface of the substrate laying therebetween, and that substrate surface is flat in traditional planar FETs. The variability of FETs can be reduced by maintaining the ΔW between two STI insulators due to manufacturing variability, and increasing the device width or the effective distance between the two STI insulators. However, decreasing the size of integrated circuits is a high priority, so simply producing wider FETs is not desirable.
Accordingly, it is desirable to provide systems and methods for producing a FET with an increased effective device width between adjacent STI insulators. In addition, it is desirable to provide a FET with decreased variability without utilizing more of the substrate surface area. Furthermore, other desirable features and characteristics of the present embodiment will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.
Integrated circuits and methods of manufacturing the same are provided. In an exemplary embodiment, a method is provided for producing an integrated circuit. The method includes forming a first and second STI insulator in a substrate, and bowing a substrate surface between the first and second STI insulators. A transistor is formed between the first and second STI insulators.
In a different embodiment, a method is provided for manufacturing an integrated circuit. The method includes forming a first and second STI insulator in a substrate, where a device width is the distance between the first and second STI insulators measured along a substrate surface. The device width is increased after forming the first and second STI insulators, and a transistor is formed between the first and second STI insulators.
An integrated circuit is provided in another embodiment. The integrated circuit includes a substrate with a substrate surface. A first and second STI insulator are positioned within the substrate, where the substrate has a bowed shape between the first and second STI insulators. A transistor is positioned between the first and second STI insulators.
The present embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
The following detailed description is merely exemplary in nature and is not intended to limit the various embodiments or the application and uses thereof. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description.
An integrated circuit begins with the production of first and second STI insulators, and the STI insulators are recessed to below a substrate surface. The substrate surface between the first and second STI insulators is then bowed. This increases the effective device width, because the distance between the STI insulators along a bowed surface is greater than the straight line distance between the STI insulators. The STI insulators are formed using standard techniques, so the variation in the distance between the STI insulators is consistent with traditional approaches. The substrate surface can be bowed using different techniques. For example, a cap formed by epitaxial growth can extend the substrate between the STI insulators, where the cap is grown in a bowed shape, such as by the epitaxial loading effect. In an alternate embodiment, the substrate surface is melted, such as with a gas cluster ion beam, so the substrate surface reflows and forms a bowed shape. A field effect transistor (FET) is then produced on the bowed substrate.
Referring to the exemplary embodiment illustrated in
Reference is made to the exemplary embodiment illustrated in
Reference is made to the exemplary embodiment in
The cap 34 extends the crystalline structure of the substrate 12, but the first and second STI insulators 20, 22 are not crystalline so the cap 34 does not grow from them. As such, the cap 34 forms over the substrate 12 and along the exposed vertical portion of the substrate 12 in the first and second trenches 14, 16. The cap 34 is formed of substrate material, which may be the same or different than the material in the substrate 12 below the cap 34, so the cap 34 becomes a portion of the substrate 12 as it is formed. The top of the cap 34 becomes the substrate surface 32, because the cap 34 is part of the substrate 12. The cap 34 is not constrained in an enclosed space, so the cap 34 does not have significant crystal lattice strain even in embodiments where the cap 34 includes compounds different than the substrate, such as a substrate 12 underlying the cap 34 with about 99 or more mole percent silicon and a cap 34 with about 25 mole percent germanium.
The cap 34 is formed into a bow shape during the epitaxial growth. Not to be bound by theory, but the cap 34 may form a bowed shape due to the epitaxial loading effect. The cap 34 may extend into the first and second trenches 14, 16 somewhat, but most of the material of the cap 34 is positioned overlying the substrate 12 between the first and second STI insulators 20, 22. The bowed cap 34 has a bow length illustrated by the doubled headed arrow 40, and a bow height illustrated by the double headed arrow 42. In an exemplary embodiment, the bow height 42 is about 10 to about 40 percent of the bow length 40, or the bow height 42 is about 20 to about 30 percent of the bow length 40 in another embodiment. For example, the bow length 40 may be about 80 nanometers, and the bow height 42 may be about 20 nanometers in an embodiment where the bow height 42 is about 25 percent of the bow length 40. The bowed shape of the substrate surface 32 increases the device width 30, because the distance between the first and second STI insulators 20, 22 along the bowed substrate surface 32 is greater than the straight line distance between the first and second STI insulators 20, 22.
Referring to the exemplary embodiment in
Reference is made to the exemplary embodiment in
In an exemplary embodiment, the substrate surface 32 melts and reflows into a bow shape, as mentioned above. The bow shape may be due to surface tension or other effects, or it may result from some of the substrate material near the first and second trenches 14, 16 becoming dislodged. The bowed shape increases the device width 30 after the formation of the first and second STI insulators 20, 22, as described above. A transistor 50 is then formed between the first and second STI insulators 20, 22, as described above and as illustrated in
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the application in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing one or more embodiments, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope, as set forth in the appended claims.