Patent Application
20060222975
This invention generally relates to lithographic processes and more particularly to resist baking and development processes in an integrated circuit manufacturing process including an integrated temperature control and optical metrology system for achieving dynamic and real-time adjustments in a resist baking process to achieve improved critical dimension (CD) and critical dimension uniformity (CDU) control in a lithography process including increased wafer throughput.
Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been the increasingly stringent requirements placed on the accuracy and resolution of lithographic patterning processes. Various methods have been implemented to increase the critical dimension (CD) resolution performance of resists and to increase within wafer critical dimension uniformity (CDU) in lithographic patterning processes.
Typically a resist layer is applied to a semiconductor wafer process surface, followed by exposure of the resist through a mask. A baking process, referred to as post-exposure bake (PEB) is then carried out to alter physical properties of the resist including initiating chemical reactions in the resist to render the resist soluble in a subsequent development process. The temperature and time period of the PEB process can be critical to CD control of subsequently developed photoresist profiles. Temperatures must typically be controlled to within about 0.1° C. to prevent undesirable CD variations in the subsequently developed resist to form a circuitry pattern.
As semiconductor device CD's are scaled down to below about 100 nm, small nanometer sized variations in a resist profile make up an increasingly larger percentage of the CD, thereby increasing the level of CD error. For example, two parameters known as bias and tolerance are frequently used to define CD requirements in the semiconductor processing art. CD Bias is the difference in lateral dimension between the patterned image and the mask image. CD uniformity is a measure of the statistical distribution of CD bias values (e.g., 3×sigma) that characterizes the uniformity of patterning. For example, in etching polysilicon gate structures, the gate length determines the channel length and the acceptable electronic functioning of a transistor making gate CD uniformity critical in the gate formation process. Nonuniform resist patterning may adversely affect the manufacturing process as well as the reliability of integrated circuits in several ways. For example, unacceptable within-wafer CD variations require that the lithographic process be repeated, which lowers wafer throughput and increases production costs.
In prior art processes, following resist development, an after development inspection process (ADI) may be carried out in-line by scanning electron microscope (SEM) or may be carried out off-line by transmission electron microscopy (TEM). For example SEM processes obtain surface CD information, but are not able to obtain profiles of developed resist patterns. TEM, on the other hand, requires time consuming and sample destructive preparation processes to prepare a sample including a profile (cross-section) of the resist in order to ascertain the efficacy of a PEB and/or development process with respect to resist profiles.
Another limitation in prior art processes, is that once a deficiency in a PEB process has been determined, time consuming calibration and adjustment of a heating plate is required to alter the PEB process temperature, frequently involving a trial and error approach. For example, a process wafer throughput flow is frequently interrupted to carryout iterative PEB temperature adjustments on a test wafer followed by an ADI process, and so forth, until acceptable resist CD is achieved. Unfortunately, several variables may make previously determined PEB process temperature profiles unacceptable in producing desired CD's, including environmental variables, hardware variables, and variables specific to the line density and pitch of a particular circuitry pattern. As such, achieving acceptable resist pattern CD's is frequently time consuming and costly, requiring frequent reworking of process wafers.
Thus, there is a need in the integrated circuit manufacturing art for an improved resist metrology process as well as an improved method for adjusting lithography process variables to quickly and accurately determine process wafer resist profiles and accordingly adjust lithography process variables to improve CD and within wafer CD uniformity while improving a wafer throughput.
It is therefore an object of the invention to provide an improved resist metrology process as well as an improved method for adjusting lithography process variables to quickly and accurately determine process wafer resist profiles and accordingly adjust lithography process variables to improve CD and within wafer CD uniformity while improving a wafer throughput, in addition to overcoming other shortcomings and deficiencies of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method and apparatus for improving a yield and throughput of a lithographic process track.
In a first embodiment, the method includes providing a first resist layer on a first process wafer; forming a first resist pattern in the first resist layer including a heating process according to a first temperature profile wherein the heating process comprises a plurality of temperature controllable heating zones; producing and collecting scattered light spectra from the first resist pattern; processing the scattered light spectrum to obtain 3-dimensional information including first resist pattern critical dimensions; determining a second temperature profile for performing the heating process to achieve targeted resist pattern critical dimensions including a second resist pattern on a second process wafer; and, forming the second resist pattern dimensions including the heating process according to the second temperature profile.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention, which are further described below in conjunction with the accompanying Figures.
Although the system and method of the present invention are explained in exemplary implementation with respect to achieving CD accuracy and uniformity of a patterned resist layer in an integrated circuit manufacturing process, it will be appreciated that the invention may be adapted for application to micro-engineered machine (MEM) processes or other processes where resist patterns with critical dimensions (CD's) of less than about 0.25 microns are formed for subsequent dry etching according to the patterned resist layer.
Referring to
In an important aspect of the invention, an optical metrology station 16 including a conventional spectrometer for collecting spectra of scattered light in digital format from the resist, as further explained below, is provided downstream of the development station 12D or downstream of the rinse/dry station 12E. For example, the optical metrology station 16 may include conventional spectrometers for probing, detecting, and collecting scattered light such as ellipsometers or reflectometers as are known in the art. A conventional controller 18, preferably including one or more dedicated processors for processing digital information according to processing algorithms as well as conventional storage media, is provided in communication (e.g., controller command and instrument response) with the optical metrology station 16 (spectrometer) e.g., communication line 18A. The collected spectra may be received, stored, and processed in response to controller 18 commands. It will be appreciated the controller may be incorporated in the optical metrology station 16, and that the optical metrology station 16 may be incorporated into the lithographic process track. Both wire and wireless communication will be understood to be included in the term “communication” as used herein and as a represented by communication lines, e.g., 18A.
According to an important aspect of the invention communication between the controller 18, e.g., and the heating stations, e.g., 12B and 12C, preferably including at least the PEB station 12C, is provided e.g., via communication line 18B. It will be appreciated that more heating stations may be provided in communication with the controller 18 for sending a temperature status and responding to heating zone temperature setting commands. In another aspect of the invention the heating stations e.g., 12B and 12C, are preferably heating plates that have a plurality of heating cells including conventional heating elements and sensors, e.g. resistive heating elements and associated thermocouples or RTD sensors, associated with one or more heating cells. The heating cells may be selected and grouped by the controller 18 according to programmed instructions into clusters of any geometry to form heating plate heating zones.
For example referring to
According to an embodiment of the invention, a plurality of the heating cells e.g., 22A and 22B may be selected or grouped into any geometry of adjacent heating zones as shown below in
Referring to
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In an important aspect of the invention, the scattered light spectra, collected in digital form from the patterned resist layer (resist pattern), is then passed to the controller 16 for processing and analysis, preferably including dedicated processors for carrying out the processing functions. An ADI diffraction analysis process, referred to herein as optical digital profilometry (ODP), is then preferably undertaken to render the collected spectroscopic digital data (spectra) into 3-dimensional digital information including information representing a 3-dimensional profile of the sampled portion of the resist pattern as a function of resist pattern depth. It will be appreciated that the controller 16 may include incorporated or separate conventional graphical display means and graphical display software for rendering the 3-dimensional profile information of the resist pattern into graphical form with respect to any set of chosen set of reference coordinates. IN an important aspect of the invention, the ODP analysis process preferably includes rigorous wave coupled analysis (RCWA) as is known in the art.
For example, in one embodiment, a test process wafer including patterned adjacent resist lines having a predetermined linewidth and pitch to form a resist grating pattern is first formed by passing the test process wafer through the lithographic track including PEB and development processes to form a resist pattern, referred to herein as a resist grating. One or more scattered spectra are then collected from the resist grating and subjected to diffraction analysis, preferably using RCWA computing methods including simultaneously solving a system of differential equations with appropriate boundary conditions. Preferably, no simplifying or approximating assumptions, for example with respect to boundary conditions, are made prior the performing the RCWA computing algorithm.
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Moreover, the ADI ODP analysis of the present invention advantageously provides 3-dimensional information concerning the dimensions of the patterned resist profile. For example, the ADI ODP analysis is able to determine a CD at an uppermost portion or the resist layer, similar to SEM analysis, but additionally includes information on the resist profile as a function of resist layer depth, for example including CD information on the sidewall portions of the developed resist pattern.
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It will be appreciated the heating zones of the heating plate may be advantageously created ‘virtually’ by appropriate commands from the controller 18, for example using relational database software, to cluster or map selected heating cells e.g., 22A, 22B and heating elements into heating zones (e.g., 1, 31A, etc.) the number of heating zones only limited by the size of individual heating cells. Representative spectra is collected in each of the process wafer heating zones and stored, for example in a relational database including calculated CD parameters such as CD bias, CD tolerance, 3×sigma, and mean CD over selected measurement points of a wafer surface area as well as the temperatures of the corresponding heating plate heating zones for the PEB process for that particular process or test wafer. A model function relationship between temperature variation of selected heating plate heating zone temperatures and corresponding CD variation of the resist pattern as a function of the temperature variation is then derived by conventional statistical methods including function fitting relationships such as linear and non-linear least squares analysis.
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Following obtaining a model functional relationship between heating plate heating zone temperatures and resist CD, the model functional relationship is preferably used to determine a desired temperature profile to obtain desired CD parameters in a subsequent heating process (e.g., PEB) of production process wafers. For example, following lithographic track processing of a production line process wafer including PEB and development to form a resist pattern, the wafer is passed to the optical metrology station 16 and scattering spectra collected and analyzed according to the ADI ODP method to obtain CD profile parameters in 3-dimensions (e.g., CD bias, tolerance, and/or uniformity) including at least a top portion and sidewall portions of the resist pattern. The CD profile information is then analyzed to determine a deviation from a desired CD result by applying (comparing) the previously developed model functional relationship to the CD profile to determine a required (desired) temperature profile (temperatures of the corresponding heating cells/zones) in processing an upstream process wafer in the PEB process to achieve a desired CD profile.
The desired temperature profile is then communicated to the heating plate including heating cells and/or zones to carry out the next heating process (e.g., PEB process). It will be appreciated that the ADI ODP analysis, as well as determining a desired temperature profile and communication to the heating plate at the PEB station, may be automated functions, e.g., by having controller 18 execute programmed instructions as well as communicating with the optical metrology station 16, the PEB station 12C, and the lithographic process track including process wafer selection and transfer functions.
It will be appreciated that a database including a second functional relationship between individual heating cell temperatures and heating zone temperatures may be used to achieve a desired temperature in a heating plate heating zone. For example, a calibration process for heating zone temperature control may be periodically carried out by known methods. Advantageously, however, the method and integrated optical metrology system of the present invention minimizes the need for periodically individually calibrating each heating cell to an absolute temperature to achieve acceptable resist CD control.
For example, since relative changes in resist CD with respect to relative changes in temperature may be readily ascertained and modeled by the model functional relationship, the absolute temperature of the heating cell/zone need not be known. To account for hardware, environmental or lithography process changes, however, the relative changes in temperature of the heating cell/zone are preferably periodically correlated with resist CD variation to update the model functional relationships. In addition, several different model functional relationships may be obtained and stored for use in a particular production line process beforehand, for example where different circuitry patterns having various linewidth, pitch, and density are found to alter the model functional relationship. In addition, it will be appreciated that different model functional relationships may be desirable and necessary when changes in the lithographic track process occur including the type of resist used, the soft-bake temperature and time, PEB temperature and time, as well as changes in the development process, all of which may affect a resist pattern CD variation.
For example, by having a model functional relationship between heating zone temperatures and resist pattern CD parameters, real-time adjustments to the PEB process may be made during the in-line production process to improve resist pattern CD parameters thereby increasing throughput, minimizing downtime for calibration, and increasing wafer yield. For example, the ADI ODP analysis is periodically carried out in-line on production wafers, more preferably, each production wafer is inspected by the ADI ODP analysis and selected CD parameters are compared with the model functional relationship to determine a required heating cell/zone adjustment in real-time and applied to production wafers upstream of the PEB process. Advantageously, unacceptable variations in resist CD may be quickly spotted and corrected in real time by in-line heating zone adjustment to achieve a desired resist CD parameter.
In addition, the lithographic track process may be programmed for interruption by automatic triggers following ADI ODP analysis where it is determined that resist CD parameters are outside a pre-determined acceptance window. In this case, upon triggering an unacceptable result, the lithographic track process may automatically (according to programmed instructions) switched to processing test wafers to perform a calibration process with a resist grating as outlined above to determine a new model functional relationship. Upon obtaining a new model functional relationship, the lithographic track process may be then automatically switched to the processing of production wafers. It will be appreciated that the entire process may advantageously be automated including ADI ODP analysis, production process interruption for calibration, and resumption of the production process.
For example, referring to
Thus, an integrated optical metrology and lithographic system has been present as well as a method for carrying out an integrated lithographic and optical ADI process to improve resist CD parameters as well as improve wafer throughput and yield. Advantageously, the ADI ODP method can be easily integrated in-line in a conventional lithographic track process and advantageously provides 3-dimensional CD information on a patterned resist layer with at least the same resolution as prior art methods providing 2-dimensional CD information, e.g., SEM, TEM. Moreover, the ADI ODP process can obtain 3-dimensional information non-destructively and more quickly compared to prior art processes e.g., SEM, TEM. Advantageously, the ADI ODP analysis can be carried out with few or no simplifying assumptions in a period of time acceptable for an in-line ADI wafer-by-wafer process to improve wafer yield, not practicable with prior art processes. Further, by integrating the ADI ODP process with selectably temperature controllable heating plate heating zones in a PEB process, PEB temperature adjustments to achieve desired resist pattern CD's can be performed in-line and in real time to be applied prior to upstream process wafers thereby increasing wafer throughput and yield. Moreover, the integrated ADI ODP method makes the need for individual absolute temperature calibration of temperature sensors in the heating plate unnecessary by using a model functional relationship to accurately predict in real time CD resist parameters in response to relative temperature changes in the heating plate temperature, thereby increasing flexibility to process variable changes and minimizing down time. Finally, the entire process including production, calibration, and adjustment to environmental or process specific conditions can be readily automated to increase wafer throughput and yield.
The preferred embodiments, aspects, and features of the invention having been described, it will be apparent to those skilled in the art that numerous variations, modifications, and substitutions may be made without departing from the spirit of the invention as disclosed and further claimed below.
