Patent Application
20240420994
The integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc., is being continuously improved in integrated circuit industry by continual reduction in minimum feature sizes. As the feature sizes are reduced, the distance between metal features is continually reduced, causing an increase in parasitic capacitance, which leads to larger resistance-capacitance (RC) delay for an integrated chip. To reduce the parasitic capacitance, materials having low dielectric constant (k) values are used. However, such materials having low k values might impede thermal dissipation, and thus, cause thermal-related reliability issues and performance deterioration.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “on,” “downwardly,” “upwardly,” “upper,” “lower,” “over,” “below,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
For the purposes of this specification and appended claims, unless otherwise indicated, all numbers expressing amounts, sizes, dimensions, proportions, shapes, formulations, parameters, percentages, quantities, characteristics, and other numerical values used in the specification and claims, are to be understood as being modified in all instances by the term “about” even though the term “about” may not expressly appear with the value, amount or range. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and attached claims are not and need not be exact, but may be approximate and/or larger or smaller as desired, reflecting tolerances, conversion factors, rounding off, measurement error and the like, and other factors known to those of skill in the art depending on the desired properties sought to be obtained by the presently disclosed subject matter. For example, the term “about,” when referring to a value can be meant to encompass variations of, in some aspects ±10%, in some aspects ±5%, in some aspects ±2.5%, in some aspects ±1%, in some aspects ±0.5%, and in some aspects ±0.1% from the specified amount, as such variations are appropriate to perform the disclosed methods or employ the disclosed compositions.
As feature sizes in semiconductor devices are continuously reduced in integrated circuit industry, thermal management of the semiconductor devices becomes an important issue for boosting performances of the semiconductor devices. Currently, materials having low dielectric constant (k) values are used to reduce a parasitic capacitance and a resistance-capacitance (RC) time delay. However, such materials having low k values may impede thermal dissipation, and thus cause thermal-related reliability issues and performance deterioration. When the materials having low k values are used as inter-metal dielectric materials in semiconductor devices, heat produced from, for example, but not limited to, working devices and/or conductive lines will degrade the performance of the semiconductor devices if the heat cannot be dissipated efficiently. Therefore, the present disclosure is directed to a semiconductor device including an interconnect layer having improved thermal dissipation. Such interconnect layer can be applied on a front side, a back side, or both sides of a semiconductor substrate. In addition, a single damascene process or a dual damascene process can be used for manufacturing the interconnect layer.
Referring to
In some embodiments, the semiconductor substrate 10 may include, for example, but not limited to, an elemental semiconductor or a compound semiconductor. In some embodiments, the elemental semiconductor includes a single species of atoms, such as silicon (Si) or germanium (Ge) in column XIV of the periodic table, and may be in crystal, polycrystalline, or an amorphous form. Other suitable materials are within the contemplated scope of the present disclosure. In some embodiments, the compound semiconductor includes two or more elements, and examples thereof may include, but not limited to, silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP). Other suitable materials are within the contemplated scope of the present disclosure. The compound semiconductor may have a gradient feature in which the compositional ratio thereof changes from one location to another location therein. The compound semiconductor may be formed over a silicon substrate. The compound semiconductor may be strained. In some embodiments, the semiconductor substrate may include a multilayer compound semiconductor structure. In some embodiments, the semiconductor substrate may be a semiconductor on insulator (SOI) (e.g., silicon germanium on insulator (SGOI)). Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, or combinations thereof. Other suitable materials are within the contemplated scope of the present disclosure. The SOI substrate may be doped with a P-type dopant, for example, but not limited to, boron (Br), aluminum (Al), or gallium (Ga). Other suitable materials are within the contemplated scope of the present disclosure. Alternatively, the SOI substrate may be doped with an N-type dopant, for example, but not limited to, nitrogen (N), phosphorous (P), or arsenic (As). Other suitable materials are within the contemplated scope of the present disclosure. In some embodiments, the semiconductor substrate may further include various active regions, for example, the active regions configured for an N-type metal oxide semiconductor transistor device (NMOS) or the active regions configured for a P-type metal oxide semiconductor transistor device (PMOS).
In some embodiments, the conductive line layer 20 may include a dielectric layer (not shown) disposed on the semiconductor layer 10, and a plurality of conductive lines (for example, metal lines) 21 disposed in the dielectric layer and spaced apart from each other. One of the conductive lines 21 is shown in
The dielectric layer is formed on the semiconductor substrate 10 using the dielectric material by a suitable deposition process, for example, but not limited to, a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a spin-on-dielectric (SOD) process, or the like, or combination thereof. Other suitable deposition processes are within the contemplated scope of the present disclosure. The dielectric layer formed on the semiconductor substrate 10 is patterned by a suitable etching process (for example, a dry etching process, a wet etching etching process, or a combination thereof) through a pattern of openings formed in a patterned mask layer (not shown) so as to form a plurality of trenches (not shown) spaced part from each other. The conductive material is filled into the trenches by a suitable deposition process as is known to those skilled in the art of semiconductor fabrication, for example, but not limited to, selective or non-selective physical vapor deposition (PVD), selective or non-selective CVD, selective or non-selective plasma-enhanced CVD (PECVD), selective or non-selective ALD, selective or non-selective plasma-enhanced ALD (PEALD), electroless deposition (ELD), electro-chemical plating (ECP), or the like, and a planarization treatment (e.g., chemical mechanic planarization (CMP)) is then performed to remove excess of the conductive material over the dielectric layer so as to form the conductive line layer 20 including the conductive lines 21 disposed in the dielectric layer.
In some embodiments, the etch stop layer 30 is formed on the conductive line layer 20 by a suitable deposition process as is known in the art of semiconductor fabrication, such as PVD, CVD, ALD, PEALD, thermal ALD, PECVD, or the like. Other suitable deposition techniques are within the contemplated scope of the present disclosure. In some embodiments, the etch stop layer 30 may include silicon nitride, silicon carbonitride, silicon oxide, silicon oxynitride, silicon oxycarbon nitride, silicon carbide, silicon oxycarbide, metal (for example, but not limited to, ruthenium (Ru), tungsten (W), titanium (Ti), aluminum (Al), cobalt (Co), or the like, or combinations thereof), metal oxide (for example, but not limited to, aluminum oxide (AlOx), or the like), metal oxynitride (for example, but not limited to, aluminum oxynitride (AlOxNy), or the like). Other suitable materials are within the contemplated scope of the present disclosure. In some embodiments, two or more of the etch stop layers 30 may be formed on the conductive line layer 20 depending on practical requirements, and each of the etch stop layers 30 may be independently selected from the materials for the etch stop layer 30 as described above. In some embodiments, the etch stop layer 30 has a thickness ranging from about 10 nanometers (nm) to about 500 nm. If the thickness of the etch stop layer 30 is less than 10 nm, the etch stop layer 30 cannot be used as an effective etch stop layer to stop a subsequent etching process.
In some embodiments, the dielectric layer 40 may be formed on the etch stop layer 30 by a suitable deposition process as is known in the art of semiconductor fabrication, such as CVD, ALD, PEALD, thermal ALD, PECVD, or the like. Other suitable deposition techniques are within the contemplated scope of the present disclosure. In some embodiments, the dielectric layer 40 include a high thermal conductive dielectric material. In some embodiments, the high thermal conductive dielectric material for the dielectric layer 40 has a thermal conductivity greater than about 10 W/mK. In some embodiments, the high thermal conductive dielectric material for the dielectric layer 40 has a thermal conductivity greater than about 100 W/mK. In some embodiments, the high thermal conductive dielectric material for the dielectric layer 40 may include, for example, but not limited to, boron arsenide (BAs), beryllium oxide (BeOx), hexagonal boron nitride (h-BN), diamond, graphene, graphite, silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AlOx), aluminum nitride (AlN), magnesium oxide (MgO), silicon oxide (SiOx), sapphire, zirconium oxide (ZrOx), bismuth oxide (BiOx), titanium oxide (TiOx), gallium oxide (GaOx), gallium arsenide (GaAs), gallium nitride (GaN), β-carbon nitride (β-C3N4), indium antimonide (InSb), boron carbide (B4C), hafnium oxide (HfO), or combinations thereof. Other suitable high thermal conductive dielectric materials are within the contemplated scope of the present disclosure. In some embodiments, one or more layers of the high thermal conductive dielectric material independently selected from the high thermal conductive dielectric material described above can be used for forming the dielectric layer 40.
Referring to
In some embodiments, the patterned mask layer for patterning the dielectric layer 40 of the structure shown in
A mask layer (for example, a hard mask layer) is deposited on the dielectric layer 40 of the structure shown in
Referring to
Referring to
Referring to
In some embodiments, the conductive interconnect structure 70 includes a plurality of first conductive features (for example, conductive lines) 71 spaced part from each other and a second conductive feature (for example, a conductive via) 72 disposed below and connected to a corresponding one of the first conductive features 71, so as to electrically interconnect the corresponding one of the first conductive feature 71 and the corresponding one of the conductive lines 21 of the conductive line layer 20. The second conductive feature 72 cooperates with the corresponding one of the first conductive features 71 to form an integrated conductive feature 73. In some embodiments, the conductive interconnect structure 70 may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), gold (Au), silver (Ag), tungsten (W), cobalt (Co), ruthenium (Ru), iridium (Ir), platinum (Pt), nickel (Ni), palladium (Pd), osmium (Os), molybdenum (Mo), titanium (Ti), ruthenium (Ru), scandium (Sc), rhodium (Rh), carbon (C), or the like, or combinations thereof. Other suitable conductive materials are within the contemplated scope of the present disclosure.
In some embodiments, one or more layers of the barrier liner material are conformally formed on the structure shown in
Referring to the example illustrated in
The first interconnect sub-layer 80′ includes: an upper portion of the dielectric layer 40; the first conductive features 71 disposed in the upper portion of the dielectric layer 40; the first blocking dielectric portions 51, each of which is disposed in the upper portion of the dielectric layer 40 to isolate a corresponding one of the first conductive features 71 from the upper portion of the dielectric layer 40; an upper part of the second blocking dielectric portion 52 disposed to isolate a corresponding one of the first conductive features 71 from the upper portion of the dielectric layer 40; the first barrier liner portions 61 disposed to separate a corresponding one of the first conductive features 71 from a corresponding one of the first blocking dielectric portions 51; and an upper part of the second barrier liner portion 62 disposed to separate a corresponding one of the first conductive features 71 from the upper part of the second blocking dielectric portion 52.
The second interconnect sub-layer 80″ includes: a lower portion of the dielectric layer 40; the second conductive feature 72 disposed in the lower portion of the dielectric layer 40; a lower part of the second blocking dielectric portion 52 disposed to isolate the second conductive feature 72 from the lower portion of the dielectric layer 40; and a lower part of the second barrier liner portion 62 disposed to separate the second conductive features 72 from the lower part of the second blocking dielectric portion 52.
Since the dielectric layer 40 is made of the high thermal conductive dielectric material having a thermal conductivity greater than about 10 W/mK, and serves as a heat dissipation layer, the heat produced from, for example, but not limited to, the conductive interconnect structure 70 can be dissipated efficiently. In addition, the blocking dielectric layer 50′ is disposed in the dielectric layer 40 to isolate the conductive interconnect structure 70 from the dielectric layer 40 and to isolate the first conductive features 71 from one another. Therefore, current leakage among the first conductive features 71 through the dielectric layer 40 can be avoided. In some embodiments, the blocking dielectric layer 50′ has a thickness ranging from about 0.1 nm to about 500 nm. If the thickness of the blocking dielectric layer 50′ is less than 0.1 nm, the current leakage among the first conductive features 71 through the dielectric layer 40 cannot be avoided effectively.
In addition, the interconnect layer 80 includes an interconnect structure 81, which includes a plurality of first features 811 (for example, a plurality of line features) spaced apart from each other and a second feature 812 (for example, a via feature) connected to a corresponding one of the first features 811. The first features 811 are disposed in the upper portion of the dielectric layer 40, and the second feature 812 is disposed in the lower portion of the dielectric layer 40. The second feature 812 includes the second conductive feature 72, the lower part of the second barrier liner portion 62 covering a bottom and a lateral surface of the second conductive feature 72, and the lower part of the second blocking dielectric portion 52 laterally covering the lower part of the second barrier liner portion 62. In some embodiments, the second feature 812 has a horizontal dimension (D1) ranging from about 10 nm to about 1000 nm. The corresponding one of the first features 811 connected to the second feature 812 includes a corresponding one of the first conductive features 71 connected to the second conductive feature 72, the upper part of the second barrier liner portion 62 laterally covering the corresponding one of the first conductive features 71, and the upper part of the second blocking dielectric portion 52 laterally covering the upper part of the second barrier liner portion 62. Each of the first features 811, other than the corresponding one of the first features 811 connected to the second feature 812, includes a corresponding one of the first conductive features 71, a corresponding one of the first barrier liner portions 61 covering a bottom and a lateral surface of the corresponding one of the first conductive features 71, and a corresponding one of the first blocking dielectric portions 51 disposed to be separated from the corresponding one of the first conductive features 71 by the corresponding one of the first barrier liner portions 61. Each of the first features 811 has a horizontal dimension (D2) ranging from about 10 nm to about 1000 nm. Two adjacent ones of the first features 811 are spaced apart from each other by a distance (D3) ranging from about 10 nm to about 1000 nm. In some embodiments, the first features 811 have a height (H1) ranging from about 10 nm to about 3000 nm. In some embodiments, the second features 812 have a height (H2) ranging from about 10 nm to about 3000 nm.
Referring to
In some embodiments, the blocking dielectric layer 50′ of the structure shown in
Referring to
Referring to
Similarly, referring to the example illustrated in
In a semiconductor device of the present disclosure, a dielectric layer made of a high thermal conductive dielectric material having a thermal conductivity greater than about 10 W/mK serves as a heat dissipation layer of an interconnect layer, so that heat produced from, for example, but not limited to, a conductive interconnect structure can be dissipated efficiently. In addition, a blocking dielectric layer is disposed in the dielectric layer to isolate the conductive interconnect structure from the dielectric layer and to isolate conductive features of the conductive interconnect structure from one another. Therefore, current leakage among the conductive features through the dielectric layer 40 can be avoided.
In accordance with some embodiments of the present disclosure, a semiconductor device includes a substrate, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. The heat dissipation dielectric layer is disposed on the substrate and has a thermal conductivity greater than 10 W/mK. The conductive interconnect structure is disposed in the heat dissipation dielectric layer. The blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.
In accordance with some embodiments of the present disclosure, the heat dissipation dielectric layer includes a thermal conductive dielectric material, which includes boron arsenide, beryllium oxide, hexagonal boron nitride, diamond, graphene, graphite, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, sapphire, zirconium oxide, bismuth oxide, titanium oxide, gallium oxide, gallium arsenide, gallium nitride, β-carbon nitride, indium antimonide, boron carbide, hafnium oxide, or combinations thereof.
In accordance with some embodiments of the present disclosure, the blocking dielectric layer includes a blocking dielectric material, which includes boron arsenide, beryllium oxide, hexagonal boron nitride, diamond, graphene, graphite, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, sapphire, zirconium oxide, bismuth oxide, titanium oxide, gallium oxide, gallium arsenide, gallium nitride, β-carbon nitride, indium antimonide, boron carbide, hafnium oxide, silicon carbonitride, aluminum oxynitride, or combinations thereof.
In accordance with some embodiments of the present disclosure, the conductive interconnect structure includes at least one conductive feature having a sidewall, and the blocking dielectric layer includes at least one blocking dielectric portion covering the sidewall of the at least one conductive feature.
In accordance with some embodiments of the present disclosure, the at least one conductive feature further has a bottom connected to the sidewall, and the at least one blocking dielectric portion further covers the bottom of the at least one conductive feature.
In accordance with some embodiments of the present disclosure, the side wall of the at least one conductive feature is partially covered by the at least one blocking dielectric portion.
In accordance with some embodiments of the present disclosure, the side wall of the at least one conductive feature is fully covered by the at least one blocking dielectric portion.
In accordance with some embodiments of the present disclosure, the conductive interconnect structure includes a plurality of first conductive features and a second conductive feature connected to a corresponding one of the first conductive features to form an integrated conductive feature having a sidewall. Each of the first conductive features other than the corresponding one of the first conductive features connected to the second conductive feature have a sidewall and a bottom connected to the sidewall. The blocking dielectric layer includes a first blocking dielectric portion and a second blocking dielectric portion. The first blocking dielectric portion covers the sidewall and the bottom of each of the first conductive features other than the corresponding one of the first conductive features connected to the second conductive feature. The second blocking dielectric portion covers the sidewall of the integrated conductive feature.
In accordance with some embodiments of the present disclosure, the sidewall of the integrated conductive feature is partially covered by the second blocking dielectric portion.
In accordance with some embodiments of the present disclosure, the sidewall of the integrated conductive feature is fully covered by the second blocking dielectric portion.
In accordance with some embodiments of the present disclosure, a semiconductor device includes a substrate, an etch stop layer, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. The etch stop layer is disposed on the substrate. The heat dissipation dielectric layer is disposed on the etch stop layer opposite to the substrate, and has a thermal conductivity greater than 10 W/mK. The conductive interconnect structure is disposed in the heat dissipation dielectric layer. The blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.
In accordance with some embodiments of the present disclosure, the heat dissipation dielectric layer includes a thermal conductive dielectric material, which includes boron arsenide, beryllium oxide, hexagonal boron nitride, diamond, graphene, graphite, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, sapphire, zirconium oxide, bismuth oxide, titanium oxide, gallium oxide, gallium arsenide, gallium nitride, β-carbon nitride, indium antimonide, boron carbide, hafnium oxide, or combinations thereof. The blocking dielectric layer includes a blocking dielectric material, which includes boron arsenide, beryllium oxide, hexagonal boron nitride, diamond, graphene, graphite, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, sapphire, zirconium oxide, bismuth oxide, titanium oxide, gallium oxide, gallium arsenide, gallium nitride, β-carbon nitride, indium antimonide, boron carbide, hafnium oxide, silicon carbonitride, aluminum oxynitride, or combinations thereof.
In accordance with some embodiments of the present disclosure, the conductive interconnect structure includes at least one conductive feature having a sidewall, and the blocking dielectric layer includes at least one blocking dielectric portion covering the sidewall of the at least one conductive feature.
In accordance with some embodiments of the present disclosure, the at least one blocking dielectric portion extends to terminate at the etch stop layer so as to partially cover the sidewall of the at least one conductive feature.
In accordance with some embodiments of the present disclosure, the at least one blocking dielectric portion extends through the etch stop layer so as to fully cover the sidewall of the at least one conductive feature.
In accordance with some embodiments of the present disclosure, the conductive interconnect structure includes a plurality of first conductive features and a second conductive feature connected to a corresponding one of the first conductive features to form an integrated conductive feature having a sidewall. Each of the first conductive features other than the corresponding one of the first conductive features connected to the second conductive feature has a sidewall and a bottom connected to the sidewall. The blocking dielectric layer includes a first blocking dielectric portion and a second blocking dielectric portion. The first blocking dielectric portion covers the sidewall and the bottom of each of the first conductive features other than the corresponding one of the first conductive features connected to the second conductive feature. The second blocking dielectric portion extends to terminate at the etch stop layer so as to partially cover the sidewall of the integrated conductive feature.
In accordance with some embodiments of the present disclosure, the conductive interconnect structure includes a plurality of first conductive features and a second conductive feature connected to a corresponding one of the first conductive features to form an integrated conductive feature having a sidewall. Each of the first conductive features other than the corresponding one of the first conductive features connected to the second conductive feature has a sidewall and a bottom connected to the sidewall. The blocking dielectric layer includes a first blocking dielectric portion and a second blocking dielectric portion. The first blocking dielectric portion covers the sidewall and the bottom of each of the first conductive features other than the corresponding one of the first conductive features connected to the second conductive feature. The second blocking dielectric portion extends through the etch stop layer so as to fully cover the sidewall of the integrated conductive feature.
In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a first patterned dielectric layer on a substrate, the first patterned dielectric layer being formed with a first recess and having a thermal conductivity greater than 10 W/mK; forming a first feature in the first recess, the first feature including a first conductive feature and a layer of a first blocking dielectric material laterally covering the first conductive feature; forming a second patterned dielectric layer on the first patterned dielectric layer, the second patterned dielectric layer being formed with a plurality of second recesses, one of which is formed on the first feature, the second patterned dielectric layer having a thermal conductivity greater than 10 W/mK; and forming a plurality of second features in the second recesses, respectively, each of the second feature including a second conductive feature and a layer of a second blocking dielectric material laterally covering the second conductive feature.
In accordance with some embodiments of the present disclosure, each of the first patterned dielectric layer and the second patterned dielectric layer independently includes a thermal conductive dielectric material selected from boron arsenide, beryllium oxide, hexagonal boron nitride, diamond, graphene, graphite, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, sapphire, zirconium oxide, bismuth oxide, titanium oxide, gallium oxide, gallium arsenide, gallium nitride, β-carbon nitride, indium antimonide, boron carbide, hafnium oxide, and combinations thereof. Each of the first blocking dielectric material and the second blocking dielectric material is independently selected from boron arsenide, beryllium oxide, hexagonal boron nitride, diamond, graphene, graphite, silicon nitride, silicon carbide, aluminum oxide, aluminum nitride, magnesium oxide, silicon oxide, sapphire, zirconium oxide, bismuth oxide, titanium oxide, gallium oxide, gallium arsenide, gallium nitride, β-carbon nitride, indium antimonide, boron carbide, hafnium oxide, silicon carbonitride, aluminum oxynitride, and combinations thereof.
In accordance with some embodiments of the present disclosure, the first patterned dielectric layer and the second patterned dielectric layer are formed integrally at the same time. The first recess is disposed below and in spatial communication with a corresponding one of the second recesses. The first feature and the second features are formed at the same time.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes or structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
