The present invention relates generally to semiconductor test equipment, and more particularly relates to methods and apparatus for routing test signals/power to and from integrated circuits of semiconductor dies.
Integrated circuits are used in a wide variety of products. Integrated circuits have continuously decreased in price and increased in performance, becoming ubiquitous in modern electronic devices. These improvements in the performance/cost ratio are based, at least in part, on miniaturization, which enables more semiconductor dies to be produced from a wafer with each new generation of the integrated circuit manufacturing technology. Furthermore, the total number of the signal and power/ground contacts on a semiconductor die generally increases with new, more complex die designs.
Prior to shipping a semiconductor die to a customer, the performance of the integrated circuits is tested, either on a statistical sample basis or by testing each die. An electrical test of the semiconductor die typically includes powering the die through the power/ground contacts, transmitting signals to the input contacts of the die, and measuring the resulting signals at the output contacts of the die. Therefore, during the electrical test at least some contacts on the die must be electrically contacted to connect the die to sources of power and test signals.
Conventional test contactors include an array of contact pins attached to a substrate that can be a relatively stiff printed circuit board (PCB). In operation, the test contactor is pressed against a wafer such that the array of contact pins makes electrical contact with the corresponding array of die contacts (e.g., pads or solderballs) on the dies (i.e., devices under test or DUTs) of the wafer. Next, a wafer tester sends electrical test sequences (e.g., test vectors) through the test contactor to the input contacts of the dies of the wafer. In response to the test sequences, the integrated circuits of the tested die produce output signals that are routed through the test contactor back to the wafer tester for analysis and determination whether a particular die passes the test. Next, the test contactor is stepped onto another die or group of dies that are tested in parallel to continue testing till the entire wafer is tested. If, for example, the test contactor contacts a group of dies that is tested in parallel, then to test some groups of the dies that are close to the edge of the wafer, the test contactor must step over the edge of the wafer. For example, if all the dies on the wafer are to be tested in four touch-downs, then the test contactor may contact a quarter of the wafer in one touch-down, and, after testing the dies in that segment of the wafer, move into the contact with another quarter of the wafer in the next touch-down, and so on. Such a sequence of contacts between the test contactor and the wafer may result in an overhang of the test contactor over the edge of the wafer. The overhang may damage some conventional contactors because of an uneven force loading of the contactor when not engaging all their contact pins against the dies under the test.
In general, an increasing number of die contacts that are distributed over a decreasing area of the die results in smaller contacts spaced apart by smaller distances (e.g., a smaller pitch). Furthermore, a characteristic diameter of the contact pins of the test contactor generally scales with a characteristic dimension of the contact structures on the semiconductor die or the package. Therefore, as the contact structures on the die become smaller and/or have a smaller pitch, the contact pins of the test contactors become smaller, too. However, it is difficult to significantly reduce the diameter and pitch of the contact pins of the test contactor, e.g., because of the difficulties in machining and assembling such small parts, resulting in low yield and inconsistent performance from one test contactor to another. Furthermore, precise alignment between the test contactor and the wafer is difficult because of the relatively small size/pitch of the contact structures on the wafer.
Accordingly, there remains a need for cost effective test contactors that are not damaged by uneven loading and that can scale down in size with the size and pitch of the contact structure on the die.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated with reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
Specific details of several embodiments of representative wafer translators and associated methods for use and manufacture are described below. The wafer translators can be used for testing semiconductor dies on a wafer. The semiconductor dies may include, for example, memory devices, logic devices, light emitting diodes, micro-electro-mechanical-systems, and/or combinations of these devices. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference to
Briefly described, methods and devices for testing dies on the semiconductor wafers are disclosed. The semiconductor wafers are produced in several diameters, e.g., 150 mm, 200 mm, 300 mm, 450 mm, etc. The disclosed methods and systems enable operators to test devices having pads, solderballs and/or other contact structures having small sizes and/or pitches. Solderballs, pads, and/or other suitable conductive elements on the dies are collectively referred to herein as “contact structures” or “contacts.” In many embodiments, the technology described in the context of one or more types of contact structures can also be applied to other contact structures.
In some embodiments, a wafer-side of the wafer translator carries the wafer-side contact structures having relatively small sizes and/or pitches (collectively, “scale”). The wafer-side contact structures of the wafer translator are electrically connected to corresponding inquiry-side contact structures having relatively larger sizes and/or pitches at the opposite, inquiry-side of the wafer translator. Therefore, once the wafer-side contact structures are properly aligned to contact the semiconductor wafers, the larger size/pitch of the opposing inquiry-side contact structures enable more robust contact (e.g., requiring less precision). The larger size/pitch of the inquiry-side contact structures may provide more reliable contact and be easier to align against the pins of the test contactor. In some embodiments, the inquiry-side contacts may have mm scale, while the wafer-side contacts have sub-mm or μm scale.
In at least some embodiments, contact between the wafer translator and the wafer is facilitated by a vacuum in a space between the wafer translator and the wafer. For example, a pressure differential between a lower pressure (e.g., sub-atmospheric pressure) in the space between the wafer translator and the wafer, and a higher outside pressure (e.g., atmospheric pressure) can generate a force over the inquiry-side of the wafer translator resulting in a sufficient electrical contact between the wafer-side contact structures and the corresponding die contacts of the wafer.
Many embodiments of the technology described below may take the form of computer- or controller-executable instructions, including routines executed by a programmable computer or controller. Those skilled in the art will appreciate that the technology can be practiced on computer/controller systems other than those shown and described below. The technology can be embodied in a special-purpose computer, controller or data processor that is specifically programmed, configured or constructed to perform one or more of the computer-executable instructions described below. Accordingly, the terms “computer” and “controller” as generally used herein refer to any data processor and can include Internet appliances and hand-held devices (including palm-top computers, wearable computers, cellular or mobile phones, multi-processor systems, processor-based or programmable consumer electronics, network computers, mini computers and the like). Information handled by these computers can be presented by any suitable display medium, including a CRT display or LCD.
The technology can also be practiced in distributed environments, where tasks or modules are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules or subroutines may be located in local and remote memory storage devices. Aspects of the technology described below may be stored or distributed on computer-readable media, including magnetic or optically readable or removable computer disks, as well as distributed electronically over networks. Data structures and transmissions of data particular to aspects of the technology are also encompassed within the scope of the embodiments of the technology.
In some embodiments, the signals and power can be routed from the tester to the test contactor 30 using cables 39. Conductive traces 38 carried by a test contactor substrate 32 can electrically connect the cables 39 to contacts 36 on the opposite side of the test contactor substrate 32. In operation, the test contactor 30 can contact an inquiry-side 13 of a wafer translator 10 as indicated by arrows A. In at least some embodiments, relatively large inquiry-side contact structures 14 can improve alignment with the corresponding contacts 36 of the test contactor 30. The contact structures 14 at the inquiry-side 13 are electrically connected with relatively small wafer-side contact structures 16 on a wafer-side 15 of the translator 10 through conductive traces 18 of a wafer translator substrate 12. The size and/or pitch of the wafer-side contact structures 16 are suitable for contacting the corresponding die contacts 26 of the wafer 20. Arrows B indicate a movement of the wafer translator 10 to make contact with an active side 25 of the wafer 20. As explained above, the signals and power from the tester can test the DUTs of the wafer 20, and the output signals from the tested DUTs can be routed back to the tester for analysis and a determination as to whether the DUTs are suitable for packaging and shipment to the customer.
The wafer 20 is supported by a wafer chuck 40. Arrows C indicate the direction of the wafer 20 mating with the wafer chuck 40. In operation, the wafer 20 can be held against the wafer chuck 40 using, e.g., vacuum V or mechanical clamping.
The wafer 20 includes multiple groups of dies 120A-120D shown in a detail 100. In the illustrated embodiment, the die 120A denotes a northeast die in the group, the die 120B denotes the northwest die, the die 120C denotes the southwest die, and the die 120D denotes the southeast die. The individual dies include a group of the die contacts 26 (e.g., a column of the die contacts 26) that may be used for die testing.
The inquiry-side 13 of the wafer translator 110 includes inquiry-side contact structures 114 that, in operation, can be contacted by the contacts of the test contactor 30 (not shown) to transfer test signals/power from the tester to the dies of the wafer 20, and back. As explained with reference to
In at least some embodiments, by stepping the test contactor 30 by one inquiry-side contact, for example, from contacting the inquiry-side contacts 114B to contacting the inquiry-side contacts 114C, the tester terminates electrical contact with the dies 120B, and establishes electrical contact with the dies 120C. The process may continue by stepping the test contactor 30 by one inquiry-side contact from the inquiry-side contacts 114C to the inquiry-side contacts 114A, etc. In some embodiments, for example, when the pattern of four dies 120A-120D repeats across the semiconductor wafer 20, the test contactor 30 may establish electrical contact with all or almost all dies with four touch-downs of the test contactor 30 against the wafer translator 10. In at least some embodiments, this sequence of touch-downs between the test contactor 30 and the wafer translator 20 can reduce or eliminate an overhang of the test contactor 30 over the edge of the semiconductor wafer 20 and/or the wafer translator 10. In some embodiments, all the dies 120A may be tested in parallel at a touch-down of the test contactor 30, followed by testing all the dies 120B in parallel with the next touch-down, etc.
In some embodiments, the wafer translator 10 may include multiple routing layers for routing the conductive traces 118A-118D. For example, each group of conductive traces 118A-118D may be routed in a dedicated routing layer of a four-layer wafer translator 110. Other routing approaches are possible, for example, using one routing layer for two groups of conductive traces resulting in a two-layer wafer translator 10 (e.g., the conductive traces 118A and 118C in one routing layer, and the conductive traces 118B and 118D in another routing layer). Other distributions of the conductive traces within the routing layers are possible.
From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, in some embodiments, testing of the dies may be done using the tester resources (e.g., tester chips that generate test vectors) carried by the wafer translator, or the tester resources can be carried partially by the tester and partially by the wafer translator. Moreover, while various advantages and features associated with certain embodiments have been described above in the context of those embodiments, other embodiments may also exhibit such advantages and/or features, and not all embodiments need necessarily exhibit such advantages and/or features to fall within the scope of the technology. Accordingly, the disclosure can encompass other embodiments not expressly shown or described herein.
This application claims the benefit of U.S. Provisional Application No. 62/230,608, filed Jun. 10, 2015, and U.S. Provisional Application No. 62/255,230, filed Nov. 13, 2015, both of which are hereby incorporated by reference in their entireties.
Number | Date | Country | |
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62230608 | Jun 2015 | US | |
62255230 | Nov 2015 | US |