Patent Application
20150069627
Embodiments described herein relate to an interposer wafer and a method of manufacturing the same.
When a silicon interposer is manufactured, first holes for forming through electrodes called through silicon vias (TSVs) and second holes for forming alignment marks are simultaneously formed on a silicon wafer. Since the second holes are formed simultaneously with the first holes, the second holes have approximately the same or the half of the depth of the first holes. Even if the depth of the second holes is approximately the half of the depth of the first holes, the second holes are deep enough. Furthermore, an interval between the second holes is set significantly narrower than an interval between the first holes. Therefore, when the through electrodes and the alignment marks are expanded by a thermal process after the through electrodes and the alignment marks are formed, great stress is applied on the alignment marks that have been formed very densely and formed deeply enough. As a result, cracks may be generated, starting from the alignment marks.
Embodiments will now be explained with reference to the accompanying drawings.
In one embodiment, a method of manufacturing an interposer wafer includes forming a first hole having a first depth on a first main surface of a semiconductor wafer. The method further includes forming a second hole having a second depth on the first main surface of the semiconductor wafer before forming the first hole or after forming the first hole, the second depth being shallower than the first depth. The method further includes forming an electrode in the first hole. The method further includes forming an alignment mark in the second hole.
The interposer wafer of the present embodiment includes a semiconductor wafer 1, a plurality of through electrodes (TSV) 2, and a plurality of alignment marks 3.
The semiconductor wafer 1 is, for example, a silicon wafer.
The through electrodes 2 are formed in the chip regions 1a of the semiconductor wafer 1. The planar shape of each through electrode 2 is, for example, circular. The through electrodes 2 are an example of an electrode of the disclosure.
The alignment marks 3 are formed in the scribe line regions 1b of the semiconductor wafer 1. The planar shape of each alignment mark 3 is, for example, rectangular. When an interconnect layer or the like is formed on the semiconductor wafer 1, the alignment marks 3 are used as references for mask alignment.
It is noted that positions and numbers of the through electrodes 2 and the alignment marks 3 illustrated in
The semiconductor wafer 1 includes first and second main surfaces S1 and S2. In addition, the semiconductor wafer 1 includes a plurality of first holes H1 in the chip region 1a and a plurality of second holes H2 in the scribe line region 1b.
In the present specification, a +Z direction is treated as an upward direction, and a −Z direction is treated as a downward direction. For example, a positional relationship between the first and second main surfaces S1 and S2 is represented that the first main surface S1 is placed above the second main surface S2.
The first holes H1 are provided on the first main surface S1 of the semiconductor wafer 1 and have a first depth D1. The through electrodes 2 are formed in the first holes H1.
The first depth D1 is, for example, 50 to 100 μm. Also, a diameter of the first holes H1 is, for example, 5 to 20 μm. In addition, an interval between the adjacent first holes H1 is, for example, 40 to 100 μm.
The second holes H2 are provided on the first main surface S1 of the semiconductor wafer 1 and have a second depth D2 which is shallower than the first depth D1 (D2<D1). In the present embodiment, the second depth D2 is set to 1/10 or less of the first depth D1 (D2≦D1/10), from a perspective of preventing generation of cracks starting from the alignment marks 3. The alignment marks 3 are formed in the second holes H2. Details about the prevention of the crack generation will be described below.
Similarly, from the perspective of preventing the crack generation, the second depth D2 is desirably set to 10 μm or less, and more desirably to 2 μm or less. In the present embodiment, the second depth D2 is set to, for example, 1 to 5 μm. Also, a width of the second holes H2 in a short side direction is, for example, 0.5 to 1 μm. In addition, an interval between the adjacent second holes H2 is, for example, 5 to 10 μm.
Each through electrode 2 includes a barrier metal layer 12 formed on side surfaces and a bottom surface of a first hole H1 via an insulating layer 11, and a plug material layer 13 formed in the first hole H1 via the insulating layer 11 and the barrier metal layer 12.
Similarly, each alignment mark 3 includes the barrier metal layer 12 formed on side surfaces and a bottom surface of a second hole H2 via the insulating layer 11, and the plug material layer 13 formed in the second hole H2 via the insulating layer 11 and the barrier metal layer 12.
The insulating layer 11 is, for example, a silicon oxide layer. The barrier metal layer 12 is, for example, a tantalum (Ta) layer or a tantalum nitride (TaN) layer. The plug material layer 13 is, for example, a copper (Cu) layer.
Continuously referring to
Conventionally, since the second holes H2 for forming the alignment marks 3 are formed simultaneously with the first holes H1 for forming the through electrodes 2, the second holes H2 have approximately the same or the half of the depth of the first holes H1. Even if the depth of the second holes H2 is approximately the half of the depth of the first holes H1, the second holes H2 are deep enough. Furthermore, the interval between the second holes H2 is normally set significantly narrower than the interval between the first holes H1. Therefore, when the through electrodes 2 and the alignment marks 3 are expanded by a thermal process after the through electrodes 2 or the alignment marks 3 are formed, great stress is applied on the alignment marks 3 that have been formed very densely and formed deeply enough. As a result, cracks may be generated, starting from the alignment marks 3. The thermal process is, for example, performed in a process of forming an interconnect layer on the semiconductor wafer 1.
This is likely to become a problem in a case where a silicon wafer is used as the semiconductor wafer 1 and copper is used to form the through electrodes 2 and the alignment marks 3. The reason is that a difference in coefficients of thermal expansion between silicon and copper is large.
Accordingly, the second holes H2 of the present embodiment are formed in a process different from a process of forming the first holes H1. Consequently, according to the present embodiment, the second depth D2 can be made sufficiently shallower than the first depth D1. When the second depth D2 is made shallow, the volume of the alignment marks 3 are decreased, and the volume difference between the volume before the thermal expansion of the alignment marks 3 and the volume after the thermal expansion of the alignment marks 3 becomes small. Therefore, according to the present embodiment, the stress applied on the alignment marks 3 can be reduced by making the second depth D2 shallower than the first depth D1, so that the generation of the cracks starting from the alignment marks 3 can be prevented.
An experiment on the thermal expansion of the alignment marks 3 was performed. In a case where the first depth D1 was 100 μm and the second depth D2 was tens of μm (i.e., a case where D2 was tens of % of D1) in the experiment, the cracks starting from the alignment marks 3 were generated. However, in a case where the second depth D2 was a few μm (i.e., a case where D2 was a few % of D1) in the experiment, the cracks starting from the alignment marks 3 were not generated. Accordingly, it is assumed that, when the second depth D2 is roughly 10% or less of the first depth D1, the generation of the cracks can be prevented. Therefore, the second depth D2 of the present embodiment is set to 1/10 or less of the first depth D1. This means that in a case where the first depth D1 is about 100 μm, the second depth D2 is set to 10 μm or less.
When the first and second holes H1 and H2 are formed in different processes, the second holes H2 may be formed before forming the first holes H1, or may be formed after forming the first holes H1.
Although the first and second holes H1 and H2 of the present embodiment are formed in different processes, the through electrodes 2 and the alignment marks 3 of the present embodiment may be formed simultaneously in the same process or may be formed in different processes.
On the other hand, when the through electrodes 2 and the alignment marks 3 are formed in different processes, the through electrodes 2 and the alignment marks 3 may be formed of the same material or may be formed of different materials. For example, in a case where the through electrodes 2 are formed by using copper, the alignment marks 3 may be formed by using copper or may be formed by using aluminum or tungsten.
First, as illustrated in
Next, as illustrated in
The processes of
Next, as illustrated in
The through electrodes 2 and the alignment marks 3 of the present embodiment are formed by simultaneously embedding an embedding material (including the insulating layer 11, the barrier metal layer 12 and the plug material layer 13) in the first and second holes H1 and H2. In other words, the through electrodes 2 and the alignment marks 3 of the present embodiment are formed by the same embedding process.
However, the through electrodes 2 and the alignment marks 3 may be formed by respectively embedding first and second embedding materials in the first and second holes H1 and H2 in different processes. In this case, the embedding process of the second embedding material may be performed before the embedding process of the first embedding material, or may be performed after the embedding process of the first embedding material. In this case, the insulating layer 11, the barrier metal layer 12 and the plug material layer 13 may be used as the first embedding material, and a material which is same as or different from the first embedding material may be used as the second embedding material.
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
In this way, a plurality of interposers are manufactured from one interposer wafer by the processes of
The semiconductor device of
The LSI chips 43 are, for example, field-programmable gate array (FPGA) chips or memory chips. The interposer 42 is, for example, the silicon interposer manufactured by the processes of
The microbumps B1 of the interposer 42 are electrically connected to the LSI chips 43. The C4 bumps B2 of the interposer 42 are electrically connected to conductive layers provided on a front surface of the package substrate 41. As a result, the LSI chips 43 are electrically connected to each other via the interconnect layers 21 in the interposer 42 and conductive layers on the package substrate 41. The present embodiment makes it possible, by using the interposer 42, to realize a system in package (SiP) in which the LSI chips 43 are disposed on the package substrate 41 via the interposer 42.
The conductive layers provided on the front surface of the package substrate 41 are electrically connected to the conductive layers provided on the back surface of the package substrate 41 by, for example, through electrodes penetrating the package substrate 41. Furthermore, the package substrate 41 is disposed on a mother board via the BGA balls 44. The conductive layers provided on the back surface of the package substrate 41 are electrically connected to conductive layers provided on a surface of the mother board via the BGA balls 44.
As described above, the second holes H2 for forming the alignment marks 3 of the present embodiment are formed in a process different from a process of the first holes H1 for forming the through electrodes 2. Therefore, according to the present embodiment, the generation of the cracks starting from the alignment marks 3 can be prevented by making the second depth D2 shallower than the first depth D1 (for example, the second depth D2 is set to 1/10 or less of the first depth D1).
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel wafers and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the wafers and methods described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
This application is based upon and claims the benefit of priority from the prior U.S. Provisional Patent Application No. 61/874,551 filed on Sep. 6, 2013, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61874551 | Sep 2013 | US |
