Described herein are systems and methods of forming an iridium encased metal interconnect for use within the metallization layers of an integrated circuit die. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.
Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.
Implementations of the invention include a metal interconnect, such as a copper interconnect, that is encased in an iridium shell. The copper interconnect may be used in integrated circuit applications, for instance, in back-end metallization layers that interconnect various devices formed on a semiconductor substrate. The iridium shell may be formed using an iridium liner and an iridium capping layer. The iridium liner may be disposed between the metal interconnect and an underlying dielectric layer and functions as both a barrier layer and an adhesion layer. The iridium capping layer may be formed atop the metal interconnect after the metal has been polished.
For reference,
After the adhesion layer 110 is formed, the conventional damascene process of
In various implementations of the invention, the iridium liner 202A may be formed using different processes such as an iridium-immobilization-process (IIP), an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process.
The process 300 begins by providing a semiconductor substrate onto which a metal interconnect, such as a copper interconnect, may be formed (302). For instance, the semiconductor substrate may be a semiconductor wafer that includes a dielectric layer on its surface. The dielectric layer may include at least one trench in which the copper interconnect is to be formed. The dielectric layer may be formed from conventional materials used in dielectric layers, including but not limited to silicon dioxide (SiO2) and carbon-doped oxide (CDO).
The substrate may be cleaned with a rinsing solution to remove impurities, contaminants, and/or oxides (304). The rinsing solution used may be an alkaline solution or a pure water rinse. The rinsing solutions may contain surfactants (e.g. polyoxyethylene derivatives), phosphates, and/or carbonates in alkaline media. These rinsing solutions tend to make the semiconductor substrate more hydrophilic and tend to remove loose particles due to the fluid motion on the wafer. Rinsing solutions typically used in a palladium-immobilization-process (PIP) may be used here, as will be known to those of ordinary skill in the art.
After the cleaning process, iridium metal may be deposited on the substrate and into the trench by way of a chelating group. Turning to
Returning to
Next, the substrate may be immersed in a solution containing iridium metal (308). When the substrate is immersed, iridium metal in solution becomes bonded to the nitrogen in the exposed azo group. This results in the formation of an adsorbed layer of an iridium species over the chelating group. In some implementations of the invention, the source of the iridium may be IrF3.H2O, IrCl3.H2O, IrBr3.H2O, IrI3.H2O, Ir(CO)2Cl4, Ir(CO)2Br4, IrI(CO)3, HIr(CO)4, CpIr(CO)2 (where Cp=cyclopentadienyl), pyrrolyl-Ir—(CO)2—Cl, and ligand variations thereof including, but not limited to, allyl, vinyl, cyclohexadienyl, pentamethyl-Cp, (COD)IrCp (where COD=cyclooctadiene), Ir(COD)2X2 (where X=a halide), Ir(CO)X, CpIr(pyrrolyl)3, hexadienyl-Ir(Cp), Ir(allyl)(pyrrolyl)2, and IrH5(PEt3)2 (where Et=ethyl).
In alternate implementations of the invention, the chelating group and the iridium metal may be applied using techniques other than immersion in two separate solutions. In some implementations, a wet chemical process may be used in which the substrate may be immersed in a solution containing both the chelating group and the iridium metal. In further implementations, CVD or ALD processes may be used in lieu of a wet chemical process. For instance, in one implementation, a wet chemical method may be used to attach the chelating group to the substrate, followed by an ALD or CVD process to attach the iridium metal to the chelating group.
After bonding to the substrate by way of the chelating group, the iridium metal is then immersed in an activation both that contains a reducing agent (310). As is well known in the art, the oxidized iridium metal is activated by being reduced in the activation bath (e.g., Ir3+ or Ir1+ is reduced to Ir0). When activated, the metal center is electronically neutral and is in the metallic state. A layer of activated iridium metal is now covalently bonded to the chelating group, thereby forming a monolayer of iridium metal that is affixed to the surface of the dielectric layer. The underlying nitrogen containing group acts as an immobilizing structure that holds the iridium metal in place on the substrate.
In another implementation of the invention, the iridium liner 202A may be formed using a novel ALD or CVD process that enables the iridium metal to be deposited directly on the dielectric layer without the need for a chelating group.
As before, the process 500 begins by providing a semiconductor substrate onto which a metal interconnect, such as a copper interconnect, may be formed (502). For instance, the semiconductor substrate may be a semiconductor wafer that includes a dielectric layer on its surface. The dielectric layer may include at least one trench in which the copper interconnect is to be formed. The dielectric layer may be formed from conventional materials used in dielectric layers, including but not limited to SiO2 and CDO. The substrate is then placed in a reactor in preparation for an ALD or CVD process.
In accordance with an implementation of the invention, at least one pulse of TMA or MPA is introduced into the reactor (504). The presence of the TMA or MPA enables the deposition of iridium to occur directly upon the dielectric layer of the substrate. For example, a TMA pulse enables the subsequent deposition of iridium on CDO using a precursor such as Ir(acac)3 at any temperature. A TMA pulse also enables the deposition of iridium on CDO using a precursor such as (MeCp)Ir(COD) at temperatures below 275° C. due to the much lower stability of the (MeCp)Ir(COD) precursor with temperature.
The following are process parameters that may be used for a TMA pulse in accordance with various implementations of the invention. The number of TMA pulses may range from one to ten pulses, with each pulse having a duration of between one and five seconds. Between each TMA pulse may be a one second to five second purge. The reactor pressure may be around 0.1 Torr to 0.5 Torr during the deposition. The TMA is pulsed into the reactor from a TMA source, which may be kept at a static pressure of around 3 Torr to 7 Torr when in a closed system. The TMA source is kept near room temperature (e.g., 20° C. to 25° C.) while the substrate temperature may vary between around 150° C. and 400° C. It should be noted that the scope of the invention includes any possible set of process parameters that may be used to carry out the implementations of the invention described herein.
The TMA or MPA pulse is followed by one or more pulses of iridium precursor and oxygen (506). In some implementations, the iridium precursor may be Ir(acac)3 where acac=acetylacetonato. In other implementations, alternate iridium precursors may be used, including but not limited to Ir4(CO)12, IrH3(PPh3)2, Ir(acac)3, (MeCp)Ir(COD) where Cp=cyclopentadienyl and COD=cyclooctadiene, and IrCl(CO)(PPh3)2. The iridium precursor causes an iridium liner to be deposited on the dielectric layer and within the trench. Multiple pulses of iridium may be used to bring the iridium liner to a desired thickness.
Conventional process parameters may be used for the iridium pulse. For instance, in implementations of the invention, the process parameters for the iridium pulse include, but are not limited to, an iridium precursor discharge pulse duration of between around 1 second and 5 seconds. Before discharge, the gas line pressure may be set to around 0 to 5 psi, the orifice may be between 0.1 mm and 1.0 mm in diameter, and the charge pulse may be between 1 second and 5 seconds. The equilibration time with the valves closed may be 1 second to 5 seconds and the discharge pulse may be 1 second to 5 seconds. The reactor pressure may be between around 0.1 Torr and 0.5 Torr, the iridium precursor temperature may be between around 80° C. and 200° C., the substrate temperature may be between around 150° C. and 400° C., and an RF energy source may be applied at a power that ranges from 5 W to 40 W and at a frequency of 13.56 MHz, 27 MHz, or 60 MHz. It should be noted that the scope of the invention includes any possible set of process parameters that may be used to carry out the implementations of the invention described herein. Furthermore, the precursor and co-reactant (e.g., oxygen) can be flown or pulsed simultaneously to accomplish a CVD-type growth.
Optionally, in an alternate implementation of the invention, one or more additional pulses of TMA or MPA may be introduced into the reactor after the iridium liner has been formed (508). This additional TMA or MPA provides aluminum metal that may be used to dope a subsequently deposited copper metal layer. For instance, after the additional TMA or MPA is pulsed, an electroplating process may be used to deposit a bulk copper layer atop the iridium layer and the additional aluminum. An annealing process may follow that causes the aluminum to diffuse into the copper metal, thereby improving the electromigration properties of the copper interconnect. Typical annealing may be between 80° C. and 400° C. in an inert atmosphere for around 10 minutes to around 60 minutes.
The iridium liner 600 functions as both a barrier to copper diffusion and as an adhesion layer that enables the direct plating of copper metal using one or a combination of an electroless plating process and an electroplating process. The iridium liner 600 therefore eliminates the need for the TaN/Ta stack or TaN/Ru stack used in conventional metal interconnects. In some implementations, the iridium liner 600 may further be used as a seed layer for the subsequent copper deposition, thereby eliminating the need for a copper seed layer.
The iridium liner 600 provides a thinner barrier and adhesion layer that widens the trench gap available for metallization, thereby enabling improved copper gapfill in narrower trenches with aggressive aspect ratios. In addition, due to the thinness of the iridium liner 600, the ratio of barrier metal-to-copper metal in the overall interconnect structure decreases (i.e., the copper line volume increases), which decreases the electrical line resistance and RC delay of the interconnect.
It will also be appreciated by those of skill in the art that the use of the TMA/MPA-enhanced ALD process to form the iridium liner replaces the conventional three step PVD process flow (i.e., PVD TaN deposition +PVD Ta deposition +PVD copper seed deposition) with a single ALD process. Therefore, when compared to the prior art, implementations of the invention reduces the number of process steps required, reduces the amount of wafer handling that occurs, reduces the number of process tools needed, and reduces the overall throughput time.
First, a substrate is provided that includes a dielectric layer having a trench and an iridium liner formed within at least the trench (702). The iridium liner may be formed using either the IIP process of
Next, in some implementations of the invention, an optional electroless copper (EL-Cu) enhancement of the iridium liner may be carried out (704). The substrate with the iridium liner may be immersed into an electroless copper bath where an electroless deposition process is carried out to deposit a copper seed layer over the iridium liner, thereby forming an EL-Cu enhanced iridium liner. The iridium metal serves as a nucleation site for the electroless deposition to occur. The plating bath may contain a copper salt (e.g., copper sulfate), a complexing agent, a reducing agent, and a surfactant. The electroless deposition process may take place at a basic pH level (e.g., a pH level between pH 10 and pH 14) and at a temperature between around 50° C. and 100° C. The substrate may be immersed in the electroless plating bath for the time required to achieve the desired thickness, for example, a time period between 10 seconds and 120 seconds. In implementations, the thin copper seed layer may range from 5 Å to 100 Å. The copper seed layer enables or catalyzes a subsequent electroplating process to fill the interconnect with void-free copper metal.
Following the optional deposition of the copper seed layer, an electroplating process is carried out to deposit a bulk copper layer over the EL-Cu enhanced iridium liner (706). The bulk copper layer fills the trench with copper to form the metal interconnect. The copper metal enters the trench where, due to the relatively large width of the trench enabled by the thin iridium liner, issues such as trench overhang are reduced or eliminated. The use of the optional EL-Cu enhances the noble metal layer catalytic properties for the electroplating process and substantially reduces or eliminates the formation of voids in the bulk copper layer within the trench.
Finally, a chemical mechanical polishing (CMP) process may be used to planarize the deposited copper metal and finalize the copper interconnect structure (708).
In an implementation of the invention, an iridium capping layer may be deposited atop the copper interconnect, thereby forming a copper interconnect that is fully enclosed within an iridium shell. This structure was described above in
In accordance with one implementation of the invention, to form the iridium capping layer, selective iridium deposition may be used on the bulk copper layer after the CMP process has completed. The presence of an iridium shell provides relatively strong protection for the copper interconnect due to the high oxidation resistance of the iridium metal. Iridium may also be used as an etch stop or, if modified chemically, as a non-reflective layer.
In implementations of the invention, the selective iridium deposition may be carried out using an ALD process.
In accordance with an implementation of the invention, the ALD process is then carried out using an iridium precursor and O2 or a reducing agent such as H2 to minimize potential copper layer oxidation (904). In one implementation, the iridium precursor may be (MeCp)Ir(COD). In alternate implementations, the iridium precursor may be Ir4(CO)12, IrH3(PPh3)2, Ir(acac)3, or IrCl(CO)(PPh3)2.
One or more pulses of each precursor may be introduced into the reactor. Process parameters that may be used for the iridium capping layer ALD deposition when (MeCp)Ir(COD) is used as the precursor include, but are not limited to, a (MeCp)Ir(COD) pulse duration of between around 1 second and 5 seconds, a reactor pressure between around 0.1 Torr and 0.5 Torr, a (MeCp)Ir(COD) temperature between around 130° C. and 140° C., a substrate temperature between around 230° C. and 250° C., and an RF energy source applied at a power that ranges from 10 W to 30 W and at a frequency of 13.56 MHz, 27 MHz, or 60 MHz. It should be noted that the scope of the invention includes any possible set of process parameters that may be used to carry out the implementations of the invention described herein.
The ALD process may continue until the iridium capping layer has reached a desired thickness.
Implementations of the invention therefore enable a metal interconnect to be formed within an iridium shell. In addition, implementations of the invention enable the iridium-encased interconnect to be formed directly on a dielectric layer without the need for a conventional barrier and adhesion layer (e.g., a TaN/Ta stack). Elimination of the TaN/Ta stack widens the gap available for metallization, thereby allowing trenches with more aggressive aspect ratios to be filled with void-free metal using known plating processes. Furthermore, replacing the conventional TaN/Ta stack with a thin iridium liner increases the copper line volume, thereby reducing electrical resistance within the interconnect.
The above description of illustrated implementations of the invention, including what is described in the Abstract is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.
These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.