Claims
- 1. A microelectronic capacitance device comprising:
- a. a semiconductor substrate of one conductivity type having first and second surfaces and a resistivity no greater than 0.01 ohm-centimeter,
- b. a multiplicity of parallel semiconductor studs of said one conductivity type integral with and extending perpendicularly from said one surface, said studs having a resistivity of at least 0.06 ohm-centimeter, said studs also having a p-n junction therein, formed by a thin surface layer of semconductor of opposite conductivity type,
- the height of said studs, measured perpindicularly from said one surface, being larger than the average center to center spacing of said studs, whereby the area of said P-N junction is substantially larger than that of a planar P-N junction, for similar substrate areas, and
- c. an adherent film of conductor coating said surface layer of opposite conductivity type and having an electrical contact thereto.
- 2. A capacitance device as in claim 1 wherein said studs have opposite parallel surfaces, and are sufficiently thin to permit the depletion regions from said surfaces to meet upon the application of operational bias.
- 3. A capacitance device as in claim 1 wherein said substrate has a thickness no less than one-half the width of the stud.
Parent Case Info
This is a continuation of application Ser. No. 259,332, filed June 2, 1972, now abandoned.
US Referenced Citations (6)
Foreign Referenced Citations (1)
Number |
Date |
Country |
4,322,748 |
Sep 1968 |
JA |
Continuations (1)
|
Number |
Date |
Country |
Parent |
259332 |
Jun 1972 |
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