LATERAL SILICIDED DIODES

Abstract

A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Description

BRIEF DESCRIPTION OF DRAWINGS

The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIGS. 1A through 1E are cross-sectional views illustrating fabrication of a first lateral Schottky barrier diode is according an embodiment of the present invention;

FIG. 2 is a cross-sectional view of a of a second lateral Schottky barrier diode is according an embodiment of the present invention;

FIGS. 3A through 3F are cross-sectional views illustrating fabrication of a third lateral Schottky barrier diode is according an embodiment of the present invention;

FIG. 4 is a cross-sectional view of a of a fourth lateral Schottky barrier diode is according an embodiment of the present invention;

FIG. 5A is a first plan view of Schottky barrier diodes according to embodiments of the present invention;

FIG. 5B is a second plan view of Schottky barrier diodes according to embodiments of the present invention;

FIGS. 6A through 6F are cross-sectional views illustrating fabrication of a fifth lateral Schottky barrier diode is according an embodiment of the present invention; FIGS. 7A through 7F are cross-sectional views illustrating fabrication of a lateral PIN diode is according an embodiment of the present invention;

FIG. 8 is a cross-sectional view illustrating a method of further isolating Schottky barrier and PIN diodes according to the various embodiments of the present invention;

FIG. 9A is a simple diagram of a field effect transistor (FET) and FIG. 9B is a simple diagram of a bipolar transistor; and

FIG. 10A through 10B are flowcharts illustrating integration of the fabrication of Schottky barrier and PIN diodes according to the various embodiments of the present invention with FETs and bipolar transistors.

Claims

1. A diode, comprising: a doped region having opposite first and second sides, said doped region extending from a top surface of a silicon substrate a first distance into said substrate;a trench having opposite first and second sidewalls and extending from said top surface of said substrate a second distance into said substrate, said first sidewall of said trench of separated from said first sidewall of said doped region by a dielectric region extending from said top surface of said substrate a third distance into said substrate and by a region of said substrate under said dielectric region and between said first side of said doped region and said first sidewall of said trench, said third distance less than said first or second distances; anda first region of a metal silicide layer on said first sidewall of said trench and a second region of said metal silicide layer on a top surface of said doped region, said first and second regions of said metal silicide layer electrically isolated from each other by said dielectric region.

2. The diode of claim 1, further including: a dielectric layer filling said trench and covering said metal silicide layer and said dielectric region;a first electrically conductive contact extending from a top surface of said dielectric layer, through said dielectric layer to said first region of said metal silicide layer, said first electrically conductive contact in direct physical and electrical contact with said first region of said metal silicide layer; anda second electrically conductive contact extending from said top surface of said dielectric layer, through said dielectric layer to said second region of said metal silicide layer, said second electrically conductive contact in direct physical and electrical contact with said second region of said metal silicide layer.

3. The diode of claim 1, wherein said first region of said metal silicide layer extends over a bottom and said second sidewall of said trench, a region of said top surface of said substrate abutting said second sidewall of said trench.

4. The diode of claim 1, wherein said dielectric region abuts said first sidewall of said trench.

5. The diode of claim 1, further including: a first additional doped region extending from said top surface of said substrate a fourth distance into said substrate, said first additional doped region between and abutting both said dielectric region and said first sidewall of said trench;a second additional doped region extending from said bottom of said trench said fourth distance into said substrate, said first additional and second additional doped regions doped to an opposite type from that of said first doped region, a dopant concentration of said first and second additional doped regions at least about 10 times greater than a dopant concentration of said substrate; andsaid second region of said metal silicide layer extending over exposed surfaces of said first and second additional doped regions.

6. The diode of claim 5, further including: an additional trench having opposite first and second sidewalls and extending from said top surface of said substrate said second distance into said substrate, said first sidewall of said additional trench abutting said second side of said doped region; andsaid second region of said metal silicide layer extending over said second side of said doped region exposed in said additional trench and over a bottom surface of said additional trench.

7. The diode of claim 6, further including said dielectric layer filling said additional trench.

8. The diode of claim 1, further including: an additional trench having opposite first and second sidewalls and extending from said top surface of said substrate said second distance into said substrate, said first sidewall of said additional trench abutting said second side of said doped region; and said second region of said metal silicide layer extending over said second side of said doped region exposed in said second trench and a bottom surface of said additional trench.

9. The diode of claim 8, further including said dielectric layer filling said additional trench.

10. The diode of claim 1, wherein said metal silicide is selected from the group consisting of tungsten silicide, molybdenum silicide, tantalum silicide, cobalt silicide, titanium silicide, nickel silicide and platinum silicide.

11. The diode of claim 1, wherein: said doped region is doped N-type and said substrate is doped P-type or is intrinsic, a concentration of dopant in said doped region at least about 10 times greater than a dopant concentration of said substrate; or said doped region is doped P-type and said substrate is doped N-type or is intrinsic, a concentration of dopant in said doped region at least about 10 times greater than a dopant concentration of said substrate.

12. A method of fabricating a diode, comprising: forming doped region in a silicon substrate, said doped region having opposite first and second sides, said doped region extending from a top surface of said substrate a first distance into said substrate;forming a trench in said substrate, said trench having opposite first and second sidewalls and extending from said top surface of said substrate a second distance into said substrate, said first sidewall of said trench separated from said first side of said doped region by a dielectric region extending from said top surface of said substrate a third distance into said substrate and by a region of said substrate under said dielectric region and between said first side of said doped region and said first sidewall of said trench, said third distance less than said first or second distances; andforming a first region of a metal silicide layer on said first sidewall of said trench and forming a second region of said metal silicide layer on a top surface of said doped region, said first and second regions of said metal silicide layer electrically isolated from each other by said dielectric region.

13. The method of claim 12, further including: filling said trench with a dielectric layer and covering said metal silicide layer with said dielectric region;forming a first electrically conductive contact in said dielectric layer, said first electrically conductive contact extending from a top surface of said dielectric layer, through said dielectric layer to said first region of said metal silicide layer, said first electrically conductive contact in direct physical and electrical contact with said first region of said metal silicide layer; andforming a second electrically conductive contact in said dielectric layer, said a second electrically conductive contact extending from said top surface of said dielectric layer, through said dielectric layer to said second region of said metal silicide layer, said second electrically conductive contact in direct physical and electrical contact with said second region of said metal silicide layer.

14. The method of claim 12, wherein said first region of said metal silicide layer extends over a bottom and said second sidewall of said trench, a region of said top surface of said substrate abutting said second sidewall of said trench.

15. The method of claim 12, wherein said dielectric region abuts said first sidewall of said trench.

16. The method of claim 12, further including: forming a first additional doped region in said substrate, said first additional doped region extending from said top surface of said substrate a fourth distance into said substrate, said first additional doped region between and abutting both said dielectric region and said first sidewall of said trench;forming a second additional doped region in said substrate, said second additional doped region extending from said bottom of said trench said fourth distance into said substrate, said first additional and second additional doped regions doped to an opposite type from that of said first doped region, a dopant concentration of said first and second additional doped regions at least about 10 times greater than a dopant concentration of said substrate; andsaid second region of said metal silicide layer extending over exposed surfaces of said first and second additional doped regions.

17. The method of claim 16, further including: forming and additional trench in said substrate, said additional trench having opposite first and second sidewalls and extending from said top surface of said substrate said second distance into said substrate, said first sidewall of said additional trench abutting said second side of said doped region; andsaid second region of said metal silicide layer extending over said second side of said doped region exposed in said additional trench and over a bottom surface of said additional trench.

18. The method of claim 17, further including filling said additional trench with said dielectric layer

19. The method of claim 12, further including: forming an additional trench in said substrate, said additional trench having opposite first and second sidewalls and extending from said top surface of said substrate said second distance into said substrate, said first sidewall of said additional trench abutting said second side of said doped region; andsaid second region of said metal silicide layer extending over said second side of said doped region exposed in said second trench and a bottom surface of said additional trench.

20. The method of claim 19, further including filling said additional trench with said dielectric layer.

21. The method of claim 12, wherein said metal silicide is selected from the group consisting of tungsten silicide, molybdenum silicide, tantalum silicide, cobalt silicide, titanium silicide, nickel silicide and platinum silicide.

22. The method of claim 12, wherein: said doped region is doped N-type and said substrate is doped P-type or is intrinsic, a concentration of dopant in said doped region at least about 10 times greater than a dopant concentration of said substrate; orsaid doped region is doped P-type and said substrate is doped N-type or is intrinsic, a concentration of dopant in said doped region at least about 10 times greater than a dopant concentration of said substrate

23. The method of claim 12, further including simultaneously with fabricating said diode, fabricating a field effect transistor, a bipolar transistor a SiGe bipolar transistor or combinations thereof in said substrate.

24. A diode, comprising: a first doped region having opposite first and second sides, said first doped region extending from a top surface of a silicon substrate a first distance into said substrate;a second doped region having opposite first and second sides, said second doped region extending from said top surface of a silicon substrate a second distance into said substrate, said first and second doped regions separated by a dielectric region extending from said top surface of said substrate a third distance into said substrate and by a region of said substrate under said dielectric layer and between said first sides of said first and second doped regions, said first side of said first doped region opposite said first side of said second doped region, said third distance less than said first or second distances;a first trench having opposite first and second sidewalls and extending from said top surface of said substrate a fourth distance into said substrate, said first sidewall of said first trench abutting said second side of said first doped region;a second trench having opposite first and second sidewalls and extending from said top surface of said substrate said fourth distance into said substrate, said first sidewall of said second trench abutting said second side of said second doped region; anda first region of a metal silicide layer on a top surface of said first doped region and on said second side of said first doped region and a second region of said metal silicide layer on a top surface of said second doped region and on said second side of said second doped region, said first and second regions of said metal silicide layer electrically isolated from each other by said dielectric region.

25. The diode of claim 24, further including: a dielectric layer filling said first and second trenches and covering said metal silicide layer and said dielectric region;a first electrically conductive contact extending from a top surface of said dielectric layer, through said dielectric layer to said first region of said metal silicide layer, said first electrically conductive contact in direct physical and electrical contact with said first region of said metal silicide layer; anda second electrically conductive contact extending from said top surface of said dielectric layer, through said dielectric layer to said second region of said metal silicide layer, said second electrically conductive contact in direct physical and electrical contact with said second region of said metal silicide layer.

26. The diode of claim 24, wherein said first region of said metal silicide layer extends over a bottom of said first trench and said second region of said metal silicide layer extends over a bottom of said second trench.

27. The diode of claim 24, wherein said metal silicide is selected from the group consisting of tungsten silicide, molybdenum silicide, tantalum silicide, cobalt silicide, titanium silicide, nickel silicide and platinum silicide.

28. The diode of claim 24, wherein: said first doped region is doped N-type, said second doped region is doped P-type and said substrate is doped P-type or is intrinsic, concentration of dopants in respective first and second doped regions significantly higher than a dopant concentration of said substrate.

29. A method of fabricating a diode, comprising: forming a first doped region in a silicon substrate, said first doped region having opposite first and second sides, said first doped region extending from a top surface of said substrate a first distance into said substrate;forming a second doped region in said substrate, said second doped region having opposite first and second sides, said second doped region extending from said top surface of a silicon substrate a second distance into said substrate, said first and second doped regions separated by a dielectric region extending from said top surface of said substrate a third distance into said substrate and by a region of said substrate under said dielectric layer and between said first sides of said first and second doped regions, said first side of said first doped region opposite said first side of said second doped region, said third distance less than said first or second distances;forming a first trench in said substrate, said first trench having opposite first and second sidewalls and extending from said top surface of said substrate a fourth distance into said substrate, said first sidewall of said first trench abutting said second side of said first doped region;forming a second trench in said substrate, said second trench having opposite first and second sidewalls and extending from said top surface of said substrate said fourth distance into said substrate, said first sidewall of said second trench abutting said second side of said second doped region; andforming a first region of a metal silicide layer on a top surface of said first doped region and on said second side of said first doped region and forming a second region of said metal silicide layer on a top surface of said second doped region and on said second side of said second doped region, said first and second regions of said metal silicide layer electrically isolated from each other by said dielectric region.

30. The method of claim 29, further including: filling said first and second trenches and covering said metal silicide layer and said dielectric region with a dielectric layer;forming a first electrically conductive contact in said dielectric layer, said first electrically conductive contact extending from a top surface of said dielectric layer, through said dielectric layer to said first region of said metal silicide layer, said first electrically conductive contact in direct physical and electrical contact with said first region of said metal silicide layer; andforming a second electrically conductive contact in said dielectric layer, said second electrically conductive contact extending from said top surface of said dielectric layer, through said dielectric layer to said second region of said metal silicide layer, said second electrically conductive contact in direct physical and electrical contact with said second region of said metal silicide layer.

31. The method of claim 29, wherein said first region of said metal silicide layer extends over a bottom of said first trench and said second region of said metal silicide layer extends over a bottom of said second trench.

32. The method of claim 29, wherein said metal silicide is selected from the group consisting of tungsten silicide, molybdenum silicide, tantalum silicide, cobalt silicide, titanium silicide, nickel silicide and platinum silicide.

33. The method of claim 29, wherein: said first doped region is doped N-type, said second doped region is doped P-type and said substrate is doped P-type or is intrinsic, concentration of dopants in respective first and second doped regions at least about 10 times greater than a dopant concentration of said substrate.

34. The method of claim 29, further including simultaneously with fabricating said diode, fabricating a field effect transistor, a bipolar transistor a SiGe bipolar transistor or combinations thereof in said substrate.