Patent Application
20170338376
The present invention relates to a layered body. The present application claims a priority based on Japanese Patent Application No. 2015-216008 filed on Nov. 2, 2015, the entire content of which is incorporated herein by reference.
A semiconductor layered body including a semiconductor layer composed of a group III nitride can be used for production of a light emitting device. Specifically, for example, a light emitting device for emitting ultraviolet light can be obtained by providing an AlN layer, an n type AlGaN layer, a quantum well structure, and a p type AlGaN layer in this order on a sapphire substrate and forming an appropriate electrode (for example, see Non-Patent Document 1).
NPD 1: M. Kneissl, et al., “Advances in group III-nitride-based deep UV light-emitting diode technology”, Semicond. Sci. Technol. 26 (2011) 014036
A layered body according to the present invention includes: a plate-like supporting body having a supporting main surface; and a plurality of projection portions disposed on the supporting main surface, each of the plurality of projection portions being composed of a group III nitride and having a dislocation density of not more than 1×108 cm−3.
In the structure disclosed in Non-Patent Document 1, it is difficult to sufficiently reduce the dislocation density of the AlN layer formed on the sapphire substrate. This results in low crystallinity of the semiconductor layer including the quantum well structure formed on the AlN layer. As a result, it is difficult to provide the light emitting device with a sufficient light emitting property, disadvantageously. In view of the above, it is one of objects to provide a layered body usable for production of a light emitting device having an excellent light emitting property.
According to the layered body, there can be provided a layered body usable for production of a light emitting device having an excellent light emitting property.
First, embodiments of the invention of the present application are listed and described. A layered body of the present application includes: a plate-like supporting body having a supporting main surface; and a plurality of projection portions disposed on the supporting main surface, each of the plurality of projection portions being composed of a group HI nitride and having a dislocation density of not more than 1×108 cm−3.
In the layered body of the present application, the plurality of projection portions are disposed on the supporting main surface of the supporting body. Therefore, the semiconductor layer can be formed on the plurality of projection portions by epitaxial growth to connect the plurality of projection portions to one another. In this way, a region not in contact with the projection portions is formed on the main surface of the semiconductor layer at the projection portion side so as to correspond to a portion between adjacent projection portions (groove between the adjacent projection portions) when viewed in a plan view. Accordingly, a stress resulting from a difference in lattice constant between each projection portion and the semiconductor layer is released in the region. Therefore, the crystallinity of the semiconductor layer is suppressed from being deteriorated due to the difference in lattice constant between the projection portion and the semiconductor layer. The dislocation density of the projection portion is reduced to not more than 1×108 cm−3, thereby obtaining a semiconductor layer having a reduced dislocation density. As a result, when another semiconductor layer including a quantum well structure is formed on the semiconductor layer, a quantum well structure excellent in crystallinity is obtained. The quantum well structure excellent in crystallinity contributes to improvement in light emitting property. Thus, according to the layered body of the present application, there can be provided a layered body usable for production of a light emitting device having an excellent light emitting property.
In the layered body, the projection portion may have a polygonal planar shape. This facilitates formation of a continuous semiconductor layer on the projection portions in the lateral direction (direction along the main surface of the projection portion).
In the layered body, when viewed in a plan view, adjacent projection portions may have sides facing each other and having lengths 2 √{square root over (3)} times or more as large as a distance between the adjacent projection portions. This facilitates formation of a continuous semiconductor layer on the projection portions in the lateral direction (direction along the main surface of the projection portion).
In the layered body, when viewed in a plan view, there may be not more than two corner portions of the projection portions facing each other. This facilitates formation of a continuous semiconductor layer on the projection portions in the lateral direction (direction along the main surface of the projection portion).
In the layered body, the projection portion may have a plate-like shape. This facilitates formation of a continuous semiconductor layer on the projection portions in the lateral direction (direction along the main surface of the projection portion).
In the layered body, each of the plurality of projection portions may have a main surface opposite to the supporting body and corresponding to a {0001} plane of the group III nitride of the projection portions. The adjacent projection portions of the plurality of projection portions may have end surfaces facing each other and corresponding to a {11-20} plane of the group III nitride of the projection portions. This facilitates formation of a continuous semiconductor layer on the projection portions in the lateral direction (direction along the main surface of the projection portion).
In the layered body, when viewed in a plan view, the supporting body may have a region overlapping with the projection portions and having an area ratio of not less than 30% and not more than 90%. When the area ratio of the region overlapping with the projection portions is less than 30%, it becomes difficult to form the semiconductor layer to connect the plurality of projection portions to one another. On the other hand, when the area ratio of the region overlapping with the projection portions is more than 90%, the stress resulting from the difference in lattice constant between each projection portion and the semiconductor layer is not sufficiently released. When the area ratio of the region overlapping with the projection portions is set at not less than 30% and not more than 90%, it is possible to facilitate formation of the semiconductor layer to connect the plurality of projection portions to one another while sufficiently releasing the stress resulting from the difference in lattice constant between each projection portion and the semiconductor layer.
In the layered body, the supporting body may include: a plate-like base body, and a dielectric film disposed on one main surface of the base body. A main surface of the dielectric film opposite to the base body may be the supporting main surface. By employing such a structure, the layered body can be readily produced.
In the layered body, the dielectric film may be composed of one or more compounds selected from a group consisting of SiO2 (silicon dioxide), SiON (silicon oxynitride), SiN (silicon nitride), TiN (titanium nitride), HfO (hafnium oxide), TiO2 (titanium dioxide), ZrO2 (zirconium dioxide), Al2O3 (aluminum oxide), or Ga2O3 (gallium oxide). These materials are suitable as a material for the dielectric film.
In the layered body, the base body may be composed of mullite, anorthite, molybdenum, silicon, aluminum nitride, or silicon carbide. These materials are suitable as a material for the base body.
In the layered body, when viewed in a plan view, the projection portions may be disposed at a cycle of not more than 10 μm. In this way, the crystallinity of the semiconductor layer formed on the projection portions can be improved further.
In the layered body, the projection portion may have a thickness of not more than 10 μm. Even though a thickness of more than 10 μm is not secured, the stress resulting from the difference in lattice constant between the projection portion and the semiconductor layer can be sufficiently released. Moreover, the thickness of the projection portion is preferably not less than 10 nm. Accordingly, the stress can be released more securely. Furthermore, the thickness of the projection portion is more preferably not less than 100 nm. Accordingly, the stress can be released much more securely.
Next, the following describes a first embodiment, which is one embodiment of a layered body according to the present invention with reference to figures. It should be noted that in the below-mentioned figures, the same or corresponding portions are given the same reference characters and are not described repeatedly.
With reference to
Supporting body 10 includes a base body 11 and a dielectric film 12. Supporting body 10 has a supporting main surface 10A. Base body 11 has a plate-like shape. Base body 11 has a disc-like shape, for example. Base body 11 has a diameter of not less than 50 mm, for example. The diameter of base body 11 may be not less than 100 mm, or may be not less than 150 mm. Base body 11 can be composed of mullite, anorthite, molybdenum, silicon, aluminum nitride, or silicon carbide, for example.
Dielectric film 12 is disposed on and in contact with one main surface of base body 11. Dielectric film 12 may be constituted of a dielectric composed of one or more compounds selected from a group consisting of SiO2, SiON, SiN, TiN, HfO, TiO2, ZrO2, Al2O3, or Ga2O3, for example. A main surface of dielectric film 12 opposite to base body 11 is supporting main surface 10A of supporting body 10.
Each of projection portions 20 projects from a reference plane 99. Supporting main surface 10A of supporting body 10 overlaps with reference plane 99. That is, a plane including supporting main surface 10A coincides with reference plane 99. Projection portion 20 has a first main surface 21, a second main surface 22, and end surfaces 23. First main surface 21 and second main surface 22 correspond to a {0001} plane of the crystal of projection portion 20, for example. End surface 23 corresponds to a {11-20} plane of the crystal of projection portion 20, for example. All the end surfaces 23 may correspond to the {11-20} plane of the crystal of projection portion 20. First main surface 21 is along reference plane 99. On first main surface 21, projection portion 20 is in contact with supporting main surface 10A of supporting body 10. Respective end surfaces 23 of adjacent projection portions 20 facing each other define a groove portion 29. That is, groove portion 29 is a region (space) interposed between end surfaces 23 of adjacent projection portions 20. Projection portion 20 has a thickness of not more than 10 μm, for example.
Projection portion 20 is constituted of a single crystal having a dislocation density of not more than 1×108 cm−3 and composed of aluminum (Al) and nitrogen (N), or aluminum, gallium (Ga) and nitrogen (N). That is, projection portion 20 is composed of a single crystal of a group III nitride expressed by a composition formula of AlxGa1-xN and satisfying 0≦x<1. The plurality of projection portions 20 are disposed at an equal interval. Each projection portion 20 has the same shape. Projection portion 20 has a plate-like shape. Projection portion 20 has a polygonal shape when viewed in a plan view. That is, projection portion 20 has a polygonal prism shape. The dislocation density thereof can be measured by an etch pit method.
With reference to
As the planar shape of projection portion 20 in the present embodiment, another shape can be employed. With reference to
With reference to
With reference to
In base layered body 1, the plurality of projection portions 20 are disposed on supporting main surface 10A of supporting body 10. Therefore, a semiconductor layer can be formed through epitaxial growth on the plurality of projection portions 20 to connect the plurality of projection portions 20 to one another. In this way, a region not in contact with projection portions 20 is formed on the main surface of the semiconductor layer at the projection portion 20 side so as to correspond to a portion between adjacent projection portions 20 (groove 29 between adjacent projection portions 20) when viewed in a plan view. Accordingly, a stress resulting from a difference in lattice constant between projection portion 20 and the semiconductor layer is released in the region. Therefore, the crystallinity of the semiconductor layer is suppressed from being deteriorated due to the difference in lattice constant between projection portion 20 and the semiconductor layer. The dislocation density of projection portion 20 is reduced to not more than 1×108 cm−3, thereby obtaining a semiconductor layer having a reduced dislocation density. As a result, when another semiconductor layer including a quantum well structure is formed on the semiconductor layer, a quantum well structure excellent in crystallinity is obtained.
With reference to
In base layered body 1, when viewed in a plan view, there are preferably not more than two corner portions 25 of the projection portions facing each other as shown in
Moreover, when viewed in a plan view, supporting body 10 preferably has a region overlapping with projection portions 20 and having an area ratio of not less than 30% and not more than 90%. This facilitates formation of the semiconductor layer on the projection portions to connect the plurality of projection portions 20 to one another while sufficiently releasing the stress resulting from the difference in lattice constant between each projection portion 20 and the semiconductor layer.
Next, with reference to
With reference to
Next, a mask layer forming step is performed as a step (S12). In this step (S12), with reference to
Next, a dry etching step is performed as a step (S13). In this step (S13), with reference to
A first semiconductor layer forming step is performed as a step (S21). In this step (S21), with reference to
With reference to
First semiconductor layer 30 has a first main surface 31 and a second main surface 32, which is a main surface opposite to first main surface 31. At first main surface 31, first semiconductor layer 30 is in contact with second main surface 22 of each of projection portions 20. First main surface 31 of first semiconductor layer 30 includes: a contact region 31A in contact with projection portion 20; and a noncontact region 31B not in contact with projection portion 20. When viewed in a plan view, contact region 31A corresponds to a region overlapping with projection portion 20 in first semiconductor layer 30. Noncontact region 31B faces supporting main surface 10A of supporting body 10 with groove portion 29, which is a space, being interposed therebetween.
Next, as steps (S31) to (S33), an n type semiconductor layer forming step, a quantum well structure forming step, and a p type semiconductor layer forming step are performed sequentially. In the step (S31), with reference to
In the step (S32), a quantum well structure 50 is formed on n type semiconductor layer 40 formed in the step (S31). Quantum well structure 50 can be formed by vapor phase epitaxy, for example. Quantum well structure 50 can be formed by alternately repeating formation of a quantum well layer 51 and formation of a barrier layer 52.
In the step (S33), a p type semiconductor layer 60 is formed on quantum well structure 50 formed in the step (S32). P type semiconductor layer 60 can be formed by vapor phase epitaxy, for example. In the steps (S21), (S31), (S32), and (S33), the respective formations can be performed through the vapor phase epitaxy continuously while changing source material gases. With the above procedure, a quantum well structure equipped semiconductor layered body 3 shown in
With reference to
N type semiconductor layer 40 is a semiconductor layer disposed on and in contact with second main surface 32 of first semiconductor layer 30. N type semiconductor layer 40 is composed of a group Ill nitride single crystal. Specifically, AlGaN having n type conductivity is employed as a material of n type semiconductor layer 40, for example. Si (silicon) can be employed as an n type impurity included in n type semiconductor layer 40, for example.
Quantum well structure 50 is disposed on and in contact with a first main surface 40A of n type semiconductor layer 40 opposite to its side facing first semiconductor layer 30. Quantum well structure 50 has a structure in which quantum well layers 51, which are composed of a group III-V semiconductor, and barrier layers 52 are alternately layered. Quantum well structure 50 is a light emitting layer that emits ultraviolet light.
P type semiconductor layer 60 is a semiconductor layer disposed on and in contact with main surface 50A of quantum well structure 50 opposite to the side facing n type semiconductor layer 40. P type semiconductor layer 60 is composed of a group III nitride single crystal. Specifically, for example, AlGaN having p type conductivity is employed as a material of p type semiconductor layer 60. As a p type impurity included in p type semiconductor layer 60, Mg (magnesium) can be employed, for example.
It should be noted that in the present embodiment, quantum well structure 50 is a multiple quantum well structure; however, a single quantum well structure can also be employed instead.
In semiconductor layered body 2 and quantum well structure equipped semiconductor layered body 3, first semiconductor layer 30 is disposed on the plurality of projection portions 20 projecting from reference plane 99, so as to connect the plurality of projection portions 20 to one another. By employing such a structure, noncontact region 31B, which is a region not in contact with projection portion 20, is formed at first main surface 31 of first semiconductor layer 30 so as to correspond to groove 29 between adjacent projection portions 20 when viewed in a plan view. Accordingly, the stress resulting from the difference in lattice constant between projection portion 20 and first semiconductor layer 30 is released in noncontact region 31B. Accordingly, the crystallinity of first semiconductor layer 30 is suppressed from being deteriorated due to the difference in lattice constant between projection portion 20 and first semiconductor layer 30. The dislocation density of projection portion 20 is reduced to not more than 1×108 cm−3, thereby obtaining first semiconductor layer 30 having a dislocation density of not more than 1×109 cm−3. As a result, when the second semiconductor layer including quantum well structure 50 is formed on first semiconductor layer 30, quantum well structure 50 having excellent crystallinity is obtained.
Next, a p side electrode forming step is performed as a step (S41). In this step (S41), with reference to
Next, a second supporting body bonding step is performed as a step (S42). In this step (S42), with reference to
Next, a supporting body removing step is performed as a step (S34). In this step (S34), with reference to
Next, an n side electrode forming step is performed as a step (S43). In this step (S43), an n side electrode 90 is formed in contact with noncontact region 31B of first main surface 31 of first semiconductor layer 30, noncontact region 31B being exposed due to the removal of supporting body 10 in the step (S34). N side electrode 90 can be formed by a deposition method, for example With the above procedure, a light emitting device 100 of the present embodiment can be manufactured. Then, for example, dicing is performed to separate into respective devices.
With reference to
N side electrode 90 is disposed on and in contact with noncontact region 31B of first semiconductor layer 30 of quantum well structure equipped semiconductor layered body 3. N side electrode 90 is composed of a conductor, such as a metal, capable of ohmic contact with first semiconductor layer 30. As the conductor of n side electrode 90, Ti (titanium)/Al (aluminum) can be employed, for example.
P side electrode 70 is disposed on and in contact with main surface 61 of p type semiconductor layer 60 of quantum well structure equipped semiconductor layered body 3 opposite to quantum well structure 50. P side electrode 70 is composed of a conductor, such as a metal, capable of ohmic contact with p type semiconductor layer 60. As the conductor of p side electrode 70, Ni (nickel)/Au (gold) can be employed, for example.
Second supporting body 82 is joined to p side electrode 70 with solder layer 81 interposed therebetween. Solder layer 81 can be composed of AuSn, which is an alloy of gold (Au) and tin (Sn), for example. Second supporting body 82 has a plate-like shape. Second supporting body 82 can be composed of CuW (copper tungsten alloy), Cu (copper), or the like, for example.
When voltage is forwardly applied to light emitting device 100, holes are injected from p type semiconductor layer 60 to quantum well structure 50 and electrons are injected from n type semiconductor layer 40 to quantum well structure 50. They are recombined in quantum well structure 50 to emit light. In the present embodiment, because quantum well structure 50 configured as above is employed, ultraviolet light is released.
Here, light emitting device 100 of the present embodiment includes quantum well structure 50 as a light emitting layer excellent in crystallinity as described above. Therefore, light emitting device 100 is a light emitting device having an excellent light emitting property (light emitting efficiency) and emitting ultraviolet light.
The dislocation density of first semiconductor layer 30 described above is preferably not more than 1×108 cm−3. Accordingly, quantum well structure 50 having more excellent crystallinity can be obtained.
Furthermore, in first semiconductor layer 30, it is preferable that the half width of an X-ray rocking curve of a (0002) plane, which is a symmetric plane, is not more than 800 arcsec and the half width of an X-ray rocking curve of a (10-12) plane, which is an asymmetric plane, is not more than 1500 arcsec. Accordingly, quantum well structure 50 having more excellent crystallinity can be obtained.
Next, the following describes a method for manufacturing another light emitting device using base layered body 1. A light emitting device 150 in a second embodiment can be manufactured by removing projection portion 20 and first semiconductor layer 30 in the method for manufacturing light emitting device 100 of the first embodiment and then forming an n side electrode.
Next, with reference to
Next, an n side electrode forming step is performed as a step (S43). In this step (S43), n side electrode 90 is formed in contact with the main surface of n type semiconductor layer 40 opposite to quantum well structure 50, the main surface being exposed due to the removal of first semiconductor layer 30 in the step (S36). N side electrode 90 can be formed by a deposition method, for example. With the above procedure, light emitting device 150 shown in
With reference to
With reference to
Light emitting device 150 is advantageous over the structure of the first embodiment in the following point: light (ultraviolet light) is avoided from being absorbed by projection portions 20 and first semiconductor layer 30.
By performing the steps (S11) to (S21) in the same procedure as in the first embodiment (see
With reference to Table 1, improved surface morphology is observed in Example A as compared with Comparative Example A. Moreover, the half widths of the X-ray rocking curves of the (0002) plane and (10-12) plane in Example A are improved to be less than ½ of those in Comparative Example A. Thus, according to the layered body of the present application, it is confirmed that the first semiconductor layer having excellent crystallinity is obtained to achieve an improved light emitting property of the light emitting device Since Example A is different from Comparative Example A in that group III nitride layer 120 is replaced with projection portions 20, it is considered that the improvement is attained because the stress resulting from the difference in lattice constant between each projection portion 20 and first semiconductor layer 30 is released in noncontact region 31B.
Light emitting device 150 shown in
With reference to
With reference to Table 2, the optical output of the light emitting device of Example B is increased by 20% as compared with the light emitting device of Comparative Example B. Accordingly, it is confirmed that by using the layered body of the present application, a light emitting device having excellent light emitting efficiency can be manufactured. Since the light emitting device of Example B has the quantum well structure, which is formed by the epitaxial growth, on the first semiconductor layer having excellent crystallinity, it is considered that higher light emitting efficiency was obtained as compared with Comparative Example B including the quantum well structure formed on the conventional sapphire substrate. Moreover, it is considered that the light emitting efficiency in Example B is improved also due to such a fact that causes of decrease in light emitting efficiency in the light emitting device of Comparative Example B, i.e., leakage current via the wall surface of the trench and decrease of the light emission region due to the formation of the trench are avoided in Example B.
It should be noted that in the present application, the state in which the projection portions are disposed at an equal interval and the state in which the projection portions have the same shape do not mean a geometrically completely equal interval and geometrically completely the same shape, but include errors inevitable in manufacturing. In other words, the state in which the projection portions are disposed at an equal interval and the state in which the projection portions have the same shape include a case where the inevitable errors are included as a result of manufacturing although the equal intervals and the same shape are intended to be attained.
It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in any respect. The scope of the present invention is defined by the terms of the claims, rather than the embodiments described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
1: base layered body; 2: semiconductor layered body; 3: quantum well structure equipped semiconductor layered body; 10: supporting body; 10A: supporting main surface; 11: base body; 12: dielectric film; 20: projection portion; 21: first main surface; 22: second main surface; 23: end surface; 25: corner portion; 28: group III nitride layer; 29: groove portion; 30: first semiconductor layer; 31: first main surface; 31A: contact region; 31B: noncontact region; 32: second main surface; 40: n type semiconductor layer; 40A: first main surface; 50: quantum well structure; 50A: main surface; 51: quantum well layer; 52: barrier layer; 60: p type semiconductor layer; 61: main surface; 70: p side electrode; 71: main surface; 81: solder layer; 82: second supporting body; 90: n side electrode; 91: mask layer; 92: opening; 99: reference plane; 100: light emitting device; 150: light emitting device.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-216008 | Nov 2015 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2016/082116 | 10/28/2016 | WO | 00 |
