Patent Application
20230245884
This application claims priority to GB Application No. 2201241.3, filed Jan. 31, 2022, which is hereby incorporated herein in its entirety by reference.
A layered structure, particularly but not exclusively for a radio frequency (RF) switch.
It is known from US 2021/020436 to provide a layered structure including a porous layer which is fully depleted of charge carriers. The substrate (starting material) is porosified to remove all charge carriers and therefore raise the resistivity of the resultant porous layer to over 10,000 ohm-centimeters (Ω·cm). An advantage of the high porosity layer is that it is a very good electrical insulator and is therefore suitable for high frequency switching applications. One disadvantage of this structure is that the high resultant porosity exposes different crystal orientations on the inner surfaces of the pores so that it is difficult to grow a high quality, low defect, single crystal layer over the porous layer.
The present invention provides a layered structure comprising: a substrate; a porous layer; and an epitaxial semiconductor layer; wherein the porous layer has a first porosity greater than 30% proximal to the substrate and a second porosity less than or equal to 25% adjacent to the semiconductor layer.
The porous layer having two different porosities is advantageous because each porosity can be optimized for different functions. The higher porosity proximal to the substrate is effective at insulating the semiconductor from the substrate (harmonic performance). The lower porosity adjacent to the semiconductor layer provides a crystalline structure with single crystal orientation exposed that supports the semiconductor layer comprising high quality, low defect, epitaxial growth.
Advantageously the lower porosity portion is also a good thermal conductor, since more of the volume is filled with material and not air (or another fluid) in the pores. Thus the layered structure is able to transport the additional heat generated in the channel layer by high frequency switching better than prior layered structures.
The substrate may comprise silicon. Advantageously silicon based semiconductors are well established.
The substrate may have crystal orientation <100>, <110> or <111>. Alternatively the substrate may be in a first crystal orientation miscut towards a second crystal orientation by up to 20°. For example it may be <100> miscut towards the <111> orientation by 5°, 6°, 10°, 15°, or up to 20°. Advantageously the layered structure does not depend on a particular crystal orientation for the substrate meaning the orientation can be selected to suit the intended application.
The substrate may have a resistivity between 0.01 Ω·cm and 10 Ω·cm. Advantageously this is a common range of resistivity and so such a substrate can be processed in conventional foundries to produce the layered structure or subsequently to process the layered structure into devices.
The porous layer may comprise a group IV material or a compound of group IV elements. Advantageously such materials are compatible with a silicon substrate meaning that little or no strain is introduced between the substrate and porous layer due to lattice mismatch.
The porous layer may comprise silicon, germanium, carbon, silicon germanium, or silicon germanium tin. Advantageously the porous layer can be matched to the substrate and/or semiconductor layer. Alternatively, the porous layer may comprise a different material or compound to the semiconductor layer so that a small strain is introduced which improves carrier mobility.
The porous layer may be doped. The doping may have a graded profile through the porous layer from the substrate to the semiconductor layer. Advantageously a graded doping profile offers the benefits of the two different porosities whilst having no sharp interface which may introduce an undesirable spike in the band structure which may give undesirable device harmonic characteristics. Grading smooths the band structure thereby avoiding such discontinuities. Alternatively the porous layer may be doped with a first level of doping proximal to the substrate and a second level of doping adjacent to the semiconductor layer. Advantageously the properties of the two regions can be accurately controlled by the two doping levels.
The porous layer may have a resistivity greater than or equal to 3000 Ω·cm. Advantageously such resistivity range results in second harmonics less than −100 dBm with 15 dBm input power.
The semiconductor layer may comprise a group IV material, a compound of group IV elements, a compound of group III and group V elements, or a compound of one or more rare earth elements with group III and group V elements. Advantageously, this allows the optimal channel layer to be chosen to meet the specific device performance required. The semiconductor layer may comprise silicon, germanium, silicon germanium, silicon germanium tin, a III-N compound, gallium nitride, or a rare earth-III-N alloy. Advantageously the material can be the same as the porous layer. For example, the substrate, porous layer and semiconductor layer may all comprise silicon which forms a mono-elemental structure. Alternatively the material can be different to the porous layer. Advantageously a defined level of strain can be introduced which improves the carrier transport through the semiconductor layer, for example when the layered structure is implemented in an RF switch.
The semiconductor layer may have an RMS surface roughness of less than 1 nm. Advantageously such a surface is very smooth meaning that excellent device characteristics, such as high carrier mobility, are possible.
The semiconductor layer may have a resistivity greater than or equal to 10 Ω·cm. Advantageously this results in good carrier transport (device harmonic performance).
The semiconductor layer may comprise a channel layer and the layered structure may further comprise a source, a drain and a gate. Such a structure forms a field effect transistor (FET). Advantageously the layered structure is suitable for processing into a switch, for example a radio frequency switch operating at mobile communications frequencies. For example, it may operate in the range 800 MHz to 6 GHz or higher.
The present invention also provides a method of fabricating a layered structure comprising steps to: grow an epitaxial layer on a substrate, wherein the epitaxial layer has a first resistivity proximal to the substrate and a second resistivity distal from the substrate, and wherein the second resistivity is less than the first resistivity; porosify the epitaxial layer to form a porous layer with porosity greater than 30% proximal to the substrate and porosity less than or equal to 25% distal from the substrate; and epitaxially grow a semiconductor layer over the porous layer.
Advantageously the resulting layered structure has two regions with different porosity which exhibit different properties. Advantageously the method is simpler than known methods of fabricating a semiconductor over an insulator which require fabrication and bonding of two sections. Advantageously the regions of higher and lower porosity can be optimized for thermal and harmonic performance by setting the resistivity of the epitaxial layer during the growth step.
The method may further comprise doping the epitaxial layer during the step to grow the epitaxial layer. Advantageously levels of doping can be precisely controlled and varied during the growth step to set the first resistivity proximal to the substrate and the second resistivity distal therefrom, adjacent to the surface on which the semiconductor layer is subsequently grown.
The doping may comprise doping the epitaxial layer with a lower level of dopant proximal to the substrate than adjacent to the semiconductor layer. Advantageously this results in a higher resistivity proximal to the substrate than adjacent to the semiconductor layer since resistivity is inversely proportional to doping concentration.
The method may further comprise a step to ion implant at least part of the epitaxial layer prior to the step to porosify the epitaxial layer. The ion implantation may be additional or alternative to the doping of the epitaxial layer during growth. The ion implantation may decrease the resistivity of the implanted portion of the epitaxial layer. Thus it may be applied adjacent to the semiconductor layer but not proximal to the substrate. Advantageously ion implantation can be applied in precise patterns laterally and vertically through the layer.
The step to porosify the epitaxial layer may further comprise porosifying at least an upper part of the substrate, wherein the upper part of the substrate has the first resistivity. Advantageously the epitaxial layer may be thinner because part of the porous layer is formed in the substrate instead of the epitaxial layer, which is quicker and therefore cheaper to grow. Advantageously the final substrate, and layered structure, is thinner which may simplify fabrication and thus reduce cost. The resistivity of the upper part of the substrate may be set by doping or ion implantation. All of the substrate may have the same resistivity or only the upper part have the first resistivity.
The method may further comprise a step to provide a source, a drain and a gate over the semiconductor layer to form a switch, wherein the semiconductor layer forms a channel layer. The method may further comprise a step to provide a source, a drain and a gate over the semiconductor layer to form a radio frequency switch, wherein the semiconductor layer forms a channel layer. The switch may be suitable to operate at frequencies of 800 MHz to 6 GHz or higher. The source and drain may be provided by diffusing or ion implanting a region into the top of the channel layer using a mask. Advantageously the channel layer is a high quality, low detect epitaxial layer and is therefore suitable for high frequency operation. Advantageously the porosity of the porous layer proximal to the substrate is a good insulator between the channel and substrate. Advantageously at least some of the porous layer is a good thermal conductor.
The present invention will be more fully described by way of example with reference to the accompanying drawings, in which:
Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metal-organic vapor phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapor deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition.
Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapor deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer.
A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a III-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus Al0.25Ga0.75As means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As.
Crystalline means a material or layer with a single crystal orientation. In epitaxial growth or deposition subsequent layers with the same or similar lattice constant follow the registry of the previous crystalline layer and therefore grow with the same crystal orientation. In-plane is used herein to mean parallel to the surface of the substrate; out-of-plane is used to mean perpendicular to the surface of the substrate.
Throughout this disclosure, as will be understood by the skilled reader, crystal orientation <100> means the face of a cubic crystal structure and encompasses [100], [010] and [001] orientations using the Miller indices. Similarly <0001> encompasses [0001] and [000-1] except if the material polarity is critical. Integer multiples of any one or more of the indices are equivalent to the unitary version of the index. For example, (222) is equivalent to, the same as, (111).
Substrate means a planar wafer on which subsequent layers may be deposited or grown. A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb).
A substrate may be on-axis, that is where the growth surface aligns with a crystal plane. For example it has <100> crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane.
Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction.
Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type.
Lattice matched means that two crystalline layers have the same, or similar, lattice spacing and so the second layer will tend to grow isomorphically on the first layer. Lattice constant is the unstrained lattice spacing of the crystalline unit cell. Lattice coincident means that a crystalline layer has a lattice constant which is, or is close to, an integer multiple of the previous layer so that the atoms can be in registry with the previous layer. Lattice mismatch is where the lattice constants of two adjacent layers are neither lattice matched nor lattice coincident. Such mismatch introduces elastic strain into the structure, particularly the second layer, as the second layer adopts the in-plane lattice spacing of the first layer. The strain is compressive where the second layer has a larger lattice constant and tensile where the second layer has a smaller lattice constant.
Where the strain is too great the structure relaxes to minimize energy through defect generation, typically dislocations, known as slip, or additional interstitial bonds, each of which allows the layer to revert towards its lattice constant. The strain may be too great due to a large lattice mismatch or due to an accumulation of small mismatches over many layers. A relaxed layer is known as metamorphic, incoherent, incommensurate or relaxed, which terms are also commonly interchangeable.
A pseudomorphic system is one in which a single-crystal thin layer overlies a single-crystal substrate and where the layer and substrate have similar crystal structures and nearly identical lattice constants. In a pseudomorphic structure the in-plane lattice spacing of the thin layer adopts the in-plane lattice constant of the substrate and is therefore elastically strained, either compressively where the layer has a larger lattice spacing than the substrate or tensilely where the layer has a smaller lattice spacing than the substrate. A pseudomorphic structure is not constrained in the out-of-plane direction and so the lattice spacing of the thin layer in this direction may change to accommodate the strain generated by the mismatch between lattice spacing. The thin layer may alternatively be described as “coherent”, “commensurate”, “strained” or “unrelaxed”, which terms are often used interchangeably. In a pseudomorphic structure all the layers adopt the lattice spacing of the substrate in their respective in-plane lattice spacing.
A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayers. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and/or through the thickness of the layer (horizontally and/or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and/or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function.
A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that 25% of the equivalent volume of bulk material is voided.
A fully depleted porous layer means a layer in which there are no charge carriers.
A crystalline bixbyite oxide layer may be a rare earth oxide layer. The rare earth elements are scandium (Sc), yttrium (Y) and all of the lanthanoid series which is lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb) and lutetium (Lu). The bixbyite oxides are bixbyite in crystal structure. Other bixbyite oxides include indium oxide (In2O3), vanadium oxide (V2O5), iron oxide (Fe2O3), manganese oxide (Mn2O3) and ternary compounds of a rare earth, a metal and oxygen (RE-M-O).
Where a device is described it should be understood that it will typically be formed on a circular substrate water of 4″ (100 mm), 6″ (150 mm), 8″ (200 mm), 12″ (300 mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (components or chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer.
For example, the insulator 14 may comprise a thick polycrystalline silicon layer with a buried oxide layer, e.g. silicon dioxide (SiO2), over it. In combination with a high resistivity substrate 12, for example with resistivity greater than 3000 Ω·cm, this insulator 14 separates the harmonic performance of the channel 16 from the substrate 12. One disadvantage of a buried oxide is that the resistivity is limited and the permittivity is relatively high meaning that there can be cross-talk between proximal devices. One disadvantage of a polycrystalline silicon and buried oxide insulator 14 is that a complex multi-step fabrication process is required to form the device since a crystalline silicon channel 16 cannot be grown over polycrystalline or amorphous structures. A further disadvantage is that a high resistivity substrate 12 is required which is expensive and may be difficult to process in some fabrication environments.
The invention will now be described more particularly with reference to
The substrate 26 may be p-type or n-type by appropriate doping. A p-doped Si substrate 26 that is heavily doped, for example with 5e18-1e19 cm−3 dopant impurity concentration, may be referred to as a p+ substrate 26 whereas a lightly doped Si substrate 26, for example with less than or equal to 5e15 cm−3 carriers, may be referred to as a p− substrate 26. A p+ substrate 26 that is doped at 5e18-1e19 cm−3 has a resistivity around 0.01 Ω·cm to 0.02 Ω·cm.
Grown on or over the substrate 26 is an insulator 28. The insulator 28 comprises porous silicon which is formed from epitaxially grown silicon as will be described. The insulator 28 may comprise two sublayers 30, 32 with different porosities. The first sublayer 30, which is directly on or over the substrate 26, comprises a higher porosity, for example 30-60%, 30-40% or 35-40%, than the second sublayer 32 which is grown on or over it and which has a porosity less than 25%. The insulator 28 also has a high resistivity, for example greater than or equal to 3000 Ω·cm. The higher porosity first sublayer 30 has a higher resistivity than the lower porosity second sublayer 32. For example the first sublayer 30 may have a resistivity of 10,000 Ω·cm, 25,000 Ω·cm or even higher.
The porous Si having two different porosities means that it combines different beneficial properties. The higher porosity first sublayer 30 is an excellent insulator because the porosification process depletes most or all of the carriers so that it becomes non-conductive, that is not electrically conductive. The lower porosity second sublayer 32 retains the crystalline structure of the epitaxial layer from which it is formed and therefore subsequent layers can be grown epitaxially with very low defect generation or propagation. The second sublayer 32 also has the required thermal properties since it has a higher proportion of the original epitaxial material which has significantly higher thermal conductivity as compared to the porous voids. By appropriate design of the first sublayer 30 and second sublayer 32, the insulator 28 may have thermal conductivity of 3 W·m−1·K−1 or greater, of 5 W·m−1·K−1 or greater, of 10 W·m−1·K−1 or greater, or of another value.
The porous Si insulator 28 may be several microns thick. For example it may be 3 μm thick, 4 μm thick, 5 μm thick, 10 μm thick, 20 μm thick or another thickness. The thickness of the first sublayer 30 and the second sublayer 32 can be selected so that the desired properties are present. Thus the first sublayer 30 may be thick enough to insulate fully and the second sublayer 32 can be thick enough to provide the thermal conductivity and crystalline structure for subsequent growth.
On or over the insulator 28 is a semiconductor layer 34. The semiconductor layer 34 comprises epitaxially grown silicon, for example 50-1000 nm, or more narrowly, 50-500 nm, 50-200 nm, 50-75 nm, 50-150 nm, 100-250 nm, 150-500 nm or 500-1000 nm of silicon. The thickness is set by the desired performance of a device fabricated in, over or from the semiconductor layer 34 but the trend is for the semiconductor layer 34 to need to be thinner relative to the previous generation of devices. The semiconductor layer 34 has a low RMS surface roughness, for example less than or equal to 1 nm. The semiconductor layer 34 also has a resistivity greater than a threshold value in order to exhibit appropriate transport properties for the device grown over the layered structure 24. For example the resistivity threshold value may be 10 Ω·cm, 5 Ω·cm, 20 Ω·cm or another value suitable for the specific application contemplated.
The semiconductor layer 34 is high quality, low defect, silicon because it is epitaxially grown. It is therefore particularly suitable to be a channel layer for an RF switch operating at very high speed as it exhibits excellent high frequency performance. The first sublayer 30 of the insulator 28 has a high enough porosity that it is significantly depleted of charge carriers, and may be fully depleted of carriers. It therefore operates as an effective insulator to isolate the channel layer 34 from the substrate 26. This means that there are no parasitic currents which can flow through the insulator 28, particularly the first sublayer 30 of the insulator 28, and that all the current flows through the channel layer 34. This layered structure 24 is characterized by excellent overall harmonic performance. For example, the second harmonic 2 F0 may be less than −100 dBm at 15 dBm input power, typically measured via a coplanar waveguide structure, which is excellent harmonic performance.
The second sublayer 32 of the insulator 28 has a low enough porosity that the crystalline structure is maintained. This enables the high quality crystalline semiconductor layer 34 to be epitaxially grown over the second sublayer 32. The different levels of porosity in the first and second sublayers 30, 32 may be achieved through the use of different levels of dopant or ion implantation.
The interface between the semiconductor layer 34 and the insulator 28 is high quality because of the crystallinity of the second sublayer 32 of the porous layer 28. This means that it does not act as a loss mechanism for a switch formed using the layered structure 24. This becomes more important for thinner semiconductor layers 34 for future devices since the interface thickness is a larger proportion of the semiconductor layer thickness and so any losses are proportionately larger.
The thermal characteristics of the layered structure 24 are important because when the switch in the device region 36 is operated it generates heat. If this is not dissipated sufficiently the device heats up during operation and the device characteristics may change. For example the device characteristics may drift out of specification. As switching speed demands increase more heat is generated and so thermal conductivity becomes more important. The porous insulator 28 described addresses this problem by providing the first sublayer 30 which has good harmonic performance whilst also providing the second sublayer 32 which has good crystallinity for subsequent epitaxial overgrowth (i.e. it provides crystal registry) and good thermal conductivity. The first sublayer 30 may also contribute to the thermal conductivity. Furthermore, the harmonic performance of the first sublayer 30 is substantially insensitive to the operating temperature.
The permittivity of the porous insulator 28 is lower than for silicon oxide, a common insulator based on silicon. Advantageously permittivity is responsible for cross-talk between proximal devices in operation and therefore the lower permittivity of the porous insulator 28 reduces cross-talk.
Porosifying the epitaxial layer 44 raises the resistivity of the resultant porous insulator 28 to greater than or equal to 3000 Ω·cm. The first and second sublayers 46, 48 of the epitaxial layer 44 may have resistivities of less than or equal to 10 Ω·cm, or even less than or equal to 1 Ω·cm, prior to porosification. For example the first sublayer 46 may have resistivity in the range 0.01-0.4 Ω·cm and the second sublayer 48 have resistivity in the range 0.4-10 Ω·cm. The higher the initial resistivity, the higher the final resistivity following porosification with a non-linear relationship therebetween. Thus the first sublayer 30 of the porous layer 28 may have resistivity of greater than or equal to 3000 Ω·cm and the second sublayer 32 may have resistivity significantly higher than this, for example greater than or equal to 10,000 Ω·cm.
Alternatively the second step in the method of fabricating the layered structure 24 may comprise porosifying only an upper portion of the epitaxial layer 44 to leave a part adjacent to the substrate 26 which is non-porosified epitaxial material, 29 as illustrated in
More particularly the porosification comprises placing the layered structure 24 of
In use the front side fluid chamber 74 and the back side fluid chamber 78 are filled with a fluid 76. The fluid 76 is chosen such that when a voltage is applied between the cathode 62 and anode 64 a current flows through from the cathode 62 to the front side 68 of the wafer 66 and from the back side 70 of the wafer 66 to the anode 64, as shown by the arrows 80. For example, the fluid 76 may be hydrofluoric acid. This current porosities the front side 68 of the wafer 66 by electrolysis. That is, it etches (tunnels) pores into the surface of the wafer 66 which extend approximately perpendicular to the surface thereby removing material from the wafer 66 in a semi-random pattern. The density of the wafer 66 is therefore reduced.
In a third step of the method of fabricating the layered structure 24, illustrated in
Optionally the semiconductor layer 34 is a channel layer and the method includes a further step to grow, deposit or bond the source 38, drain 40 and gate 42 over the channel layer 34 to form the device region 36.
Alternatively the porous layer 28 may comprise more than two sublayers, with an intermediate sublayer or sublayers having greater or lesser porosity than the layers on either side of it. For example, there may be three sublayers with the middle sublayer having higher porosity than either the lower or upper sublayers; or with the middle sublayer having intermediate porosity between the upper and lower sublayers; or with the middle sublayer having lower porosity than the upper or the lower sublayers. Or there could be four sublayers with alternating porosity such that the lowest sublayer has high porosity, for example at least 30%, the next sublayer has lower porosity, for example ≤25%, the next sublayer has the same porosity as the lowest sublayer and the top sublayer has the same porosity as the second sublayer. There could also be a non-porosified sublayer 29 between the lowest sublayer and the substrate 26. Other combinations of sublayers and grading profiles will be apparent to the skilled reader.
The layered structure 24 may be implemented wholly in silicon as described above. Alternatively the insulative porous layer 28 may comprise a different group IV material, such as germanium (Ge), or a compound of silicon with one or more other group IV elements. For example, it may comprise silicon germanium (SiGe) or silicon germanium tin (SiGeSn). If the semiconductor layer 34 is pure silicon there may be a small lattice mismatch between the top of the porous layer 44 and the semiconductor layer 34. This introduces a small amount of strain into the semiconductor layer 34 which may improve carrier transport characteristics, i.e. carrier mobility, relative to an unstrained layer.
Additionally or alternatively the semiconductor layer 34 may comprise another group IV, such as germanium, or a compound of group IV elements such as silicon germanium or silicon germanium tin. As with changing the material of the porous layer 28 this enables a small strain to be introduced to the semiconductor layer 34, by introducing a controlled lattice mismatch, and therefore improves carrier mobility.
Alternatively the semiconductor layer 34 may comprise a compound of a group III and a group V material. For example the semiconductor layer 34 may comprise a III-N material such as gallium nitride (GaN). Such a material may have applications for electronic devices (e.g. a field effect transistor, FET) or photonic devices (e.g. μLEDs). In some applications a GaN semiconductor layer 34 may be grown over a porous layer 28 which is grown over a Si <111> substrate. The semiconductor layer 34 may also comprise a rare earth material in compound with a group III and a group V material. For example it may comprise a rare-earth-III-N compound.
The insulator 28 has been described with doping of the epitaxial layer 44 during growth in order to achieve the required resistivity. However, ion implantation may be used instead, prior to the porosification of the epitaxial layer 44, to achieve the same levels of resistivity close to the substrate 26 and close to the semiconductor layer 34. For example the epitaxial layer 44 may be doped with the same level of dopant throughout its thickness and then the upper part, adjacent the semiconductor layer 34, be ion implanted to raise the dopant level to give the lower resistivity porous. Alternatively two different amounts of ion implantation can be used distal from and close to the substrate 26, or a graded profile can be used. The ion implantation conductions can be chosen to give a dopant profile that approximately matches those achieved in epitaxial growth.
Although the porous layer 28 has been described as having two sublayers 30, 32 of different porosities, it could instead have three or more sublayers. For example, it could have four sublayers of alternating higher and lower porosity. Such a porous layer 28 can be formed from an epitaxial layer 44 having alternating higher and lower resistivity. Alternatively a first sublayer 30 of the porous layer 28 having higher porosity may be formed from the upper part 54 of the substrate 26 and then a further three sublayers with the lower, higher and lower porosities respectively may be formed from the epitaxial layer 44.
Devices, for example 5G mobile phones, follow a trend of increasing functionality which leads to more stringent requirements on efficiency to minimize signal and power loss with consequential preservation of battery life. Increased functionality also leads to higher frequency which implies a need for improved harmonics and thus a thicker insulator 28 is required to isolate the substrate 26 from the semiconductor layer 34 more effectively. The insulator 28 can be as thick as needed because the porous process is not inherently depth limited but can be controlled by doping level, current density, electrolytic concentration or time. Furthermore, a high quality semiconductor layer 34 can be achieved regardless of the thickness of the insulator 28 because it is dependent on the quality of the epitaxial layer 44 and the preserved crystallinity due to the lower porosity of the second sublayer 32.
By contrast prior methods including a silicon oxide insulator cannot be made thicker because these methods require hydrogen implantation to enable a cleave. If the oxide is too thick, hydrogen implantation to the required depth is not possible. Furthermore, silicon dioxide is a poor thermal conductor and so it cannot be made thicker. Therefore, the prior insulators are not suitable for next generation devices with more stringent harmonic requirements, such as for 5G mobile communications.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2201241.3 | Jan 2022 | GB | national |
